Misplaced Pages

#980019

52-606: The A10 (internally, T8010) is built on TSMC's 16 nm FinFET process and contains 3.28 billion transistors (including the GPU and caches) on a die size of 125 mm. It features two Apple-designed 64-bit 2.34 GHz ARMv8-A cores called Hurricane , each with a die size of 4.18 mm. As the first Apple-produced quad-core SoC, it has two high-performance cores designed for demanding tasks like gaming, while also featuring two energy-efficient Apple-designed 64-bit 1.05 GHz cores codenamed Zephyr at 0.78 mm for normal tasks in

104-473: A metal–oxide–semiconductor field-effect transistor (MOSFET) that has more than one gate on a single transistor. The multiple gates may be controlled by a single gate electrode, wherein the multiple gate surfaces act electrically as a single gate, or by independent gate electrodes. A multigate device employing independent gate electrodes is sometimes called a multiple-independent-gate field-effect transistor ( MIGFET ). The most widely used multi-gate devices are

156-427: A "generational jump in power efficiency" while also offering stable frame rates for graphics, gaming, virtual reality, and multimedia applications. In March 2017, Samsung and eSilicon announced the tapeout for production of a 14 nm FinFET ASIC in a 2.5D package. A tri-gate transistor, also known as a triple-gate transistor, is a type of MOSFET with a gate on three of its sides. A triple-gate transistor

208-446: A 16   nm process, TSMC began production of a 16   nm FinFET process, and Samsung Electronics began production of a 10   nm process. TSMC began production of a 7 nm process in 2017, and Samsung began production of a 5 nm process in 2018. In 2019, Samsung announced plans for the commercial production of a 3   nm GAAFET process by 2021. FD-SOI (Fully Depleted Silicon On Insulator ) has been seen as

260-540: A 1980 patent describing the planar XMOS transistor. Sekigawa fabricated the XMOS transistor with Yutaka Hayashi at the ETL in 1984. They demonstrated that short-channel effects can be significantly reduced by sandwiching a fully depleted silicon-on-insulator (SOI) device between two gate electrodes connected together. The first FinFET transistor type was called a "Depleted Lean-channel Transistor" (DELTA) transistor, which

312-705: A 4 MB L3 cache that services the entire SoC. The new 6-core @ 900 MHz GPU built into the A10 chip is 50% faster while consuming 66% of the power of its A9 predecessor. Further analysis has suggested that Apple has kept the GT7600 used in Apple A9, but replaced portions of the PowerVR based GPU with its own proprietary designs. These changes appear to be using lower half-precision floating-point numbers, allowing for higher-performance and lower power consumption. Embedded in

364-805: A December 2000 paper, used to describe a non-planar, double-gate transistor built on an SOI substrate. In 2006, a team of Korean researchers from the Korea Advanced Institute of Science and Technology (KAIST) and the National Nano Fab Center developed a 3 nm transistor, the world's smallest nanoelectronic device, based on gate-all-around (GAA) FinFET technology. In 2011, Rice University researchers Masoud Rostami and Kartik Mohanram demonstrated that FinFETs can have two electrically independent gates, which gives circuit designers more flexibility to design with efficient, low-power gates. In 2020, Chenming Hu received

416-568: A better analog performance due to a higher intrinsic gain and lower channel length modulation. These advantages translate to lower power consumption and enhanced device performance. Nonplanar devices are also more compact than conventional planar transistors, enabling higher transistor density which translates to smaller overall microelectronics. The primary challenges to integrating nonplanar multigate devices into conventional semiconductor manufacturing processes include: BSIMCMG106.0.0, officially released on March 1, 2012 by UC Berkeley BSIM Group ,

468-600: A configuration similar to the ARM big.LITTLE technology. Unlike most implementations of big.LITTLE, such as the Snapdragon 820 or Exynos 8890, only one core type can be active at a time, either the high-performance or low-power cores, but not both. Thus, the A10 Fusion appears to software and benchmarks as a dual core chip. Apple claims that the high-performance cores are 40% faster than Apple's previous A9 processor and that

520-505: A higher electron mobility than silicon. A gate-all-around (GAA) MOSFET was first demonstrated in 1988, by a Toshiba research team including Fujio Masuoka , Hiroshi Takato, and Kazumasa Sunouchi, who demonstrated a vertical nanowire GAAFET which they called a "surrounding gate transistor" (SGT). Masuoka, best known as the inventor of flash memory , later left Toshiba and founded Unisantis Electronics in 2004 to research surrounding-gate technology along with Tohoku University . In 2006,

572-524: A potential low cost alternative to FinFETs. Commercial production of nanoelectronic FinFET semiconductor memory began in the 2010s. In 2013, SK Hynix began mass-production of 16   nm NAND flash memory, and Samsung Electronics began production of 10   nm multi-level cell (MLC) NAND flash memory. In 2017, TSMC began production of SRAM memory using a 7 nm process. Double-gate A multigate device , multi-gate MOSFET or multi-gate field-effect transistor ( MuGFET ) refers to

SECTION 10

#1732787635981

624-529: A single gate stacked on top of two vertical gates (a single gate wrapped over three sides of the channel), allowing essentially three times the surface area for electrons to travel. Intel reports that their tri-gate transistors reduce leakage and consume far less power than previous transistors. This allows up to 37% higher speed or a power consumption at under 50% of the previous type of transistors used by Intel. Intel explains: "The additional control enables as much transistor current flowing as possible when

676-470: A team of Korean researchers from the Korea Advanced Institute of Science and Technology (KAIST) and the National Nano Fab Center developed a 3 nm transistor, the world's smallest nanoelectronic device, based on gate-all-around (GAA) FinFET technology. GAAFET transistors may make use of high-k/metal gate materials. GAAFETs with up to 7 nanosheets have been demonstrated which allow for improved performance and/or reduced device footprint. The widths of

728-471: A triangle rather than rectangle, and it is speculated that this might be either because a triangle has a higher structural strength and can be more reliably manufactured or because a triangular prism has a higher area-to-volume ratio than a rectangular prism, thus increasing switching performance. In September 2012, GlobalFoundries announced plans to offer a 14-nanometer process technology featuring FinFET three-dimensional transistors in 2014. The next month,

780-428: Is a type of non-planar transistor , or "3D" transistor. It is the basis for modern nanoelectronic semiconductor device fabrication . Microchips utilizing FinFET gates first became commercialized in the first half of the 2010s, and became the dominant gate design at 14 nm , 10 nm and 7 nm process nodes . It is common for a single FinFET transistor to contain several fins, arranged side by side and all covered by

832-496: Is called split transistor . This enables more refined control of the operation of the transistor. Indonesian engineer Effendi Leobandung, while working at the University of Minnesota , published a paper with Stephen Y. Chou at the 54th Device Research Conference in 1996 outlining the benefit of cutting a wide CMOS transistor into many channels with narrow width to improve device scaling and increase device current by increasing

884-431: Is highly scalable due to its sub-lithographic channel length; non-implanted ultra-shallow source and drain extensions; non-epi raised source and drain regions; and gate-last flow. FlexFET is a true double-gate transistor in that (1) both the top and bottom gates provide transistor operation, and (2) the operation of the gates is coupled such that the top gate operation affects the bottom gate operation and vice versa. FlexFET

936-446: Is similar to a GAAFET except for the use of nanosheets instead of nanowires. MBCFET is a word mark (trademark) registered in the U.S. to Samsung Electronics. Samsung plans on mass producing MBCFET transistors at the 3 nm node for its foundry customers. Intel is also developing RibbonFET, a variation of MBCFET "nanoribbon" transistors. Unlike FinFETs, both the width and the number of the sheets can be varied to adjust drive strength or

988-525: Is the first standard model for FinFETs. BSIM-CMG is implemented in Verilog-A . Physical surface-potential-based formulations are derived for both intrinsic and extrinsic models with finite body doping. The surface potentials at the source and drain ends are solved analytically with poly-depletion and quantum mechanical effects. The effect of finite body doping is captured through a perturbation approach. The analytic surface potential solution agrees closely with

1040-518: The Defense Advanced Research Projects Agency (DARPA), which in 1997 awarded a contract to a research group at the University of California, Berkeley to develop a deep sub-micron transistor based on DELTA technology. The group was led by Hisamoto along with TSMC 's Chenming Hu . The team made the following breakthroughs between 1998 and 2004. They coined the term "FinFET" (fin field-effect transistor) in

1092-1099: The Electrotechnical Laboratory , Toshiba , Grenoble INP , Hitachi , IBM , TSMC , UC Berkeley , Infineon Technologies , Intel , AMD , Samsung Electronics , KAIST , Freescale Semiconductor , and others, and the ITRS predicted correctly that such devices will be the cornerstone of sub-32 nm technologies . The primary roadblock to widespread implementation is manufacturability, as both planar and non-planar designs present significant challenges, especially with respect to lithography and patterning. Other complementary strategies for device scaling include channel strain engineering , silicon-on-insulator -based technologies, and high-κ /metal gate materials. Dual-gate MOSFETs are commonly used in very high frequency (VHF) mixers and in sensitive VHF front-end amplifiers. They are available from manufacturers such as Motorola , NXP Semiconductors , and Hitachi . Dozens of multigate transistor variants may be found in

SECTION 20

#1732787635981

1144-694: The FinFET (fin field-effect transistor) and the GAAFET (gate-all-around field-effect transistor), which are non-planar transistors, or 3D transistors . Multi-gate transistors are one of the several strategies being developed by MOS semiconductor manufacturers to create ever-smaller microprocessors and memory cells , colloquially referred to as extending Moore's law (in its narrow, specific version concerning density scaling, exclusive of its careless historical conflation with Dennard scaling ). Development efforts into multigate transistors have been reported by

1196-628: The IEEE Medal of Honor award for his development of the FinFET, which the Institute of Electrical and Electronics Engineers (IEEE) credited with taking transistors to the third dimension and extending Moore's law . The industry's first 25 nanometer transistor operating on just 0.7 volts was demonstrated in December 2002 by TSMC . The "Omega FinFET" design, named after the similarity between

1248-410: The 2-D device simulation results. If the channel doping concentration is low enough to be neglected, computational efficiency can be further improved by a setting a specific flag (COREMOD = 1). All of the important multi-gate (MG) transistor behavior is captured by this model. Volume inversion is included in the solution of Poisson's equation , hence the subsequent I–V formulation automatically captures

1300-451: The A10 is the M10 motion coprocessor . The A10 also includes a new image processor which Apple says has twice the throughput of the prior image processor. The A10 has video codec encoding support for HEVC and H.264 . It has decoding support for HEVC, H.264, MPEG‑4 Part 2 , and Motion JPEG . The A10 is packaged in a new InFO packaging from TSMC which reduces the height of the package. In

1352-651: The Greek letter " Omega " and the shape in which the gate wraps around the source/drain structure, has a gate delay of just 0.39 picosecond (ps) for the N-type transistor and 0.88 ps for the P-type. In 2004, Samsung demonstrated a "Bulk FinFET" design, which made it possible to mass-produce FinFET devices. They demonstrated dynamic random-access memory ( DRAM ) manufactured with a 90   nm Bulk FinFET process. In 2011, Intel demonstrated tri-gate transistors , where

1404-407: The N-type transistor and 0.88 ps for the P-type. In 2004, Samsung Electronics demonstrated a "Bulk FinFET" design, which made it possible to mass-produce FinFET devices. They demonstrated dynamic random-access memory ( DRAM ) manufactured with a 90   nm Bulk FinFET process. In 2006, a team of Korean researchers from the Korea Advanced Institute of Science and Technology (KAIST) and

1456-508: The National Nano Fab Center developed a 3 nm transistor, the world's smallest nanoelectronic device, based on FinFET technology. In 2011, Rice University researchers Masoud Rostami and Kartik Mohanram demonstrated that FINFETs can have two electrically independent gates, which gives circuit designers more flexibility to design with efficient, low-power gates. In 2012, Intel started using FinFETs for its future commercial devices. Leaks suggest that Intel's FinFET has an unusual shape of

1508-419: The amount of current the transistor can drive at a given voltage. The sheets often vary from 8 to 50 nanometers in width. The width of the nanosheets is known as Weff, or effective width. Planar transistors have been the core of integrated circuits for several decades, during which the size of the individual transistors has steadily decreased. As the size decreases, planar transistors increasingly suffer from

1560-419: The drain–source channel is sandwiched between two independently fabricated gate/gate-oxide stacks. The primary challenge in fabricating such structures is achieving satisfactory self-alignment between the upper and lower gates. FlexFET is a planar, independently double-gated transistor with a damascene metal top gate MOSFET and an implanted JFET bottom gate that are self-aligned in a gate trench. This device

1612-415: The effective device width. This structure is what a modern FinFET looks like. Although some device width is sacrificed by cutting it into narrow widths, the conduction of the side wall of narrow fins more than make up for the loss, for tall fins. The device had a 35 nm channel width and 70 nm channel length. The potential of Digh Hisamoto's research on DELTA transistors drew the attention of

Apple A10 - Misplaced Pages Continue

1664-405: The entirety of the fin(s). A 25 nm transistor operating on just 0.7  volt was demonstrated in December 2002 by TSMC (Taiwan Semiconductor Manufacturing Company). The "Omega FinFET" design is named after the similarity between the Greek letter omega (Ω) and the shape in which the gate wraps around the source/drain structure. It has a gate delay of just 0.39  picosecond (ps) for

1716-457: The gate is placed on two, three, or four sides of the channel or wrapped around the channel (gate all around), forming a double or even multi gate structure. These devices have been given the generic name "FinFETs" because the source/drain region forms fins on the silicon surface. The FinFET devices have significantly faster switching times and higher current density than planar CMOS (complementary metal–oxide–semiconductor) technology. FinFET

1768-670: The gate surrounds the channel on three sides, allowing for increased energy efficiency and lower gate delay—and thus greater performance—over planar transistors. Commercially produced chips at 22 nm and below have generally utilised FinFET gate designs (but planar processes do exist down to 18 nm, with 12 nm in development). Intel's tri-gate variant were announced at 22 nm in 2011 for its Ivy Bridge microarchitecture . These devices shipped from 2012 onwards. From 2014 onwards, at 14 nm (or 16 nm) major foundries (TSMC, Samsung, GlobalFoundries ) utilised FinFET designs. In 2013, SK Hynix began commercial mass-production of

1820-455: The left and right sides of the fin. The thickness of the fin (measured in the direction from source to drain) determines the effective channel length of the device. The wrap-around gate structure provides a better electrical control over the channel and thus helps in reducing the leakage current and overcoming other short-channel effects . The first FinFET transistor type was called a "Depleted Lean-channel Transistor" or "DELTA" transistor, which

1872-528: The literature. In general, these variants may be differentiated and classified in terms of architecture (planar vs. non-planar design) and the number of channels/gates (2, 3, or 4). A planar double-gate MOSFET (DGMOS) employs conventional planar (layer-by-layer) manufacturing processes to create double-gate MOSFET (metal–oxide–semiconductor field-effect transistor) devices, avoiding more stringent lithography requirements associated with non-planar, vertical transistor structures. In planar double-gate transistors

1924-463: The nanosheets in GAAFETs is controllable which more easily allows for the adjustment of device characteristics. As of 2020, Samsung and Intel have announced plans to mass produce GAAFET transistors (specifically MBCFET transistors) while TSMC has announced that they will continue to use FinFETs in their 3 nm node, despite TSMC developing GAAFET transistors. A multi-bridge channel FET (MBCFET)

1976-516: The rival company TSMC announced start early or "risk" production of 16 nm FinFETs in November 2013. In March 2014, TSMC announced that it is nearing implementation of several 16 nm FinFETs die-on wafers manufacturing processes : AMD released GPUs using their Polaris chip architecture and made on 14 nm FinFET in June 2016. The company has tried to produce a design to provide

2028-434: The same gate, that act electrically as one. The number of fins can be varied to adjust drive strength and performance, with drive strength increasing with a higher number of fins. The concept of a double-gate thin-film transistor (TFT) was proposed by H. R. Farrah ( Bendix Corporation ) and R. F. Steinberg in 1967. A double-gate MOSFET was later proposed by Toshihiro Sekigawa of the Electrotechnical Laboratory (ETL) in

2080-405: The same package there are also four LPDDR4 RAM chips integrating 2 GB of RAM in the iPhone 7, the iPad 6th generation, and the iPod touch 7th generation, or 3 GB in the iPhone 7 Plus and the iPad 7th generation. FinFET A fin field-effect transistor ( FinFET ) is a multigate device , a MOSFET (metal–oxide–semiconductor field-effect transistor ) built on a substrate where

2132-562: The successor to FinFETs, as they can work at sizes below 7 nm. They were used by IBM to demonstrate 5 nm process technology. GAAFET, also known as a surrounding-gate transistor (SGT), is similar in concept to a FinFET except that the gate material surrounds the channel region on all sides. Depending on design, gate-all-around FETs can have two or four effective gates. Gate-all-around FETs have been successfully characterized both theoretically and experimentally. They have also been successfully etched onto nanowires of InGaAs , which have

Apple A10 - Misplaced Pages Continue

2184-506: The team developed the first N-channel FinFETs and successfully fabricated devices down to a 17   nm process. The following year, they developed the first P-channel FinFETs. They coined the term "FinFET" (fin field-effect transistor) in a December 2000 paper. In current usage the term FinFET has a less precise definition. Among microprocessor manufacturers, AMD , IBM , and Freescale describe their double-gate development efforts as FinFET development, whereas Intel avoids using

2236-451: The term when describing their closely related tri-gate architecture. In the technical literature, FinFET is used somewhat generically to describe any fin-based, multigate transistor architecture regardless of number of gates. It is common for a single FinFET transistor to contain several fins, arranged side by side and all covered by the same gate, that act electrically as one, to increase drive strength and performance. The gate may also cover

2288-487: The transistor is in the 'on' state (for performance), and as close to zero as possible when it is in the 'off' state (to minimize power), and enables the transistor to switch very quickly between the two states (again, for performance)." Intel has stated that all products after Sandy Bridge will be based upon this design. The term tri-gate is sometimes used generically to denote any multigate FET with three effective gates or channels. Gate-all-around FETs (GAAFETs) are

2340-459: The two high-efficiency cores consume 20% of the power of the high performance Hurricane cores; they are used when performing simple tasks, such as checking email. A new performance controller decides in real-time which pair of cores should run for a given task in order to optimize for performance or battery life. The A10 has an L1 cache of 64  KB for data and 64 KB for instructions, an L2 cache of 3  MB shared by both cores, and

2392-478: The undesirable short-channel effect, especially "off-state" leakage current, which increases the idle power required by the device. In a multigate device, the channel is surrounded by several gates on multiple surfaces. Thus it provides better electrical control over the channel, allowing more effective suppression of "off-state" leakage current. Multiple gates also allow enhanced current in the "on" state, also known as drive current. Multigate transistors also provide

2444-704: Was described on May 4, 2011, in San Francisco. It was announced that Intel's factories were expected to make upgrades over 2011 and 2012 to be able to manufacture the Ivy Bridge CPUs. It was announced that the new transistors would also be used in Intel's Atom chips for low-powered devices. Tri-gate fabrication was used by Intel for the non-planar transistor architecture used in Ivy Bridge , Haswell and Skylake processors. These transistors employ

2496-400: Was developed and is manufactured by American Semiconductor, Inc. FinFET (fin field-effect transistor) is a type of non-planar transistor, or "3D" transistor (not to be confused with 3D microchips ). The FinFET is a variation on traditional MOSFETs distinguished by the presence of a thin silicon "fin" inversion channel on top of the substrate, allowing the gate to make two points of contact:

2548-542: Was first fabricated by Hitachi Central Research Laboratory 's Digh Hisamoto, Toru Kaga, Yoshifumi Kawamoto and Eiji Takeda in 1989. In the late 1990s, Digh Hisamoto began collaborating with an international team of researchers on further developing DELTA technology, including TSMC 's Chenming Hu and a UC Berkeley research team including Tsu-Jae King Liu , Jeffrey Bokor , Xuejue Huang, Leland Chang, Nick Lindert, S. Ahmed, Cyrus Tabery, Yang-Kyu Choi, Pushkar Ranade, Sriram Balasubramanian, A. Agarwal and M. Ameen. In 1998,

2600-641: Was first demonstrated in 1987, by a Toshiba research team including K. Hieda, Fumio Horiguchi and H. Watanabe. They realized that the fully depleted (FD) body of a narrow bulk Si -based transistor helped improve switching due to a reduced body-bias effect. In 1992, a triple-gate MOSFET was demonstrated by IBM researcher Hon-Sum Wong. Intel announced this technology in September 2002. Intel announced "triple-gate transistors" which maximize "transistor switching performance and decreases power-wasting leakage". A year later, in September 2003, AMD announced that it

2652-546: Was first fabricated in Japan by Hitachi Central Research Laboratory 's Digh Hisamoto, Toru Kaga, Yoshifumi Kawamoto and Eiji Takeda in 1989. The gate of the transistor can cover and electrically contact the semiconductor channel fin on both the top and the sides or only on the sides. The former is called a tri-gate transistor and the latter a double-gate transistor . A double-gate transistor optionally can have each side connected to two different terminal or contacts. This variant

SECTION 50

#1732787635981

2704-711: Was working on similar technology at the International Conference on Solid State Devices and Materials. No further announcements of this technology were made until Intel's announcement in May 2011, although it was stated at IDF 2011, that they demonstrated a working SRAM chip based on this technology at IDF 2009. On April 23, 2012, Intel released a new line of CPUs, termed Ivy Bridge , which feature tri-gate transistors. Intel has been working on its tri-gate architecture since 2002, but it took until 2011 to work out mass-production issues. The new style of transistor

#980019