52-530: A886 may refer to: Opteron A886 road , Scotland Topics referred to by the same term [REDACTED] This disambiguation page lists articles associated with the title A886 . If an internal link led you here, you may wish to change the link to point directly to the intended article. Retrieved from " https://en.wikipedia.org/w/index.php?title=A886&oldid=970435337 " Category : Disambiguation pages Hidden categories: Short description
104-722: A HyperTransport 3.1 link connecting the two dies. These CPUs updated the multi-socket Opteron platform to use DDR3 memory and increased the maximum HyperTransport link speed from 2.40 GHz (4.80 GT/s) for the Istanbul CPUs to 3.20 GHz (6.40 GT/s). AMD changed the naming scheme for its Opteron models. Opteron 4000 series CPUs on Socket C32 (released July 2010) are dual-socket capable and are targeted at uniprocessor and dual-processor uses. The Opteron 6000 series CPUs on Socket G34 are quad-socket capable and are targeted at high-end dual-processor and quad-processor applications. AMD released Socket 939 Opterons, reducing
156-608: A 45 nm manufacturing process and are similar to the Deneb -based Phenom II X4 CPUs. The Socket AM3 quad-core Opterons are code-named "Suzuka". These CPUs carry model numbers of 1381 (2.50 GHz), 1385 (2.70 GHz), and 1389 (2.90 GHz). Socket AM3+ was introduced in 2011 and is a modification of AM3 for the Bulldozer microarchitecture. Opteron CPUs in the AM3+ package are named Opteron 3xxx. Socket F ( LGA 1207 contacts)
208-545: A common CPU bus than any Intel front-side bus . Intel technologies require each speed range of RAM to have its own interface, resulting in a more complex motherboard layout but with fewer bottlenecks. HTX 3.1 at 26 GB/s can serve as a unified bus for as many as four DDR4 sticks running at the fastest proposed speeds. Beyond that DDR4 RAM may require two or more HTX 3.1 buses diminishing its value as unified transport. HyperTransport comes in four versions—1.x, 2.0, 3.0, and 3.1—which run from 200 MHz to 3.2 GHz. It
260-531: A four-port, 1000 Mbit /s Ethernet router needs a maximum 8000 Mbit/s of internal bandwidth (1000 Mbit/s × 4 ports × 2 directions)—HyperTransport greatly exceeds the bandwidth this application requires. However a 4 + 1 port 10 Gb router would require 100 Gbit/s of internal bandwidth. Add to that 802.11ac 8 antennas and the WiGig 60 GHz standard (802.11ad) and HyperTransport becomes more feasible (with anywhere between 20 and 24 lanes used for
312-966: A lower TDP than a standard Opteron. The suffix SE indicates a top-of-the-line model having a higher TDP than a standard Opteron. Starting from 65 nm fabrication process, the Opteron codenames have been based on Formula 1 hosting cities; AMD has a long term sponsorship with F1's most successful team, Ferrari . Released June 1, 2009. Released March 29, 2010. Released March 29, 2010 Released June 23, 2010 Released June 23, 2010 Released March 20, 2012. Released March 20, 2012. Released November 14, 2011. Released November 14, 2011. Released November 14, 2011. Released November 14, 2011. Released November 14, 2011. Released November 14, 2011. Released December 4, 2012. Released December 4, 2012. Released December 4, 2012 Released December 4, 2012 Direct Connect Architecture HyperTransport ( HT ), formerly known as Lightning Data Transport ,
364-504: A memory architecture similar to the Opteron's for the Intel Core i7 family of processors and their Xeon derivatives. In April 2005, AMD introduced its first multi-core Opterons. At the time, AMD's use of the term multi-core in practice meant dual-core ; each physical Opteron chip contained two processor cores. This effectively doubled the computing performance available to each motherboard processor socket. One socket could then deliver
416-500: A microprocessor using a HyperTransport interface was released by the HyperTransport Consortium. It is known as H yper T ransport e X pansion ( HTX ). Using a reversed instance of the same mechanical connector as a 16-lane PCI Express slot (plus an x1 connector for power pins), HTX allows development of plug-in cards that support direct access to a CPU and DMA to the system RAM . The initial card for this slot
468-412: A module that allows FPGAs to plug directly into the Opteron socket. AMD started an initiative named Torrenza on September 21, 2006, to further promote the usage of HyperTransport for plug-in cards and coprocessors . This initiative opened their "Socket F" to plug-in boards such as those from XtremeData and DRC. A connector specification that allows a slot-based peripheral to have direct connection to
520-434: A packet always contains a command field. Many packets contain a 40-bit address. An additional 32-bit control packet is prepended when 64-bit addressing is required. The data payload is sent after the control packet. Transfers are always padded to a multiple of 32 bits, regardless of their actual length. HyperTransport packets enter the interconnect in segments known as bit times. The number of bit times required depends on
572-594: A response from the receiver in the form of a "target done" response. Reads also require a response, containing the read data. HyperTransport supports the PCI consumer/producer ordering model. HyperTransport also facilitates power management as it is compliant with the Advanced Configuration and Power Interface specification. This means that changes in processor sleep states (C states) can signal changes in device states (D states), e.g. powering off disks when
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#1732776470395624-460: A single system configuration as in one 16-bit link to another CPU and one 8-bit link to a peripheral device, which allows for a wider interconnect between CPUs , and a lower bandwidth interconnect to peripherals as appropriate. It also supports link splitting, where a single 16-bit link can be divided into two 8-bit links. The technology also typically has lower latency than other solutions due to its lower overhead. Electrically, HyperTransport
676-513: A variety of computing benchmarks, the Opteron architecture has demonstrated better multi-processor scaling than the Intel Xeon which did not have a point to point system until QPI and integrated memory controllers with the Nehalem design. This is primarily because adding another Opteron processor increases memory bandwidth, while that is not always the case for Xeon systems, and the fact that
728-496: Is AMD’s second generation of Opteron socket. This socket supports processors such as the Santa Rosa, Barcelona, Shanghai, and Istanbul codenamed processors. the "lidded land grid array " socket adds support for DDR2 SDRAM and improved HyperTransport version 3 connectivity. Physically the socket and processor package are nearly identical, although not generally compatible with socket 1207 FX . Socket G34 (LGA 1944 contacts)
780-443: Is a technology for interconnection of computer processors . It is a bidirectional serial / parallel high- bandwidth , low- latency point-to-point link that was introduced on April 2, 2001. The HyperTransport Consortium is in charge of promoting and developing HyperTransport technology. HyperTransport is best known as the system bus architecture of AMD central processing units (CPUs) from Athlon 64 through AMD FX and
832-479: Is also a DDR or " double data rate " connection, meaning it sends data on both the rising and falling edges of the clock signal . This allows for a maximum data rate of 6400 MT/s when running at 3.2 GHz. The operating frequency is autonegotiated with the motherboard chipset (North Bridge) in current computing. HyperTransport supports an autonegotiated bit width, ranging from 2 to 32 bits per link; there are two unidirectional links per HyperTransport bus. With
884-588: Is capable of 32-bit width links, that width is not currently utilized by any AMD processors. Some chipsets though do not even utilize the 16-bit width used by the processors. Those include the Nvidia nForce3 150, nForce3 Pro 150, and the ULi M1689—which use a 16-bit HyperTransport downstream link but limit the HyperTransport upstream link to 8 bits. There has been some marketing confusion between
936-610: Is defined to enable standardized functional test system interconnection. * AMD Athlon 64 , Athlon 64 FX, Athlon 64 X2 , Athlon X2, Athlon II , Phenom, Phenom II , Sempron , Turion series and later use one 16-bit HyperTransport link. AMD Athlon 64 FX ( 1207 ), Opteron use up to three 16-bit HyperTransport links. Common clock rates for these processor links are 800 MHz to 1 GHz (older single and multi socket systems on 754/939/940 links) and 1.6 GHz to 2.0 GHz (newer single socket systems on AM2+/AM3 links—most newer CPUs using 2.0 GHz). While HyperTransport itself
988-524: Is different from Wikidata All article disambiguation pages All disambiguation pages Opteron Opteron is AMD 's x86 former server and workstation processor line, and was the first processor which supported the AMD64 instruction set architecture (known generically as x86-64 ). It was released on April 22, 2003, with the SledgeHammer core (K8) and was intended to compete in
1040-544: Is less noteworthy, as major RISC architectures (such as SPARC , Alpha , PA-RISC , PowerPC , MIPS ) have been 64-bit for many years. In combining these two capabilities, however, the Opteron earned recognition for its ability to run the vast installed base of x86 applications economically, while simultaneously offering an upgrade path to 64-bit computing . The Opteron processor possesses an integrated memory controller supporting DDR SDRAM , DDR2 SDRAM or DDR3 SDRAM (depending on processor generation). This both reduces
1092-424: Is not the same as standard symmetric multiprocessing ; instead of having one bank of memory for all CPUs, each CPU has its own memory. Thus the Opteron is a Non-Uniform Memory Access (NUMA) architecture. The Opteron CPU directly supports up to an 8-way configuration, which can be found in mid-level servers. Enterprise-level servers use additional (and expensive) routing chips to support more than 8 CPUs per box. In
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#17327764703951144-425: Is one of the third generation of Opteron sockets, along with Socket C32 . This socket supports Magny-Cours Opteron 6100, Bulldozer-based Interlagos Opteron 6200, and Piledriver-based "Abu Dhabi" Opteron 6300 series processors. This socket supports four channels of DDR3 SDRAM (two per CPU die). Unlike previous multi-CPU Opteron sockets, Socket G34 CPUs will function with unbuffered ECC or non-ECC RAM in addition to
1196-421: Is similar to low-voltage differential signaling (LVDS) operating at 1.2 V. HyperTransport 2.0 added post-cursor transmitter deemphasis . HyperTransport 3.0 added scrambling and receiver phase alignment as well as optional transmitter precursor deemphasis. HyperTransport is packet -based, where each packet consists of a set of 32-bit words, regardless of the physical width of the link. The first word in
1248-477: The EPYC server CPUs is a superset of HyperTransport. The HORUS interconnect from Newisys extends this concept to larger clusters. The Aqua device from 3Leaf Systems virtualizes and interconnects CPUs, memory, and I/O. HyperTransport can also be used as a bus in routers and switches . Routers and switches have multiple network interfaces, and must forward data between these ports as fast as possible. For example,
1300-588: The Zen -based CPUs and Vega GPUs which were subsequently released in 2017. On Zen and Zen+ CPUs, the "SDF" data interconnects are run at the same frequency as the DRAM memory clock (MEMCLK), a decision made to remove the latency caused by different clock speeds. As a result, using a faster RAM module makes the entire bus faster. The links are 32-bit wide, as in HT, but 8 transfers are done per cycle (128-bit packets) compared to
1352-501: The front-side bus in their Opteron , Athlon 64 , Athlon II , Sempron 64 , Turion 64 , Phenom , Phenom II and FX families of microprocessors. Another use for HyperTransport is as an interconnect for NUMA multiprocessor computers. AMD used HyperTransport with a proprietary cache coherency extension as part of their Direct Connect Architecture in their Opteron and Athlon 64 FX ( Dual Socket Direct Connect (DSDC) Architecture ) line of processors. Infinity Fabric used with
1404-538: The server and workstation markets, particularly in the same segment as the Intel Xeon processor. Processors based on the AMD K10 microarchitecture (codenamed Barcelona ) were announced on September 10, 2007, featuring a new quad-core configuration. The last released Opteron CPUs are the Piledriver -based Opteron 4300 and 6300 series processors, codenamed "Seoul" and "Abu Dhabi" respectively. In January 2016,
1456-556: The 8000 Series (quad or octo socket-capable). The 1000 Series uses the AM2 socket . The 2000 Series and 8000 Series use Socket F . [1] AMD announced its third-generation quad-core Opteron chips on September 10, 2007 with hardware vendors announcing servers in the following month. Based on a core design codenamed Barcelona , new power and thermal management techniques were planned for the chips. Earlier dual core DDR2 based platforms were upgradeable to quad core chips. The fourth generation
1508-540: The CPU goes to sleep. HyperTransport 3.0 added further capabilities to allow a centralized power management controller to implement power management policies. The primary use for HyperTransport is to replace the Intel-defined front-side bus , which is different for every type of Intel processor. For instance, a Pentium cannot be plugged into a PCI Express bus directly, but must first go through an adapter to expand
1560-514: The Opterons use a switched fabric , rather than a shared bus . In particular, the Opteron's integrated memory controller allows the CPU to access local RAM very quickly. In contrast, multiprocessor Xeon system CPUs share only two common buses for both processor-processor and processor-memory communication. As the number of CPUs increases in a typical Xeon system, contention for the shared bus causes computing efficiency to drop. Intel migrated to
1612-537: The advent of version 3.1, using full 32-bit links and utilizing the full HyperTransport 3.1 specification's operating frequency, the theoretical transfer rate is 25.6 GB /s (3.2 GHz × 2 transfers per clock cycle × 32 bits per link) per direction, or 51.2 GB/s aggregated throughput, making it faster than most existing bus standard for PC workstations and servers as well as making it faster than most bus standards for high-performance computing and networking. Links of various widths can be mixed together in
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1664-527: The associated motherboard chipsets. HyperTransport has also been used by IBM and Apple for the Power Mac G5 machines, as well as a number of modern MIPS systems. The current specification HTX 3.1 remained competitive for 2014 high-speed (2666 and 3200 MT /s or about 10.4 GB/s and 12.8 GB/s) DDR4 RAM and slower (around 1 GB/s [1] similar to high end PCIe SSDs ULLtraDIMM flash RAM) technology —a wider range of RAM speeds on
1716-666: The cost of motherboards for low-end servers and workstations. Except for the fact they have 1 MB L2 cache (versus 512 KB for the Athlon 64) the Socket 939 Opterons are identical to the San Diego and Toledo core Athlon 64s , but are run at lower clock speeds than the cores are capable of, making them more stable. Socket AM2 Opterons are available for servers that only have a single-chip setup. Codenamed Santa Ana, rev. F dual core AM2 Opterons feature 2 × 1 MB L2 cache, unlike
1768-582: The first ARMv8-A based Opteron-branded SoC was released, though it is unclear what, if any, heritage this Opteron-branded product line shares with the original Opteron technology other than intended use in the server space. Opteron combines two important capabilities in a single processor: The first capability is notable because at the time of Opteron's introduction, the only other 64-bit architecture marketed with 32-bit x86 compatibility (Intel's Itanium ) ran x86 legacy-applications only with significant speed degradation. The second capability, by itself,
1820-453: The form Opteron XZYY . For all first, second, and third-generation Opterons, the first digit (the X ) specifies the number of CPUs on the target machine: For Socket F and Socket AM2 Opterons, the second digit (the Z ) represents the processor generation. Presently, only 2 (dual-core, DDR2), 3 (quad-core, DDR2) and 4 (six-core, DDR2) are used. Socket C32 and G34 Opterons use a new four-digit numbering scheme. The first digit refers to
1872-423: The implementation of the AMD K10 microarchitecture. New processors, launched in the third quarter of 2007 (codename Barcelona ), incorporate a variety of improvements, particularly in memory prefetching, speculative loads, SIMD execution and branch prediction , yielding an appreciable performance improvement over K8-based Opterons, within the same power envelope. In 2007 AMD introduced a scheme to characterize
1924-492: The last two digits in the model number (the YY ) indicate the clock frequency of a CPU, a higher number indicating a higher clock frequency. This speed indication is comparable to processors of the same generation if they have the same amount of cores, single-cores and dual-cores have different indications despite sometimes having the same clock frequency. The suffix HE or EE indicates a high-efficiency/energy-efficiency model having
1976-598: The latency penalty for accessing the main RAM and eliminates the need for a separate northbridge chip. In multi-processor systems (more than one Opteron on a single motherboard ), the CPUs communicate using the Direct Connect Architecture over high-speed HyperTransport links. Each CPU can access the main memory of another processor, transparent to the programmer. The Opteron approach to multi-processing
2028-478: The link width. HyperTransport also supports system management messaging, signaling interrupts, issuing probes to adjacent devices or processors, I/O transactions, and general data transactions. There are two kinds of write commands supported: posted and non-posted. Posted writes do not require a response from the target. This is usually used for high bandwidth devices such as uniform memory access traffic or direct memory access transfers. Non-posted writes require
2080-712: The majority of their Athlon 64 X2 cousins which feature 2 × 512 KB L2 cache. These CPUs are given model numbers ranging from 1210 to 1224. AMD introduced three quad-core Opterons on Socket AM2+ for single-CPU servers in 2007. These CPUs are produced on a 65 nm manufacturing process and are similar to the Agena Phenom X4 CPUs. The Socket AM2+ quad-core Opterons are code-named "Budapest". The Socket AM2+ Opterons carry model numbers of 1352 (2.10 GHz), 1354 (2.20 GHz), and 1356 (2.30 GHz). AMD introduced three quad-core Opterons on Socket AM3 for single-CPU servers in 2009. These CPUs are produced on
2132-593: The needed bandwidth). The issue of latency and bandwidth between CPUs and co-processors has usually been the major stumbling block to their practical implementation. Co-processors such as FPGAs have appeared that can access the HyperTransport bus and become integrated on the motherboard. Current generation FPGAs from both main manufacturers ( Altera and Xilinx ) directly support the HyperTransport interface, and have IP Cores available. Companies such as XtremeData, Inc. and DRC take these FPGAs (Xilinx in DRC's case) and create
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2184-414: The number of CPUs in the target machine: Like the previous second and third generation Opterons, the second number refers to the processor generation. "1" refers to AMD K10-based units ( Magny-Cours and Lisbon ), "2" refers to the Bulldozer -based Interlagos , Valencia , and Zurich -based units, and "3" refers to the Piledriver -based Abu Dhabi , Seoul , and Delhi -based units. For all Opterons,
2236-468: The original 2. Electrical changes are made for higher power efficiency. On Zen 2 and Zen 3 CPUs, the IF bus is on a separate clock, either in a 1:1 or a 2:1 ratio to the DRAM clock. This avoids a limitation on desktop platforms where maximum DRAM speeds were in practice limited by the IF speed. The bus width has also been doubled. On Zen 4 and later CPUs, the IF bus is able to run at an asynchronous clock to
2288-420: The performance of two processors, two sockets could deliver the performance of four processors, and so on. Because motherboard costs increase dramatically as the number of CPU sockets increase, multicore CPUs enable a multiprocessing system to be built at lower cost. AMD's model number scheme has changed somewhat in light of its new multicore lineup. At the time of its introduction, AMD's fastest multicore Opteron
2340-464: The power consumption of new processors under "average" daily usage, named average CPU power (ACP). The Opteron X1150 and Opteron X2150 APU are used with the BGA-769 or Socket FT3 . See APU features table For Socket 940 and Socket 939 Opterons, each chip has a three-digit model number, in the form Opteron XYY . For Socket F and Socket AM2 Opterons, each chip has a four-digit model number, in
2392-495: The system. The proprietary front-side bus must connect through adapters for the various standard buses, like AGP or PCI Express. These are typically included in the respective controller functions, namely the northbridge and southbridge . In contrast, HyperTransport is an open specification, published by a multi-company consortium. A single HyperTransport adapter chip will work with a wide spectrum of HyperTransport enabled microprocessors. AMD used HyperTransport to replace
2444-512: The traditional registered ECC RAM. Socket C32 (LGA 1207 contacts) is the other member of the third generation of Opteron sockets. This socket is physically similar to Socket F but is not compatible with Socket F CPUs. Socket C32 uses DDR3 SDRAM and is keyed differently so as to prevent the insertion of Socket F CPUs that can use only DDR2 SDRAM. Like Socket G34, Socket C32 CPUs will be able to use unbuffered ECC or non-ECC RAM in addition to registered ECC SDRAM. The Opteron line saw an update with
2496-401: The use of HT referring to H yper T ransport and the later use of HT to refer to Intel 's Hyper-Threading feature on some Pentium 4 -based and the newer Nehalem and Westmere-based Intel Core microprocessors. Hyper-Threading is officially known as H yper- T hreading T echnology ( HTT ) or HT Technology . Because of this potential for confusion, the HyperTransport Consortium always uses
2548-513: The written-out form: "HyperTransport." Infinity Fabric ( IF ) is a superset of HyperTransport announced by AMD in 2016 as an interconnect for its GPUs and CPUs. It is also usable as interchip interconnect for communication between CPUs and GPUs (for Heterogeneous System Architecture ), an arrangement known as Infinity Architecture . The company said the Infinity Fabric would scale from 30 GB/s to 512 GB/s, and be used in
2600-603: Was announced in June 2009 with the Istanbul hexa-cores. It introduced HT Assist , an additional directory for data location, reducing the overhead for probing and broadcasts. HT Assist uses 1 MB L3 cache per CPU when activated. In March 2010 AMD released the Magny-Cours Opteron 6100 series CPUs for Socket G34 . These are 8- and 12-core multi-chip module CPUs consisting of two four or six-core dies with
2652-531: Was the QLogic InfiniPath InfiniBand HCA. IBM and HP , among others, have released HTX compliant systems. The original HTX standard is limited to 16 bits and 800 MHz. In August 2008, the HyperTransport Consortium released HTX3, which extends the clock rate of HTX to 2.6 GHz (5.2 GT/s, 10.7 GTi, 5.2 real GHz data rate, 3 MT/s edit rate) and retains backwards compatibility. The "DUT" test connector
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#17327764703952704-431: Was the model 875, with two cores running at 2.2 GHz each. AMD's fastest single-core Opteron at this time was the model 252, with one core running at 2.6 GHz. For multithreaded applications, or many single threaded applications, the model 875 would be much faster than the model 252. Second-generation Opterons are offered in three series: the 1000 Series (single socket only), the 2000 Series (dual socket-capable), and
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