66-690: [REDACTED] Look up ASE in Wiktionary, the free dictionary. ASE may refer to: Organisations [ edit ] Academia de Studii Economice (the Economic Sciences Academy), in Bucharest, Romania Admiralty Signal Establishment , a former defense research organization in the UK ASE Group (Advanced Semiconductor Engineering), African School of Economics ,
132-427: A branch delay slot . Unless the branch delay slot is filled by an instruction performing useful work, an nop is substituted. MIPS I branch instructions compare the contents of a GPR (rs) against zero or another GPR (rt) as signed integers and branch if the specified condition is true. Control is transferred to the address computed by shifting the 16-bit offset left by two bits, sign-extending the 18-bit result, and adding
198-402: A load delay slot . The instruction in the load delay slot cannot use the data loaded by the load instruction. The load delay slot can be filled with an instruction that is not dependent on the load; a nop is substituted if such an instruction cannot be found. MIPS I has instructions to perform addition and subtraction. These instructions source their operands from two GPRs (rs and rt), and write
264-500: A 32-bit and a 64-bit architecture: MIPS32 and MIPS64. Both were introduced in 1999. MIPS32 is based on MIPS II with some additional features from MIPS III, MIPS IV, and MIPS V; MIPS64 is based on MIPS V. NEC , Toshiba and SiByte (later acquired by Broadcom ) each obtained licenses for MIPS64 as soon as it was announced. Philips , LSI Logic , IDT , Raza Microelectronics, Inc. , Cavium , Loongson Technology and Ingenic Semiconductor have since joined them. MIPS32/MIPS64 Release 5
330-465: A 6-bit opcode. In addition to the opcode, R-type instructions specify three registers, a shift amount field, and a function field; I-type instructions specify two registers and a 16-bit immediate value; J-type instructions follow the opcode with a 26-bit jump target. The following are the three formats used for the core instruction set: MIPS I has instructions that load and store 8-bit bytes, 16-bit halfwords, and 32-bit words. Only one addressing mode
396-476: A certification organization for American and Canadian automotive repair The Association for Science Education , a professional association in the United Kingdom for teachers of science Association for Social Economics , an international association dedicated to social economics Association of Space Explorers , a non-governmental space organization of international astronauts Atomstroyexport ,
462-552: A corresponding microMIPS32/64 version. A processor may implement microMIPS32/64 or both microMIPS32/64 and its corresponding MIPS32/64 subset. Starting with MIPS32/64 Release 6, support for MIPS16e ended, and microMIPS is the only form of code compression in MIPS. The base MIPS32 and MIPS64 architectures can be supplemented with a number of optional architectural extensions, which are collectively referred to as application-specific extensions (ASEs). These ASEs provide features that improve
528-495: A method for extracting chemicals from a matrix Amplified spontaneous emission or superluminescence Advanced silicon etching , a deep reactive ion etching Computing [ edit ] Accredited Solutions Expert , Hewlett Packard Enterprise Company Adaptive Server Enterprise , a database product from Sybase Android Scripting Environment , now known as Scripting Layer for Android Application-specific extensions , supplemental optional architectural extensions in
594-466: A new data type, the Paired Single (PS), which consisted of two single-precision (32-bit) floating-point numbers stored in the existing 64-bit floating-point registers. Variants of existing floating-point instructions for arithmetic, compare and conditional move were added to operate on this data type in a SIMD fashion. New instructions were added for loading, rearranging and converting PS data. It
660-415: A pair of 32-bit registers called HI and LO, since they may execute separately from (and concurrently with) the other CPU instructions. For multiplication, the high- and low-order halves of the 64-bit product is written to HI and LO (respectively). For division, the quotient is written to LO and the remainder to HI. To access the results, a pair of instructions (Move from HI and Move from LO) is provided to copy
726-645: A private university located in Benin Agence spatiale européenne , the French name for European Space Agency Alliance to Save Energy , a non-profit coalition in Washington, D.C., US Amalgamated Society of Engineers American Society of Echocardiography Amity School of Engineering , a private engineering college located in Noida, India The National Institute for Automotive Service Excellence ,
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#1732771999268792-410: Is a 64-bit version of the original shift instructions, used to specify constant shift distances of 0–31 bits. The second version is similar to the first, but adds 32 10 the shift amount field's value so that constant shift distances of 32–63 bits can be specified. The third version obtains the shift distance from the six low-order bits of a GPR. MIPS III added a supervisor privilege level in between
858-516: Is a family of reduced instruction set computer (RISC) instruction set architectures (ISA) developed by MIPS Computer Systems, now MIPS Technologies , based in the United States . There are multiple versions of MIPS, including MIPS I, II, III, IV, and V, as well as five releases of MIPS32/64 (for 32- and 64-bit implementations, respectively). The early MIPS architectures were 32-bit; 64-bit versions were developed later. As of April 2017,
924-539: Is denoted by the .d suffix. MIPS II removed the load delay slot and added several sets of instructions. For shared-memory multiprocessing, the Synchronize Shared Memory , Load Linked Word , and Store Conditional Word instructions were added. A set of Trap-on-Condition instructions were added. These instructions caused an exception if the evaluated condition is true. All existing branch instructions were given branch-likely versions that executed
990-594: Is different from Wikidata All article disambiguation pages All disambiguation pages ASE Too Many Requests If you report this error to the Wikimedia System Administrators, please include the details below. Request from 172.68.168.133 via cp1102 cp1102, Varnish XID 549427548 Upstream caches: cp1102 int Error: 429, Too Many Requests at Thu, 28 Nov 2024 05:33:19 GMT Application-specific extensions MIPS ( Microprocessor without Interlocked Pipelined Stages )
1056-438: Is implementation-defined), to exceed or meet IEEE 754 accuracy requirements (respectively). The FP reciprocal and reciprocal square-root instructions do not comply with IEEE 754 accuracy requirements, and produce results that differ from the required accuracy by one or two units of last place (it is implementation defined). These instructions serve applications where instruction latency is more important than accuracy. MIPS V added
1122-454: Is making the transition to RISC-V . The first version of the MIPS architecture was designed by MIPS Computer Systems for its R2000 microprocessor, the first MIPS implementation. Both MIPS and the R2000 were introduced together in 1985. When MIPS II was introduced, MIPS was renamed MIPS I to distinguish it from the new version. MIPS Computer Systems ' R6000 microprocessor (1989)
1188-472: Is only defined for 32-bit MIPS, but GCC has created a 64-bit variation called O64. For 64-bit, the N64 ABI by Silicon Graphics is most commonly used. The most important improvement is that eight registers are now available for argument passing; it also increases the number of floating-point registers to 32. There is also an ILP32 version called N32, which uses 32-bit pointers for smaller code, analogous to
1254-428: Is supported: base + displacement. Since MIPS I is a 32-bit architecture, loading quantities fewer than 32 bits requires the datum to be either sign-extended or zero-extended to 32 bits. The load instructions suffixed by "unsigned" perform zero extension; otherwise sign extension is performed. Load instructions source the base from the contents of a GPR (rs) and write the result to another GPR (rt). Store instructions source
1320-642: Is the link register . For integer multiplication and division instructions, which run asynchronously from other instructions, a pair of 32-bit registers, HI and LO , are provided. There is a small set of instructions for copying data between the general-purpose registers and the HI/LO registers. The program counter has 32 bits. The two low-order bits always contain zero since MIPS I instructions are 32 bits long and are aligned to their natural word boundaries. Instructions are divided into three types: R (register), I (immediate), and J (jump). Every instruction starts with
1386-683: Is the System Control Coprocessor (an essential part of the processor that is implementation-defined in MIPS I–V), CP1 is an optional floating-point unit (FPU) and CP2/3 are optional implementation-defined coprocessors (MIPS III removed CP3 and reused its opcodes for other purposes). For example, in the PlayStation video game console, CP2 is the Geometry Transformation Engine (GTE), which accelerates
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#17327719992681452-554: The x32 ABI . Both run under the 64-bit mode of the CPU. The N32 and N64 ABIs pass the first eight arguments to a function in the registers $ a0 - $ a7 ; subsequent arguments are passed on the stack. The return value (or a pointer to it) is stored in the registers $ v0 ; a second return value may be stored in $ v1 . In both the N32 and N64 ABIs all registers are considered to be 64-bits wide. A few attempts have been made to replace O32 with
1518-408: The 32-bit sign-extended result to the sum of the program counter (instruction address) and 8 10 . Jumps have two versions: absolute and register-indirect. Absolute jumps ("Jump" and "Jump and Link") compute the address to which control is transferred by shifting the 26-bit instr_index left by two bits and concatenating the 28-bit result with the four high-order bits of the address of the instruction in
1584-449: The CPU and FPU convert single- and double-precision floating-point numbers into doubleword integers and vice versa. MIPS IV is the fourth version of the architecture. It is a superset of MIPS III and is compatible with all existing versions of MIPS. MIPS IV was designed to mainly improve floating-point (FP) performance. To improve access to operands, an indexed addressing mode (base + index, both sourced from GPRs) for FP loads and stores
1650-533: The GPRs and HI/LO registers. For shared-memory multiprocessing, the Load Linked Double Word , and Store Conditional Double Word instructions were added. Existing instructions originally defined to operate on 32-bit words were redefined, where necessary, to sign-extend the 32-bit results to permit words and doublewords to be treated identically by most instructions. Among those instructions redefined
1716-879: The MIPS architecture Applied Systems Engineering ASCII Scene Export, a file format originated in 3D Studio The All-Seeing Eye , an application to help Internet gamers find game servers Publication [ edit ] Anatomical Sciences Education , an academic journal Anglo-Saxon England (journal) , an academic journal Armed Services Editions (ACEs), a paperback book format used during World War II Other uses [ edit ] Aspen–Pitkin County Airport (IATA airport code) American Silver Eagle , an American bullion coin for precious-metal investors International Conference on Automated Software Engineering , an academic conference American Sign Language ISO code See also [ edit ] Ase (disambiguation) Topics referred to by
1782-509: The MIPS architecture has ceased. The company has joined the RISC-V foundation and future processor designs will be based on the RISC-V architecture. In spite of this, some licensees such as Loongson continue with new extension of MIPS-compatible ISAs on their own. In January 2024, Loongson won a case over rights to use MIPS architecture. MIPS is a modular architecture supporting up to four coprocessors (CP0/1/2/3). In MIPS terminology, CP0
1848-502: The MIPS16e ASE. A disadvantage of MIPS16e is that it requires a mode switch before any of its 16-bit instructions can be processed. microMIPS adds versions of the most-frequently used 32-bit instructions that are encoded as 16-bit instructions. This allows programs to intermix 16- and 32-bit instructions without having to switch modes. microMIPS was introduced alongside of MIPS32/64 Release 3, and each subsequent release of MIPS32/64 has
1914-519: The MIPS32 and MIPS64 specifications, as were cache control instructions . For the purpose of cache control, both SYNC and SYNCI instructions were prepared. MIPS32/MIPS64 Release 6 in 2014 added the following: Removed infrequently used instructions: Reorganized the instruction encoding, freeing space for future expansions. The microMIPS32/64 architectures are supersets of the MIPS32 and MIPS64 architectures (respectively) designed to replace
1980-584: The Or Immediate instruction to load a 32-bit immediate into a register. MIPS I has instructions to perform left and right logical shifts and right arithmetic shifts. The operand is obtained from a GPR (rt), and the result is written to another GPR (rd). The shift distance is obtained from either a GPR (rs) or a 5-bit "shift amount" (the "sa" field). MIPS I has instructions for signed and unsigned integer multiplication and division. These instructions source their operands from two GPRs and write their results to
2046-501: The Quantum Effect Devices R5000 (1996) and RM7000 (1998). The R10000, fabricated and sold by NEC Electronics and Toshiba, and its derivatives were used by NEC, Pyramid Technology, Silicon Graphics, and Tandem Computers (among others) in workstations, servers, and supercomputers. The R5000 and R7000 found use in high-end embedded systems, personal computers, and low-end workstations and servers. A derivative of
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2112-816: The R5000 from Toshiba, the R5900, was used in Sony Computer Entertainment's Emotion Engine , which powered its PlayStation 2 game console. Announced on October 21, 1996, at the Microprocessor Forum 1996 alongside the MIPS Digital Media Extensions (MDMX) extension, MIPS V was designed to improve the performance of 3D graphics transformations. In the mid-1990s, a major use of non-embedded MIPS microprocessors were graphics workstations from Silicon Graphics. MIPS V
2178-672: The Russian nuclear power equipment and service export monopoly Auslands- und Spezialeinsätze , a specialised police unit within the Federal Criminal Police Office (Germany) Australian Screen Editors , an Australian film editing guild headquartered in Sydney Automotive Service Excellence , a U.S.-based group to improve the quality of automobile servicing Stock exchanges [ edit ] Ahmedabad Stock Exchange ,
2244-478: The base from the contents of a GPR (rs) and the store data from another GPR (rt). All load and store instructions compute the memory address by summing the base with the sign-extended 16-bit immediate. MIPS I requires all memory accesses to be aligned to their natural word boundaries, otherwise an exception is signaled. To support efficient unaligned memory accesses, there are load/store word instructions suffixed by "left" or "right". All load instructions are followed by
2310-477: The branch delay slot. Register-indirect jumps transfer control to the instruction at the address sourced from a GPR (rs). The address sourced from the GPR must be word-aligned, else an exception is signaled after the instruction in the branch delay slot is executed. Branch and jump instructions that link (except for "Jump and Link Register") save the return address to GPR 31. The "Jump and Link Register" instruction permits
2376-409: The callee needs to save its arguments, but the registers are not stored there by the caller. The return value is stored in register $ v0 ; a second return value may be stored in $ v1 . The ABI took shape in 1990 and was last updated in 1994. This perceived slowness, along with an antique floating-point model with only 16 registers, has encouraged the proliferation of many other calling conventions. It
2442-530: The contents of HI or LO to a GPR. These instructions are interlocked: reads of HI and LO do not proceed past an unfinished arithmetic instruction that will write to HI and LO. Another pair of instructions (Move to HI or Move to LO) copies the contents of a GPR to HI and LO. These instructions are used to restore HI and LO to their original state after exception handling. Instructions that read HI or LO must be separated by two instructions that do not write to HI or LO. All MIPS I control flow instructions are followed by
2508-496: The current version of MIPS is MIPS32/64 Release 6. MIPS32/64 primarily differs from MIPS I–V by defining the privileged kernel mode System Control Coprocessor in addition to the user mode architecture. The MIPS architecture has several optional extensions: MIPS-3D , a simple set of floating-point SIMD instructions dedicated to common 3D tasks; MDMX (MaDMaX), a more extensive integer SIMD instruction set using 64-bit floating-point registers; MIPS16e, which adds compression to
2574-557: The dominant personal computing platform. ARC found little success in personal computers, but the R4000 (and the R4400 derivative) were widely used in workstation and server computers, especially by its largest user, Silicon Graphics . Other uses of the R4000 included high-end embedded systems and supercomputers. MIPS III was eventually implemented by a number of embedded microprocessors. Quantum Effect Design 's R4600 (1993) and its derivatives
2640-415: The efficiency and performance of certain workloads, such as digital signal processing . MIPS has had several calling conventions, especially on the 32-bit platform. The O32 ABI is the most commonly-used ABI, owing to its status as the original System V ABI for MIPS. It is strictly stack-based, with only four registers $ a0 - $ a3 available to pass arguments. Space on the stack is reserved in case
2706-411: The exception handler. MIPS has 32 floating-point registers. Two registers are paired for double precision numbers. Odd numbered registers cannot be used for arithmetic or branching, just as part of a double precision register pair, resulting in 16 usable registers for most instructions (moves/copies and loads/stores were not affected). Single precision is denoted by the .s suffix, while double precision
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2772-505: The existing kernel and user privilege levels. This feature only affected the implementation-defined System Control Processor (Coprocessor 0). MIPS III removed the Coprocessor 3 (CP3) support instructions, and reused its opcodes for the new doubleword instructions. The remaining coprocessors gained instructions to move doublewords between coprocessor registers and the GPRs. The floating general registers (FGRs) were extended to 64 bits and
2838-480: The floating point coprocessor also had several instructions added to it. An IEEE 754-compliant floating-point square root instruction was added. It supported both single- and double-precision operands. A set of instructions that converted single- and double-precision floating-point numbers to 32-bit words were added. These complemented the existing conversion instructions by allowing the IEEE rounding mode to be specified by
2904-402: The instruction in the branch delay slot only if the branch is taken. These instructions improve performance in certain cases by allowing useful instructions to fill the branch delay slot. Doubleword load and store instructions for COP1–3 were added. Consistent with other memory access instructions, these loads and stores required the doubleword to be naturally aligned. The instruction set for
2970-632: The instruction instead of the Floating Point Control and Status Register. MIPS III is a backwards-compatible extension of MIPS II that added support for 64-bit memory addressing and integer operations. The 64-bit data type is called a doubleword, and MIPS III extended the general-purpose registers, HI/LO registers, and program counter to 64 bits to support it. New instructions were added to load and store doublewords, to perform integer addition, subtraction, multiplication, division, and shift operations on them, and to move doubleword between
3036-403: The instruction stream to reduce the space programs take up; and MIPS MT, which adds multithreading capability. Computer architecture courses in universities and technical schools often study the MIPS architecture. The architecture greatly influenced later RISC architectures such as Alpha . In March 2021, MIPS announced that the development of the MIPS architecture had ended as the company
3102-616: The mid-1990s. The first MIPS IV implementation was the MIPS Technologies R8000 microprocessor chipset (1994). The design of the R8000 began at Silicon Graphics, Inc. and it was only used in high-end workstations and servers for scientific and technical applications where high performance on large floating-point workloads was important. Later implementations were the MIPS Technologies R10000 (1996) and
3168-412: The most recent versions of both the 32-bit and 64-bit designs making them available without any licensing or royalty fees as well as granting participants licenses to existing MIPS patents. In March 2019, one version of the architecture was made available under a royalty-free license, but later that year the program was shut down again. In March 2021, Wave Computing announced that the development of
3234-398: The processing of geometry in 3D computer graphics. MIPS is a load/store architecture (also known as a register-register architecture ); except for the load/store instructions used to access memory , all instructions operate on the registers. MIPS I has thirty-two 32-bit general-purpose registers (GPR). Register $ 0 is hardwired to zero and writes to it are discarded. Register $ 31
3300-507: The requirement for instructions to use even-numbered register only was removed. This is incompatible with earlier versions of the architecture; a bit in the floating-point control/status register is used to operate the MIPS III floating-point unit (FPU) in a MIPS I- and II-compatible mode. The floating-point control registers were not extended for compatibility. The only new floating-point instructions added were those to copy doublewords between
3366-562: The result to a third GPR (rd). Alternatively, addition can source one of the operands from a 16-bit immediate (which is sign-extended to 32 bits). The instructions for addition and subtraction have two variants: by default, an exception is signaled if the result overflows; instructions with the "unsigned" suffix do not signal an exception. The overflow check interprets the result as a 32-bit two's complement integer. MIPS I has instructions to perform bitwise logical AND, OR, XOR, and NOR. These instructions source their operands from two GPRs and write
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#17327719992683432-413: The result to a third GPR. By default, the operands are interpreted as signed integers. The variants of these instructions that are suffixed with "unsigned" interpret the operands as unsigned integers (even those that source an operand from the sign-extended 16-bit immediate). The Load Immediate Upper instruction copies the 16-bit immediate into the high-order 16 bits of a GPR. It is used in conjunction with
3498-427: The result to a third GPR. The AND, OR, and XOR instructions can alternatively source one of the operands from a 16-bit immediate (which is zero-extended to 32 bits). The Set on relation instructions write one or zero to the destination register if the specified relation is true or false. These instructions source their operands from two GPRs or one GPR and a 16-bit immediate (which is sign-extended to 32 bits), and write
3564-410: The return address to be saved to any writable GPR. MIPS I has two instructions for software to signal an exception: System Call and Breakpoint. System Call is used by user mode software to make kernel calls; and Breakpoint is used to transfer control to a debugger via the kernel's exception handler. Both instructions have a 20-bit Code field that can contain operating environment-specific information for
3630-403: The same term [REDACTED] This disambiguation page lists articles associated with the title ASE . If an internal link led you here, you may wish to change the link to point directly to the intended article. Retrieved from " https://en.wikipedia.org/w/index.php?title=ASE&oldid=1127625187 " Category : Disambiguation pages Hidden categories: Short description
3696-893: The second oldest exchange in India Alberta Stock Exchange , a defunct stock exchange in Calgary American Stock Exchange , now known as NYSE American Amman Stock Exchange , the Jordanian stock exchange ASE Market Capitalization Weighted Index , a stock index of the Amman Stock Exchange in Jordan. Athens Stock Exchange , the Greek stock exchange Australian Securities Exchange Science and technology [ edit ] Accelerated solvent extraction ,
3762-747: The total to eight. FP comparison and branch instructions were redefined so they could specify which condition bit was written or read (respectively); and the delay slot in between an FP branch that read the condition bit written to by a prior FP comparison was removed. Support for partial predication was added in the form of conditional move instructions for both GPRs and FPRs; and an implementation could choose between having precise or imprecise exceptions for IEEE 754 traps. MIPS IV added several new FP arithmetic instructions for both single- and double-precision FPNs: fused-multiply add or subtract, reciprocal, and reciprocal square-root. The FP fused-multiply add or subtract instructions perform either one or two roundings (it
3828-414: Was Load Word . In MIPS III it sign-extends words to 64 bits. To complement Load Word , a version that zero-extends was added. The R instruction format's inability to specify the full shift distance for 64-bit shifts (its 5-bit shift amount field is too narrow to specify the shift distance for doublewords) required MIPS III to provide three 64-bit versions of each MIPS I shift instruction. The first version
3894-411: Was added, as were prefetch instructions for performing memory prefetching and specifying cache hints (these supported both the base + offset and base + index addressing modes). MIPS IV added several features to improve instruction-level parallelism. To alleviate the bottleneck caused by a single condition bit, seven condition code bits were added to the floating-point control and status register, bringing
3960-538: Was announced on December 6, 2012. According to the Product Marketing Director at MIPS, Release 4 was skipped because the number four is perceived as unlucky in many Asian cultures. In December 2018, Wave Computing, the new owner of the MIPS architecture, announced that MIPS ISA would be open-sourced in a program dubbed the MIPS Open initiative. The program was intended to open up access to
4026-407: Was based on MIPS V and retains all of its features as an optional Coprocessor 1 (FPU) feature called Paired-Single. When MIPS Technologies was spun-out of Silicon Graphics in 1998, it refocused on the embedded market. Through MIPS V, each successive version was a strict superset of the previous version, but this property was found to be a problem, and the architecture definition was changed to define
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#17327719992684092-600: Was completed by the integer-only MDMX extension to provide a complete system for improving the performance of 3D graphics applications. MIPS V implementations were never introduced. On May 12, 1997, Silicon Graphics announced the H1 ("Beast") and H2 ("Capitan") microprocessors. The former was to have been the first MIPS V implementation, and was due to be introduced in the first half of 1999. The H1 and H2 projects were later combined and eventually canceled in 1998. While there have not been any MIPS V implementations, MIPS64 Release 1 (1999)
4158-511: Was introduced in 1999. MIPS Computer Systems ' R4000 microprocessor (1991) was the first MIPS III implementation. It was designed for use in personal, workstation, and server computers. MIPS Computer Systems aggressively promoted the MIPS architecture and R4000, establishing the Advanced Computing Environment (ACE) consortium to advance its Advanced RISC Computing (ARC) standard, which aimed to establish MIPS as
4224-453: Was the first MIPS II implementation. Designed for servers, the R6000 was fabricated and sold by Bipolar Integrated Technology , but was a commercial failure. During the mid-1990s, many new 32-bit MIPS processors for embedded systems were MIPS II implementations because the introduction of the 64-bit MIPS III architecture in 1991 left MIPS II as the newest 32-bit MIPS architecture until MIPS32
4290-437: Was the first instruction set to exploit floating-point SIMD with existing resources. The first release of MIPS32, based on MIPS II, added conditional moves, prefetch instructions , and other features from the R4000 and R5000 families of 64-bit processors. The first release of MIPS64 adds a MIPS32 mode to run 32-bit code. The MUL and MADD ( multiply-add ) instructions, previously available in some implementations, were added to
4356-513: Was widely used in high-end embedded systems and low-end workstations and servers. MIPS Technologies' R4200 (1994), was designed for embedded systems, laptop, and personal computers. A derivative, the R4300i, fabricated by NEC Electronics , was used in the Nintendo 64 game console. The Nintendo 64, along with the PlayStation , were among the highest volume users of MIPS architecture processors in
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