Misplaced Pages

#469530

39-522: [REDACTED] Look up aui in Wiktionary, the free dictionary. AUI may stand for: Ethernet's Attachment Unit Interface , a 15-pin D-connector aUI , a constructed language The ICAO code for Ukraine International Airlines , Ukraine The National Rail code for Ardlui railway station , United Kingdom Associated Universities, Inc .,

78-484: A PHY chip . The MII is standardized by IEEE 802.3u and connects different types of PHYs to MACs. Being media independent means that different types of PHY devices for connecting to different media (i.e. twisted pair , fiber optic , etc.) can be used without redesigning or replacing the MAC hardware. Thus any MAC may be used with any PHY, independent of the network signal transmission medium. The MII can be used to connect

117-622: A MAC to an external PHY using a pluggable connector, or directly to a PHY chip on the same PCB . On older PCs the CNR connector Type B carried MII signals. Network data on the interface is framed using the IEEE Ethernet standard. As such it consists of a preamble, start frame delimiter, Ethernet headers, protocol-specific data and a cyclic redundancy check (CRC). The original MII transfers network data using 4-bit nibbles in each direction (4 transmit data bits, 4 receive data bits). The data

156-484: A network. It contains a bit field with the following information: The transmit clock is a free-running clock generated by the PHY based on the link speed (25 MHz for 100 Mbit/s , 2.5 MHz for 10 Mbit/s ). The remaining transmit signals are driven by the MAC synchronously on the rising edge of TX_CLK. This arrangement allows the MAC to operate without having to be aware of the link speed. The transmit enable signal

195-648: A repeater; this is possible, however, with the National DP83848 which supplies the decoded RX_DV as a supplemental signal in RMII mode. TTL logic levels are used for 5 V or 3.3 V logic. Input high threshold is 2.0 V and low is 0.8 V . The specification states that inputs should be 5 V tolerant, however, some popular chips with RMII interfaces are not 5 V tolerant. Newer devices may support 2.5 V and 1.8 V logic. The RMII signals are treated as lumped signals rather than transmission lines . However,

234-774: A single clock signal recovered from the incoming data. The management interface controls the behavior of the PHY. It has the same set of registers as the MII, except that register #15 is the Extended Status register. The reduced gigabit media-independent interface (RGMII) uses half the number of data pins as are used in the GMII interface. This reduction is achieved by running half as many data lines at double speed, time multiplexing signals and by eliminating non-essential carrier-sense and collision-indication signals. Thus RGMII consists only of 14 pins, as opposed to GMII's 24 to 27. Data

273-461: A synchronous serial data interface similar to I²C . As with I²C, the interface is a multidrop bus so MDC and MDIO can be shared among multiple PHYs. The interface requires 18 signals, out of which only two (MDIO and MDC) can be shared among multiple PHYs. This presents a problem, especially for multiport devices; for example, an eight-port switch using MII would need 8 × 16 + 2 = 130 signals. Reduced media-independent interface (RMII)

312-513: Is a DA-15 ( D-subminiature ) type, where the DTE side has a female connector and the MAU side has a male connector. The connector often uses a sliding clip instead of the typical thumbscrews found on D-connectors, allowing the DTE and MAU to be directly attached, even when their size or shape would not accommodate thumbscrews. However, the clip mechanism is sometimes considered awkward or unreliable. In

351-423: Is a standard which was developed to reduce the number of signals required to connect a PHY to a MAC. Reducing pin count reduces cost and complexity for network hardware especially in the context of microcontrollers with built-in MAC, FPGAs , multiport switches or repeaters, and PC motherboard chipsets. Four things were changed compared to the MII standard to achieve this. These changes mean that RMII uses about half

390-502: Is carried by duplicating data words 100/10 times each, so the clock is always at 625 MHz. The high serial gigabit media-independent interface (HSGMII) is functionally similar to the SGMII but supports link speeds of up to 2.5 Gbit/s . The quad serial gigabit media-independent interface (QSGMII) is a method of combining four SGMII lines into a 5 Gbit/s interface. QSGMII, like SGMII, uses low-voltage differential signaling (LVDS) for

429-401: Is clocked at 25 MHz to achieve 100 Mbit/s throughput. The original MII design has been extended to support reduced signals and increased speeds. Current variants include: The Management Data Input/Output (MDIO) serial bus is a subset of the MII that is used to transfer management information between MAC and PHY. At power up, using autonegotiation , the PHY usually adapts to whatever it

SECTION 10

#1732780324470

468-417: Is clocked on rising and falling edges for 1000 Mbit/s , and on rising edges only for 10/100 Mbit/s . The RX_CTL signal carries RXDV (data valid) on the rising edge, and (RXDV xor RXER) on the falling edge. The TX_CTL signal likewise carries TXEN on rising edge and (TXEN xor TXER) on the falling edge. This is the case for both 1000 Mbit/s and 10/100 Mbit/s . The transmit clock signal is always provided by

507-408: Is clocked out two bits at a time vs 4 bits at a time for MII or 1 bit at a time for SNI ( 10 Mbit/s only). Data is sampled on the rising edge only (i.e. it is not double-pumped ). The REF_CLK operates at 50 MHz in both 100 Mbit/s mode and 10 Mbit/s mode. The transmitting side (PHY or MAC) must keep all signals valid for 10 clock cycles in 10 Mbit/s mode. The receiver (PHY or MAC) samples

546-459: Is connected to unless settings are altered via the MDIO interface. The standard MII features a small set of registers: Register #15 is reserved; registers #16 through #31 are vendor-specific. The registers are used to configure the device and to query the current operating mode. The MII Status Word is the most useful datum, since it may be used to detect whether an Ethernet NIC is connected to

585-590: Is different from Wikidata All article disambiguation pages All disambiguation pages Attachment Unit Interface The IEEE 802.3 specification officially defines the AUI as an interconnect between a DTE and the MAU. However, devices like the DEC Digital Ethernet Local Network Interconnect (DELNI) provided hub-like functionality using AUI-compatible connectors. Additionally, under certain conditions, it

624-405: Is held high during frame transmission and low when the transmitter is idle. Transmit error may be raised for one or more clock periods during frame transmission to request the PHY to deliberately corrupt the frame in some visible way that precludes it from being received as valid. This may be used to abort a frame when some problem is detected after transmission has already started. The MAC may omit

663-457: Is useful for diagnostic and monitoring purposes without impacting the physical medium. The AUI uses Manchester encoding for data transmission, which ensures clock synchronization without requiring a separate timing signal. The data and control circuits operate independently and are self-clocked. Control signals coordinate communication between the DTE and MAU, enabling error signaling, MAU isolation, and medium access requests. An AUI connector

702-514: The Apple Attachment Unit Interface (AAUI) was introduced on Apple Macintosh computers in 1991, and was phased out by 1998. The AUI can operate in both normal mode and monitor mode . In normal mode, it functions as a direct connection between the DTE and the network medium. Monitor mode, an optional feature, isolates the MAU's transmitter from the medium while allowing the DTE to observe network activity. This mode

741-631: The medium access control (MAC) device and the physical layer ( PHY ). The interface operates at speeds up to 1000 Mbit/s , implemented using a data interface clocked at 125 MHz with separate eight-bit data paths for receive and transmit, and is backwards compatible with the MII specification and can operate on fall-back speeds of 10 or 100 Mbit/s . The GMII interface was first defined for 1000BASE-X in IEEE 802.3z-1998 as clause 35, and subsequently incorporated into IEEE 802.3-2000 onwards. There are two transmitter clocks. The clock used depends on whether

780-410: The IEEE version of the related MII standard specifies 68 Ω trace impedance. National recommends running 50 Ω traces with 33 Ω series termination resistors for either MII or RMII mode to reduce reflections. National also suggests that traces be kept under 0.15 m long and matched within 0.05 m on length to minimize skew. The gigabit media-independent interface (GMII) is an interface between

819-624: The MAC on the TXC line. The receive clock signal is always provided by the PHY on the RXC line. Source-synchronous clocking is used: the clock signal that is output (by either the PHY or the MAC) is synchronous with the data signals. This requires the PCB to be designed to add a 1.5–2 ns delay to the clock signal to meet the setup and hold times on the sink. RGMII v2.0 specifies an optional internal delay, obviating

SECTION 20

#1732780324470

858-568: The PHY is operating at gigabit or 10/100 Mbit/s speeds. For gigabit operation, the GTXCLK is supplied to the PHY and the TXD, TXEN, TXER signals are synchronized to this. For 10 or 100 Mbit/s operation, the TXCLK is supplied by the PHY and is used for synchronizing those signals. This operates at either 25 MHz for 100 Mbit/s or 2.5 MHz for 10 Mbit/s connections. In contrast, the receiver uses

897-515: The RMII Consortium specification states that its MDIO/MDC interface is identical to that specified for MII in IEEE 802.3u. Current revisions of IEEE 802.3 specify a standard MDIO/MDC mechanism for negotiating and configuring the link's speed and duplex mode, but it is possible that older PHY devices might have been designed against obsolete versions of the standard, and may therefore use proprietary methods to set speed and duplex. The lack of

936-640: The RX_ER signal which is not connected on some MACs (such as multiport switches) is dealt with by data replacement on some PHYs to invalidate the CRC . The missing COL signal is derived from AND-ing together the TX_EN and the decoded CRS signal from the CRS_DV line in half duplex mode. This means a slight modification of the definition of CRS: On MII, CRS is asserted for both Rx and Tx frames; on RMII only for Rx frames. This has

975-528: The TX and RX data, and a single LVDS clock signal. QSGMII uses significantly fewer signal lines than four separate SGMII connections. QSGMII predates NBASE-T and is used to connect multi-port PHYs to MACs, for example in network routers. The PSGMII (penta serial gigabit media-independent interface) uses the same signal lines as QSGMII, but operates at 6.25 Gbit/s , which supports five 1 gigabit/s ports through one MII. 10 gigabit media-independent interface (XGMII)

1014-424: The case of incompatible fittings, the jackposts or sliding clip can be unscrewed and replaced, or adapter dongles and cables can be used. Electrically, the AUI's differential signals are designed for use with a 78 Ω cable and can transmit data between DTE and MAU at 10 Mbps over the standard's specified 50-meter length. AUI drivers and receivers are required to tolerate wiring faults without permanent impairment of

1053-403: The consequence that on RMII the two error conditions no carrier and lost carrier cannot be detected, and it is difficult or impossible to support shared media such as 10BASE2 or 10BASE5 . Since the RMII standard neglected to stipulate that TX_EN should only be sampled on alternate clock cycles, it is not symmetric with CRS_DV and two RMII PHY devices cannot be connected back to back to form

1092-886: The corporation that operates the National Radio Astronomy Observatory (NRAO) Amiga User International , a monthly magazine dedicated to the Amiga computer Al Akhawayn University , a university located in Ifrane, Morocco Adaptive user interface Audible user interface, for blind people to use digital devices Attentive user interface Gold monoiodide , chemical formula AuI See also [ edit ] [REDACTED] Search for "aui" on Misplaced Pages. All pages with titles containing Aui All pages with titles beginning with AUI All pages with titles beginning with aui AUIS (disambiguation) Topics referred to by

1131-491: The frame starts, but must do so in time to ensure the "start of frame delimiter" byte is included in the received data. Some of the preamble nibbles may be lost. Similar to transmit, raising RX_ER outside a frame is used for special signalling. For receive, two data values are defined: 0b0001 to indicate the link partner is in EEE low power mode, and 0b1110 for a false carrier indication. The CRS and COL signals are asynchronous to

1170-484: The input signals only every ten cycles in 10 Mbit/s mode. There is no signal which defines whether the interface is in full or half duplex mode, but both the MAC and the PHY need to agree. This must instead be communicated over the serial MDIO/MDC interface. There is also no signal which defines whether the interface is in 10 or 100 Mbit/s mode, so this must also be handled using the MDIO/MDC interface. Version 1.2 of

1209-586: The introduction of Fast Ethernet , the AUI interface became obsolete and was replaced by the Media Independent Interface (MII). Subsequent Ethernet standards, such as Gigabit Ethernet and 10 Gigabit Ethernet , introduced the GMII and XGMII interfaces, respectively. A 10 Gigabit Ethernet interface, known as XAUI , was developed to extend the operational distance of XGMII and reduce the number of interface signals. A smaller variant called

AUI - Misplaced Pages Continue

1248-753: The need for the PCB designer to add delay; this is known as RGMII-ID. RGMII version 1.3 uses 2.5V CMOS, whereas RGMII version 2 uses 1.5V HSTL . The serial gigabit media-independent interface (SGMII) is a variant of MII used for Gigabit Ethernet but can also carry 10/100 Mbit/s Ethernet. It uses differential pairs at 625 MHz clock frequency DDR for TX and RX data and TX and RX clocks. It differs from GMII by its low-power and low pin-count 8b/10b -coded SerDes . Transmit and receive path each use one differential pair for data and another differential pair for clock. The TX/RX clocks must be generated on device output but are optional on device input ( clock recovery may be used alternatively). 10/100 Mbit/s Ethernet

1287-463: The number of signals compared to MII. MDC and MDIO can be shared among multiple PHYs. The receiver signals are referenced to the REF_CLK, same as the transmitter signals. This interface requires 9 signals, versus MII's 18. Of those 9, on multiport devices, MDIO, MDC, and REF_CLK may be shared leaving 6 or 7 pins per port. RMII requires a 50 MHz clock where MII requires a 25 MHz clock and data

1326-408: The pair. Signal jitter is controlled to within 1.5 nanoseconds across the interface. The DA-15 pinout is specified by the IEEE 802.3 standard and describes four differential pairs: Media Independent Interface The media-independent interface ( MII ) was originally defined as a standard interface to connect a Fast Ethernet (i.e., 100 Mbit/s ) medium access control (MAC) block to

1365-513: The receive clock, and are only meaningful in half-duplex mode. Carrier sense is high when transmitting, receiving, or the medium is otherwise sensed as being in use. If a collision is detected, COL also goes high while the collision persists. In addition, the MAC may weakly pull-up the COL signal, allowing the combination of COL high with CRS low (which a PHY will never produce) to serve as indication of an absent/disconnected PHY. MDC and MDIO constitute

1404-403: The same term [REDACTED] This disambiguation page lists articles associated with the title AUI . If an internal link led you here, you may wish to change the link to point directly to the intended article. Retrieved from " https://en.wikipedia.org/w/index.php?title=AUI&oldid=1159745191 " Category : Disambiguation pages Hidden categories: Short description

1443-480: The signal if it has no use for this functionality, in which case the signal should be tied low for the PHY. More recently, raising transmit error outside frame transmission is used to indicate the transmit data lines are being used for special-purpose signalling. Specifically, the data value 0b0001 (held continuously with TX_EN low and TX_ER high) is used to request an EEE -capable PHY to enter low power mode. The first seven receiver signals are entirely analogous to

1482-418: The transmitter signals, except RX_ER is not optional and used to indicate the received signal could not be decoded to valid data. The receive clock is recovered from the incoming signal during frame reception. When no clock can be recovered (i.e. when the medium is silent), the PHY must present a free-running clock as a substitute. The receive data valid signal (RX_DV) is not required to go high immediately when

1521-488: Was possible to directly connect two AUI devices without the need for transceivers using a crossover cable . AUI connectors became increasingly rare in the early 1990s as computers and hubs directly integrated the MAU, especially with the rising adoption of the 10BASE-T standard. This shift led to the decline of 10BASE5 (thicknet) and 10BASE2 (thinnet) which made use of the interface. The electrical AUI connection remained internally within equipment for some time. With

#469530