Double Data Rate Synchronous Dynamic Random-Access Memory ( DDR SDRAM ) is a double data rate (DDR) synchronous dynamic random-access memory (SDRAM) class of memory integrated circuits used in computers . DDR SDRAM, also retroactively called DDR1 SDRAM, has been superseded by DDR2 SDRAM , DDR3 SDRAM , DDR4 SDRAM and DDR5 SDRAM . None of its successors are forward or backward compatible with DDR1 SDRAM, meaning DDR2, DDR3, DDR4 and DDR5 memory modules will not work on DDR1-equipped motherboards , and vice versa.
31-428: GDDR3 SDRAM ( Graphics Double Data Rate 3 SDRAM ) is a type of DDR SDRAM specialized for graphics processing units (GPUs) offering less access latency and greater device bandwidths. Its specification was developed by ATI Technologies in collaboration with DRAM vendors including Elpida Memory , Hynix Semiconductor , Infineon (later Qimonda ) and Micron . It was later adopted as a JEDEC standard. It has much
62-420: A 1 GB memory module are usually organized as 2 8-bit words, commonly expressed as 64M×8. Memory manufactured in this way is low-density RAM and is usually compatible with any motherboard specifying PC3200 DDR-400 memory. DDR (DDR1) was superseded by DDR2 SDRAM , which had modifications for a higher clock frequency and again doubled throughput, but operates on the same principle as DDR. Competing with DDR2
93-611: A correct match. Most DDR SDRAM operates at a voltage of 2.5 V, compared to 3.3 V for SDRAM. This can significantly reduce power consumption. Chips and modules with the DDR-400/PC-3200 standard have a nominal voltage of 2.6 V. JEDEC Standard No. 21–C defines three possible operating voltages for 184 pin DDR, as identified by the key notch position relative to its centreline. Page 4.5.10-7 defines 2.5V (left), 1.8V (centre), TBD (right), while page 4.20.5–40 nominates 3.3V for
124-466: A corresponding increase in clock frequency. One advantage of keeping the clock frequency low is that it reduces the signal integrity requirements on the circuit board connecting the memory to the controller. The name "double data rate" refers to the fact that a DDR SDRAM with a certain clock frequency achieves nearly twice the bandwidth of a SDR SDRAM running at the same clock frequency, due to this double pumping. With data being transferred 64 bits at
155-590: A quantity. The name is derived from the first two letters of the original SI prefixes followed by bi (short for binary ). It also clarifies that the SI prefixes are used only to mean powers of 10 and never powers of 2. These units are often used in a manner inconsistent with the IEC standard. Kilobit per second (symbol kbit/s or kb/s , often abbreviated "kbps") is a unit of data transfer rate equal to: Megabit per second (symbol Mbit/s or Mb/s , often abbreviated "Mbps")
186-567: A time, DDR SDRAM gives a transfer rate (in bytes/s) of (memory bus clock rate) × 2 (for dual rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus, with a bus frequency of 100 MHz, DDR SDRAM gives a maximum transfer rate of 1600 MB/s . In the late 1980s IBM invented DDR SDRAM, they built a dual-edge clocking RAM and presented their results at the International Solid-State Circuits Convention in 1990. Samsung released
217-428: Is DDR SDRAM designed to operate at 200 MHz using DDR-400 chips with a bandwidth of 3,200 MB/s. Because PC3200 memory transfers data on both the rising and falling clock edges, its effective clock rate is 400 MHz. 1 GB PC3200 non-ECC modules are usually made with 16 512 Mbit chips, 8 on each side (512 Mbits × 16 chips) / (8 bits (per byte)) = 1,024 MB. The individual chips making up
248-808: Is a common belief that number of module ranks equals number of sides. As above data shows, this is not true. One can also find 2-side/1-rank modules. One can even think of a 1-side/2-rank memory module having 16(18) chips on single side ×8 each, but it is unlikely such a module was ever produced. From Ballot JCB-99-70, and modified by numerous other Board Ballots, formulated under the cognizance of Committee JC-42.3 on DRAM Parametrics. Standard No. 79 Revision Log: "This comprehensive standard defines all required aspects of 64Mb through 1Gb DDR SDRAMs with X4/X8/X16 data interfaces, including features, functionality, ac and dc parametrics, packages and pin assignments. This scope will subsequently be expanded to formally apply to x32 devices, and higher density devices as well." PC3200
279-539: Is a product of bits per chip and number of chips. It also equals number of ranks (rows) multiplied by DDR memory bus width. Consequently, a module with a greater number of chips or using ×8 chips instead of ×4 will have more ranks. This example compares different real-world server memory modules with a common size of 1 GB. One should definitely be careful buying 1 GB memory modules, because all these variations can be sold under one price position without stating whether they are ×4 or ×8, single- or dual-ranked. There
310-405: Is a product of one chip's capacity and the number of chips. ECC modules multiply it by 8 ⁄ 9 because they use 1 bit per byte (8 bits) for error correction. A module of any particular size can therefore be assembled either from 32 small chips (36 for ECC memory), or 16(18) or 8(9) bigger ones. DDR memory bus width per channel is 64 bits (72 for ECC memory). Total module bit width
341-428: Is a unit of data transfer rate equal to: Gigabit per second (symbol Gbit/s or Gb/s , often abbreviated "Gbps") is a unit of data transfer rate equal to: Terabit per second (symbol Tbit/s or Tb/s , sometimes abbreviated "Tbps") is a unit of data transfer rate equal to: These units are often not used in the suggested ways; see § Variations . kilobyte per second ( kB/s ) (sometimes abbreviated "kBps")
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#1732793745122372-564: Is available at effective transfer rates of 400 MHz and higher. DDR3 advances extended the ability to preserve internal clock rates while providing higher effective transfer rates by again doubling the prefetch depth. The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as 16 banks, 4 bank groups with 4 banks for each bank group for ×4/×8 and 8 banks, 2 bank groups with 4 banks for each bank group for ×16 DRAM. The DDR4 SDRAM uses an 8 n prefetch architecture to achieve high-speed operation. The 8 n prefetch architecture
403-672: Is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR4 SDRAM consists of a single 8 n -bit-wide 4-clock data transfer at the internal DRAM core and 8 corresponding n -bit-wide half-clock-cycle data transfers at the I/O pins. RDRAM was a particularly expensive alternative to DDR SDRAM, and most manufacturers dropped its support from their chipsets. DDR1 memory's prices substantially increased from Q2 2008, while DDR2 prices declined. In January 2009, 1 GB DDR1
434-522: Is manufactured are also standardized by JEDEC. There is no architectural difference between DDR SDRAM modules. Modules are instead designed to run at different clock frequencies: for example, a PC-1600 module is designed to run at 100 MHz , and a PC-2100 is designed to run at 133 MHz . A module's clock speed designates the data rate at which it is guaranteed to perform, hence it is guaranteed to run at lower ( underclocking ) and can possibly run at higher ( overclocking ) clock rates than those for which it
465-437: Is the average number of bits ( bitrate ), characters or symbols ( baudrate ), or data blocks per unit time passing through a communication link in a data-transmission system. Common data rate units are multiples of bits per second (bit/s) and bytes per second (B/s). For example, the data rates of modern residential high-speed Internet connections are commonly expressed in megabits per second (Mbit/s). The ISQ symbols for
496-474: The kilobyte in its binary sense . In the context of data rates, however, typically only decimal prefixes are used, and they have their standard SI interpretation. In 1999, the IEC published Amendment 2 to " IEC 60027-2 : Letter symbols to be used in electrical technology – Part 2: Telecommunications and electronics". This standard, approved in 1998, introduced the prefixes kibi-, mebi-, gibi-, tebi-, pebi-, and exbi- to be used in specifying binary multiples of
527-490: The DDR SDRAM interface makes higher transfer rates possible through more strict control of the timing of the electrical data and clock signals. Implementations often have to use schemes such as phase-locked loops and self-calibration to reach the required timing accuracy. The interface uses double pumping (transferring data on both the rising and falling edges of the clock signal ) to double data bus bandwidth without
558-469: The I/O pins. Corresponding to the 4n-prefetch a single write or read access consists of a 128 bit wide, one-clock-cycle data transfer at the internal memory core and four corresponding 32 bit wide, one-half-clock-cycle data transfers at the I/O Pins. Single-ended unidirectional Read and Write Data strobes are transmitted simultaneously with Read and Write data respectively in order to capture data properly at
589-532: The bit and byte are bit and B , respectively. In the context of data-rate units, one byte consists of 8 bits, and is synonymous with the unit octet . The abbreviation bps is often used to mean bit/s, so that when a 1 Mbps connection is advertised, it usually means that the maximum achievable bandwidth is 1 Mbit/s (one million bits per second), which is 0.125 MB/s ( megabyte per second ), or about 0.1192 MiB/s ( mebibyte per second ). The Institute of Electrical and Electronics Engineers (IEEE) uses
620-752: The card's predecessor, the GeForce 5950 Ultra . ATI began using the memory on its Radeon X800 cards. GDDR3 was Sony 's choice for the PlayStation 3 gaming console's graphics memory, although its nVidia based GPU is also capable of accessing the main system memory, which consists of XDR DRAM designed by Rambus Incorporated (Similar technology is marketed by nVidia as TurboCache in PC platform GPUs). Microsoft 's Xbox 360 has 512 MB of GDDR3 memory. Nintendo 's Wii also contains 64 MB of GDDR3 memory. DDR SDRAM Compared to single data rate ( SDR ) SDRAM,
651-602: The effective clock rates of DDR2 are higher than DDR, the overall performance was not greater in the early implementations, primarily due to the high latencies of the first DDR2 modules. DDR2 started to be effective by the end of 2004, as modules with lower latencies became available. Memory manufacturers stated that it was impractical to mass produce DDR1 memory with effective transfer rates in excess of 400 MHz (i.e. 400 MT/s and 200 MHz external clock) due to internal speed limitations. DDR2 picks up where DDR1 leaves off, utilizing internal clock rates similar to DDR1, but
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#1732793745122682-483: The first commercial DDR SDRAM chip (64 Mbit ) in June 1998, followed soon after by Hyundai Electronics (now SK Hynix ) the same year. DDR SDRAM specification was finalized by JEDEC in June 2000 (JESD79). JEDEC has set standards for the data rates of DDR SDRAM, divided into two parts. The first specification is for memory chips, and the second is for memory modules. The first retail PC motherboard using DDR SDRAM
713-719: The physical placement of chips on the module. All ranks are connected to the same memory bus (address + data). The chip select signal is used to issue commands to specific rank. Adding modules to the single memory bus creates additional electrical load on its drivers. To mitigate the resulting bus signaling rate drop and overcome the memory bottleneck , new chipsets employ the multi-channel architecture. Note: All items listed above are specified by JEDEC as JESD79F. All RAM data rates in-between or above these listed specifications are not standardized by JEDEC – often they are simply manufacturer optimizations using tighter tolerances or overvolted chips. The package sizes in which DDR SDRAM
744-563: The receivers of both the Graphics SDRAM and the controller. Data strobes are organized per byte of the 32 bit wide interface. Despite being designed by ATI , the first card to use the technology was nVidia 's GeForce FX 5700 Ultra in early 2004, where it replaced the GDDR2 chips used up to that time. The next card to use GDDR3 was nVidia's GeForce 6800 Ultra , where it was key in maintaining reasonable power requirements compared to
775-428: The right notch position. The orientation of the module for determining the key notch position is with 52 contact positions to the left and 40 contact positions to the right. Increasing the operating voltage slightly can increase maximum speed but at the cost of higher power dissipation and heating, and at the risk of malfunctioning or damage. Module and chip characteristics are inherently linked. Total module capacity
806-578: The same technological base as DDR2 , but the power and heat dispersal requirements have been reduced somewhat, allowing for higher performance memory modules, and simplified cooling systems. GDDR3 is not related to the JEDEC DDR3 specification. This memory uses internal terminators , enabling it to better handle certain graphics demands. To improve throughput, GDDR3 memory transfers 4 bits of data per pin in 2 clock cycles . The GDDR3 interface transfers two 32 bit wide data words per clock cycle from
837-627: The symbol b for bit. In both the SI and ISQ, the prefix k stands for kilo , meaning 1000, while Ki is the symbol for the binary prefix kibi- , meaning 1024. The binary prefixes were introduced in 1998 by the International Electrotechnical Commission (IEC) and in IEEE 1541-2002 which was reaffirmed on 27 March 2008. The letter K is often used as a non-standard abbreviation for 1,024, especially in "KB" to mean KiB,
868-425: Was Rambus XDR DRAM . DDR2 dominated due to cost and support factors. DDR2 was in turn superseded by DDR3 SDRAM , which offered higher performance for increased bus speeds and new features. DDR3 has been superseded by DDR4 SDRAM , which was first produced in 2011 and whose standards were still in flux (2012) with significant architectural changes. DDR's prefetch buffer depth is 2 (bits), while DDR2 uses 4. Although
899-439: Was 2–3 times more expensive than 1 GB DDR2. MDDR is an acronym that some enterprises use for Mobile DDR SDRAM, a type of memory used in some portable electronic devices, like mobile phones , handhelds , and digital audio players . Through techniques including reduced voltage supply and advanced refresh options, Mobile DDR can achieve greater power efficiency. MB/s In telecommunications , data transfer rate
930-489: Was made. DDR SDRAM modules for desktop computers, dual in-line memory modules (DIMMs) , have 184 pins (as opposed to 168 pins on SDRAM, or 240 pins on DDR2 SDRAM), and can be differentiated from SDRAM DIMMs by the number of notches (DDR SDRAM has one, SDRAM has two). DDR SDRAM for notebook computers, SO-DIMMs , have 200 pins, which is the same number of pins as DDR2 SO-DIMMs. These two specifications are notched very similarly and care must be taken during insertion if unsure of
961-522: Was released in August 2000. To increase memory capacity and bandwidth, chips are combined on a module. For instance, the 64-bit data bus for DIMM requires eight 8-bit chips, addressed in parallel. Multiple chips with common address lines are called a memory rank . The term was introduced to avoid confusion with chip internal rows and banks . A memory module may bear more than one rank. The term sides would also be confusing because it incorrectly suggests