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104-520: The original Duron processors were derived from AMD's mainstream Athlon Thunderbird processors, the primary difference being a reduction in L2 cache size to 64  KB from the Athlon's 256 KB. This was a relatively severe reduction, making it even smaller than the 128 KB L2 available on Intel's competing budget Celeron line. However, the originating Thunderbird architecture already featured one of

208-618: A 64 KB (one segment) stack in memory supported by computer hardware . Only words (two bytes) can be pushed to the stack. The stack grows toward numerically lower addresses, with SS:SP pointing to the most recently pushed item. There are 256 interrupts , which can be invoked by both hardware and software. The interrupts can cascade, using the stack to store the return address . The original Intel 8086 and 8088 have fourteen 16- bit registers. Four of them (AX, BX, CX, DX) are general-purpose registers (GPRs), although each may have an additional purpose; for example, only CX can be used as

312-507: A Radeon Graphics processor was introduced in 2019 as AMD's highest-performance entry-level processor. Athlon comes from the Ancient Greek ἆθλον ( athlon ), meaning "(sport) contest", or "prize of a contest", or "place of a contest; arena". With the Athlon name originally used for AMD's high-end processors, AMD currently uses Athlon for budget APUs with integrated graphics. AMD positions the Athlon against its rival,

416-579: A backward compatible version of this functionality on the same microprocessor as the main processor. In addition to this, modern x86 designs also contain a SIMD -unit (see SSE below) where instructions can work in parallel on (one or two) 128-bit words, each containing two or four floating-point numbers (each 64 or 32 bits wide respectively), or alternatively, 2, 4, 8 or 16 integers (each 64, 32, 16 or 8 bits wide respectively). The presence of wide SIMD registers means that existing x86 processors can load or store up to 128 bits of memory data in

520-500: A 1.2 GHz Athlon 4 and a 950 MHz Duron. The Mobile Athlon 4 processors included the PowerNow! function, which controlled a laptop's "level of processor performance by dynamically adjusting its operating frequency and voltage according to the task at hand", thus extending "battery life by reducing processor power when it isn't needed by applications". Duron chips also included PowerNow! In 2002, AMD released

624-404: A 133 MHz (FSB 266) bus. Enthusiast groups quickly discovered these Durons to be rebadged "Thoroughbred B" cores with 192 KiB (¾) of L2 cache disabled and possibly defective. With a basic CPU OPGA package configuration modification, it was found that "Appalbred" Durons could be turned into "Thoroughbred B" Athlon XPs, with full 256 KiB cache, with a very high success rate. However, this

728-508: A 180 nm process. The Athlon's CPU cache consisted of the typical two levels. Athlon was the first x86 processor with a 128  KB split level-1 cache; a 2-way associative cache separated into 2×64 KB for data and instructions (a concept from Harvard architecture ). SRAM cache designs at the time were incapable of keeping up with the Athlon's clock scalability, resulting in compromised CPU performance in some computers. With later Athlon models, AMD would integrate

832-518: A blend of thoroughbred and Barton , was a later variant of the Barton with half of the L2 cache disabled. The Barton was used to officially introduce a higher 400 MT/s bus clock for the Socket ;A platform, which was used to gain some Barton models more efficiency. By this point with the Barton , the four-year-old Athlon EV6 bus architecture had scaled to its limit and required

936-539: A counter with the loop instruction. Each can be accessed as two separate bytes (thus BX's high byte can be accessed as BH and low byte as BL). Two pointer registers have special roles: SP (stack pointer) points to the "top" of the stack , and BP (base pointer) is often used to point at some other place in the stack, typically above the local variables (see frame pointer ). The registers SI, DI, BX and BP are address registers , and may also be used for array indexing. One of four possible 'segment registers' (CS, DS, SS and ES)

1040-586: A large L1 cache with a slower region (the L2) and a fast region (the L1), making the L2 cache into basically a victim cache . With the new cache design, need for high L2 performance and size was lessened, and the simpler L2 cache was less likely to cause clock scaling and yield issues. Thunderbird also moved to a 16-way associative layout. The Thunderbird was "cherished by many for its overclockability" and proved commercially successful, as AMD's most successful product since

1144-476: A major change to the architecture referred to as X86S (formerly known as X86-S). The S in X86S stands for "simplification", which aims to remove support for legacy execution modes and instructions. A processor implementing this proposal would start execution directly in long mode and would only support 64-bit operating systems. 32-bit code would only be supported for user applications running in ring 3, and would use

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1248-547: A memory location. However, this memory operand may also be the destination (or a combined source and destination), while the other operand, the source, can be either register or immediate. Among other factors, this contributes to a code size that rivals eight-bit machines and enables efficient use of instruction cache memory. The relatively small number of general registers (also inherited from its 8-bit ancestors) has made register-relative addressing (using small immediate offsets) an important method of accessing operands, especially on

1352-560: A more complex micro-op which fits the execution model better and thus can be executed faster or with fewer machine resources involved. Another way to try to improve performance is to cache the decoded micro-operations, so the processor can directly access the decoded micro-operations from a special cache, instead of decoding them again. Intel followed this approach with the Execution Trace Cache feature in their NetBurst microarchitecture (for Pentium 4 processors) and later in

1456-455: A new HyperTransport bus. Notably, the 2500+ Barton with 11× multiplier was effectively identical to the 3200+ part other than the FSB speed it was binned for, meaning that seamless overclocking was possible more often than not. Early Thortons could be restored to the full Barton specification with the enabling of the other half of the L2 cache from a slight CPU surface modification, but the result

1560-748: A redesign to exceed the performance of newer Intel processors. By 2003, the Pentium ;4 had become more than competitive with AMD's processors, and Barton only saw a small performance increase over the Thoroughbred-B it derived from, insufficient to outperform the Pentium ;4. The K7-derived Athlons such as Barton were replaced in September 2003 by the Athlon ;64 family, which featured an on-chip memory controller and

1664-455: A result, it featured a few important enhancements, namely full Intel SSE support, enlarged TLBs, hardware data prefetch, and an integrated thermal diode. Like the "Palomino" core, "Morgan" was also expected to reduce heat dissipation; however in "Morgan"'s case this did not happen due to its increased core voltage. A third-generation Duron, the "Appaloosa" core, was announced in the 2001-2002 AMD Processor Roadmap, to enter production in 2002; this

1768-457: A significant performance loss. The net result was that the budget Duron "Spitfire" CPU was roughly only 10% slower than an equivalently clocked (and significantly more expensive) Athlon "Thunderbird". The Duron line was pin-compatible and operated on the same motherboards as the Athlon line, requiring only a BIOS update in most cases. The original Duron was introduced with a 100 MHz (effectively 200 MHz) front-side bus  –

1872-670: A single instruction and also perform bitwise operations (although not integer arithmetic ) on full 128-bits quantities in parallel. Intel's Sandy Bridge processors added the Advanced Vector Extensions (AVX) instructions, widening the SIMD registers to 256 bits. The Intel Initial Many Core Instructions implemented by the Knights Corner Xeon Phi processors, and the AVX-512 instructions implemented by

1976-445: A top speed of 600MHz." A number of features helped the chips compete with Intel. By working with Motorola, AMD had been able to refine copper interconnect manufacturing about one year before Intel, with the revised process permitting 180-nanometer processor production. The accompanying die-shrink resulted in lower power consumption, permitting AMD to increase Athlon clock speeds to the 1 GHz range. The Athlon architecture also used

2080-504: A traditional pin-grid array (PGA) format that plugged into a socket (" Socket A ") on the motherboard, or packaged as a Slot A cartridge. The major difference between it and the Athlon Classic was cache design, with AMD adding in 256 KB of on-chip, full-speed exclusive cache. In moving to an exclusive cache design , the L1 cache's contents were not duplicated in the L2, increasing total cache size and functionally creating

2184-618: A version of PowerNow! called Cool'n'Quiet , implemented on the Athlon XP but only adjusting clock speed instead of voltage. In 2002 the Athlon XP-M (Mobile Athlon XP) replaced the Mobile ;Athlon 4 using the newer Thoroughbred core, with Barton cores for full-size notebooks. The Athlon XP-M was also offered in a compact microPGA socket 563 version. Mobile XPs were not multiplier -locked, making them popular with desktop overclockers . The immediate successor to the Athlon XP,

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2288-470: Is allowed for almost all instructions. The largest native size for integer arithmetic and memory addresses (or offsets ) is 16, 32 or 64 bits depending on architecture generation (newer processors include direct support for smaller integers as well). Multiple scalar values can be handled simultaneously via the SIMD unit present in later generations, as described below. Immediate addressing offsets and immediate data may be expressed as 8-bit quantities for

2392-600: Is an out-of-order design, again like previous post-5x86 AMD CPUs. The Athlon utilizes the Alpha 21264 's EV6 bus architecture with double data rate (DDR) technology. AMD ended its long-time handicap with floating point x87 performance by designing a super- pipelined , out-of-order, triple-issue floating-point unit (FPU). Each of its three units could independently calculate an optimal type of instructions with some redundancy, making it possible to operate on more than one floating-point instruction at once. This FPU

2496-463: Is one of the two modes only available in long mode . The addressing modes were not dramatically changed from 32-bit mode, except that addressing was extended to 64 bits, virtual addresses are now sign extended to 64 bits (in order to disallow mode bits in virtual addresses), and other selector details were dramatically reduced. In addition, an addressing mode was added to allow memory references relative to RIP (the instruction pointer ), to ease

2600-708: Is ubiquitous in both stationary and portable personal computers, and is also used in midrange computers , workstations , servers, and most new supercomputer clusters of the TOP500 list. A large amount of software , including a large list of x86 operating systems are using x86-based hardware. Modern x86 is relatively uncommon in embedded systems , however, and small low power applications (using tiny batteries), and low-cost microprocessor markets, such as home appliances and toys, lack significant x86 presence. Simple 8- and 16-bit based architectures are common here, as well as simpler RISC architectures like RISC-V , although

2704-1001: Is underlining x86 as an example of how continuous refinement of established industry standards can resist the competition from completely new architectures. The table below lists processor models and model series implementing various architectures in the x86 family, in chronological order. Each line item is characterized by significantly improved or commercially successful processor microarchitecture designs. At various times, companies such as IBM , VIA , NEC , AMD , TI , STM , Fujitsu , OKI , Siemens , Cyrix , Intersil , C&T , NexGen , UMC , and DM&P started to design or manufacture x86 processors (CPUs) intended for personal computers and embedded systems. Other companies that designed or manufactured x86 or x87 processors include ITT Corporation , National Semiconductor , ULSI System Technology, and Weitek . Such x86 implementations were seldom simple copies but often employed different internal microarchitectures and different solutions at

2808-491: Is used to form a memory address. In the original 8086 / 8088 / 80186 / 80188 every address was built from a segment register and one of the general purpose registers. For example ds:si is the notation for an address formed as [16 * ds + si] to allow 20-bit addressing rather than 16 bits, although this changed in later processors. At that time only certain combinations were supported. The FLAGS register contains flags such as carry flag , overflow flag and zero flag . Finally,

2912-458: The fstsw instruction, and it is common to simply use some of its bits for branching by copying it into the normal FLAGS. In the Intel 80286 , to support protected mode , three special registers hold descriptor table addresses (GDTR, LDTR, IDTR ), and a fourth task register (TR) is used for task switching. The 80287 is the floating-point coprocessor for the 80286 and has the same registers as

3016-403: The 32-bit instruction set of the 80386 . This is due to the fact that this instruction set has become something of a lowest common denominator for many modern operating systems and also probably because the term became common after the introduction of the 80386 in 1985. A few years after the introduction of the 8086 and 8088, Intel added some complexity to its naming scheme and terminology as

3120-525: The 6x86 was significantly faster than the Pentium on integer code. AMD later managed to grow into a serious contender with the K6 set of processors, which gave way to the very successful Athlon and Opteron . There were also other contenders, such as Centaur Technology (formerly IDT ), Rise Technology , and Transmeta . VIA Technologies ' energy efficient C3 and C7 processors, which were designed by

3224-571: The 80186 , 80286 , 80386 and 80486 . Colloquially, their names were "186", "286", "386" and "486". The term is not synonymous with IBM PC compatibility , as this implies a multitude of other computer hardware . Embedded systems and general-purpose computers used x86 chips before the PC-compatible market started , some of them before the IBM PC (1981) debut. As of June 2022 , most desktop and laptop computers sold are based on

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3328-496: The 80486 and all subsequent x86 models, the floating-point processing unit (FPU) is integrated on-chip. The Pentium MMX added eight 64-bit MMX integer vector registers (MM0 to MM7, which share lower bits with the 80-bit-wide FPU stack). With the Pentium III , Intel added a 32-bit Streaming SIMD Extensions (SSE) control/status register (MXCSR) and eight 128-bit SSE floating-point registers (XMM0 to XMM7). Starting with

3432-412: The 8086 microprocessor and its 8-bit-external-bus variant, the 8088 . The 8086 was introduced in 1978 as a fully 16-bit extension of 8-bit Intel's 8080 microprocessor, with memory segmentation as a solution for addressing more memory than can be covered by a plain 16-bit address. The term "x86" came into being because the names of several successors to Intel's 8086 processor end in "86", including

3536-573: The AMD Opteron processor, the x86 architecture extended the 32-bit registers into 64-bit registers in a way similar to how the 16 to 32-bit extension took place. An R -prefix (for "register") identifies the 64-bit registers (RAX, RBX, RCX, RDX, RSI, RDI, RBP, RSP, RFLAGS, RIP), and eight additional 64-bit general registers (R8–R15) were also introduced in the creation of x86-64 . Also, eight more SSE vector registers (XMM8–XMM15) were added. However, these extensions are only usable in 64-bit mode, which

3640-728: The Am386DX-40 ten years earlier. AMD's new fab facility in Dresden increased production for AMD overall and put out Thunderbirds at a fast rate, with the process technology improved by a switch to copper interconnects. After several versions were released in 2000 and 2001 of the Thunderbird, the last Athlon processor using the Thunderbird core was released in 2001 in the summer, at which point speeds were at 1.4 GHz. The locked multipliers of Socket A Thunderbirds could often be disabled through adding conductive bridges on

3744-451: The Athlon 64 is an AMD64-architecture microprocessor produced by AMD, released on September 23, 2003. A number of variations, all named after cities, were released with 90 nm architecture in 2004 and 2005. Versions released in 2007 and 2009 utilized 65 nm architecture. The Athlon 64 X2 was released in 2005 as the first native dual-core desktop CPU designed by AMD using an Athlon 64. The Athlon X2

3848-615: The Athlon X2 was a subsequent family based on the Athlon ;64 X2. Introduced in 2009, Athlon II was a dual-core family of Athlon chips. A USD$ 55 low-power Athlon 200GE with a Radeon graphics processor was introduced in September 2018, sitting under the Ryzen ;3 2200G. This iteration of Athlon used AMD's Zen-based Raven Ridge core, which in turn had debuted in Ryzen with Radeon graphics processors. With

3952-653: The Centaur company, were sold for many years following their release in 2005. Centaur's 2008 design, the VIA Nano , was their first processor with superscalar and speculative execution . It was introduced at about the same time (in 2008) as Intel introduced the Intel Atom , its first "in-order" processor after the P5 Pentium . Many additions and extensions have been added to the original x86 instruction set over

4056-456: The EV6 bus licensed from DEC as its main system bus, allowing AMD to develop its own products without needing to license Intel's GTL+ bus. By the summer of 2000, AMD was shipping Athlons at high volume, and the chips were being used in systems by Gateway , Hewlett-Packard , and Fujitsu Siemens Computers among others. The second-generation Athlon, the Thunderbird, debuted in 2000. AMD released

4160-514: The Intel 8800 ), the Intel 960 , Intel 860 and the Intel/Hewlett-Packard Itanium architecture. However, the continuous refinement of x86 microarchitectures , circuitry and semiconductor manufacturing would make it hard to replace x86 in many segments. AMD's 64-bit extension of x86 (which Intel eventually responded to with a compatible design) and the scalability of x86 chips in the form of modern multi-core CPUs,

4264-652: The Intel Pentium . The first Athlon processor was a result of AMD's development of K7 processors in the 1990s. AMD founder and then-CEO Jerry Sanders aggressively pursued strategic partnerships and engineering talent in the late 1990s, working to build on earlier successes in the PC market with the AMD K6 processor line. One major partnership announced in 1998 paired AMD with semiconductor giant Motorola to co-develop copper-based semiconductor technology , resulting in

Duron - Misplaced Pages Continue

4368-495: The Mobile ;Athlon 4 , a mobile version codenamed Corvette , with the desktop Athlon XP released in the fall. The third-generation Athlon, code-named Palomino , came out on October 9, 2001, as the Athlon XP, with the suffix signifying extreme performance and unofficially referencing Windows XP . Palomino's design used 180 nm fabrication process size. The Athlon XP

4472-568: The Palomino . A revised Thoroughbred core, Thoroughbred-B , added a ninth "metal layer" to the eight-layered Thoroughbred-A , offering improvement in headroom over the A and making it popular for overclocking. Fifth-generation Athlon Barton -core processors were released in early 2003. While not operating at higher clock rates than Thoroughbred -core processors, they featured an increased L2 cache, and later models had an increased 200 MHz (400 MT/s) front side bus. The Thorton core,

4576-458: The Ryzen 3 and Ryzen 5 , the Athlon 200GE had half of the cores but left SMT enabled. It also kept the same 4 MiB L3 cache , but the L2 cache was halved to 1 MiB. In addition, the number of graphics compute units was limited to 3 in the Athlon 200GE, and the chip was multiplier-locked. Despite its limitations, the Athlon 200GE performed competitively against

4680-573: The Thoroughbred core, or T-Bred , on April 17, 2002. The Thoroughbred core marked AMD's first production 130 nm silicon, with smaller die size than its predecessor. There came to be two steppings (revisions) of this core commonly referred to as Tbred-A and Tbred-B . Introduced in June 2002, the initial A version was mostly a direct die shrink of the preceding Palomino core, but did not significantly increase clock speeds over

4784-461: The machine code format was expanded. To provide backward compatibility, segments with executable code can be marked as containing either 16-bit or 32-bit instructions. Special prefixes allow inclusion of 32-bit instructions in a 16-bit segment or vice versa. The 80386 had an optional floating-point coprocessor, the 80387 ; it had eight 80-bit wide registers: st(0) to st(7), like the 8087 and 80287. The 80386 could also use an 80287 coprocessor. With

4888-457: The "iAPX" of the ambitious but ill-fated Intel iAPX 432 processor was tried on the more successful 8086 family of chips, applied as a kind of system-level prefix. An 8086 system, including coprocessors such as 8087 and 8089 , and simpler Intel-specific system chips, was thereby described as an iAPX 86 system. There were also terms iRMX (for operating systems), iSBC (for single-board computers), and iSBX (for multimodule boards based on

4992-624: The 5000-series Intel Pentium-G, displaying similar CPU performance but an advantage in GPU performance. On November 19, 2019, AMD released the Athlon 3000G, with a higher 3.5 GHz core clock and 1100 MHz graphics clock compared to the Athlon 200GE, also with two cores. The main functional difference between the 200GE was the Athlon 3000G's unlocked multiplier, allowing the latter to be overclocked on B450 and X470 motherboards. Zen 2-based Athlon with Radeon Graphics processors, codenamed "Mendocino", were released on September 20, 2022, for

5096-424: The 8086-architecture), all together under the heading Microsystem 80 . However, this naming scheme was quite temporary, lasting for a few years during the early 1980s. Although the 8086 was primarily developed for embedded systems and small multi-user or single-user computers, largely as a response to the successful 8080-compatible Zilog Z80 , the x86 line soon grew in features and processing power. Today, x86

5200-471: The 8087 with the same data formats. With the advent of the 32-bit 80386 processor, the 16-bit general-purpose registers, base registers, index registers, instruction pointer, and FLAGS register , but not the segment registers, were expanded to 32 bits. The nomenclature represented this by prefixing an " E " (for "extended") to the register names in x86 assembly language . Thus, the AX register corresponds to

5304-414: The Athlon 3000G uses Radeon Vega graphics, which are rated as more powerful than the Pentium's Intel UHD Graphics . The AMD Athlon processor launched on June 23, 1999, with general availability by August 1999. Subsequently, from August 1999 until January 2002, this initial K7 processor was the fastest x86 chip in the world. At launch it was, on average, 10% faster than the Pentium III at

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5408-494: The Athlon XP was used to introduce 166/200 MHz FSB (FSB 333/400) speeds. The original Duron, using the "Spitfire" core, was manufactured in 2000 and 2001 at speeds ranging from 600 to 950 MHz. It was based on the 180 nm " Thunderbird " Athlon core. The second-generation Duron, the "Morgan" core, was sold in speed grades between 900 and 1300 MHz, and was based on the 180 nm " Palomino " Athlon XP core. As

5512-483: The Athlon XP the following year, and the Athlon XP's immediate successor, the Athlon 64 , was an AMD64-architecture microprocessor released in 2003. After the 2007 launch of the Phenom processors, the Athlon name was also used for mid-range processors, positioned above brands such as Sempron . The Athlon 64 X2 was released in 2005 as the first native dual-core desktop CPU designed by AMD, and

5616-634: The Decoded Stream Buffer (for Core-branded processors since Sandy Bridge). Transmeta used a completely different method in their Crusoe x86 compatible CPUs. They used just-in-time translation to convert x86 instructions to the CPU's native VLIW instruction set. Transmeta argued that their approach allows for more power efficient designs since the CPU can forgo the complicated decode step of more traditional x86 implementations. Addressing modes for 16-bit processor modes can be summarized by

5720-505: The K7 project being the first commercial processor to utilize copper fabrication technology . In the announcement, Sanders referred to the partnership as creating a "virtual gorilla" that would enable AMD to compete with Intel on fabrication capacity while limiting AMD's financial outlay for new facilities. The K7 design team was led by Dirk Meyer , who had previously worked as a lead engineer at DEC on multiple Alpha microprocessors. When DEC

5824-877: The Knights Landing Xeon Phi processors and by Skylake-X processors, use 512-bit wide SIMD registers. During execution , current x86 processors employ a few extra decoding steps to split most instructions into smaller pieces called micro-operations. These are then handed to a control unit that buffers and schedules them in compliance with x86-semantics so that they can be executed, partly in parallel, by one of several (more or less specialized) execution units . These modern x86 designs are thus pipelined , superscalar , and also capable of out of order and speculative execution (via branch prediction , register renaming , and memory dependence prediction ), which means they may execute multiple (partial or complete) x86 instructions simultaneously, and not necessarily in

5928-746: The L2 cache had to store a duplicate of the data stored in the L1 cache. As a comparison the inclusive design of the Celeron effectively reduced the available size of the Level 2 cache by the size of the Level 1, which resulted in an effective size of 96 KB (128-32) in contrast to the Duron's exclusive design (128+64=192). Consequently, the Duron inherited the Thunderbird's reduction in sensitivity to L2 cache size, allowing AMD to make their L2 cache higher latency and lower bandwidth to lessen processor complexity and allow better manufacturing yields without incurring

6032-408: The L2 cache onto the processor itself, removing dependence on external cache chips. The Slot-A Athlons were the first multiplier-locked CPUs from AMD, preventing users from setting their own desired clock speed. This was done by AMD in part to hinder CPU remarking and overclocking by resellers, which could result in inconsistent performance. Eventually a product called the "Goldfingers device"

6136-434: The advanced but delayed 5k86 ( K5 ), which, internally, was closely based on AMD's earlier 29K RISC design; similar to NexGen 's Nx586 , it used a strategy such that dedicated pipeline stages decode x86 instructions into uniform and easily handled micro-operations , a method that has remained the basis for most x86 designs to this day. Some early versions of these microprocessors had heat dissipation problems. The 6x86

6240-415: The art, had been planned for 2021; as of March 2022 the release had not taken place, however. The instruction set architecture has twice been extended to a larger word size. In 1985, Intel released the 32-bit 80386 (later known as i386) which gradually replaced the earlier 16-bit chips in computers (although typically not in embedded systems ) during the following years; this extended programming model

6344-569: The electronic and physical levels. Quite naturally, early compatible microprocessors were 16-bit, while 32-bit designs were developed much later. For the personal computer market, real quantities started to appear around 1990 with i386 and i486 compatible processors, often named similarly to Intel's original chips. After the fully pipelined i486 , in 1993 Intel introduced the Pentium brand name (which, unlike numbers, could be trademarked ) for their new set of superscalar x86 designs. With

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6448-593: The entry-level laptop market, alongside the more powerful quad-core Ryzen 7020 mobile series under the same codename. Featuring two processing cores, with two threads on Athlon Silver and four threads on Athlon Gold models, Athlon 7020 series mobile processors are equipped with two compute units (CUs) of RDNA 2 graphics. These 7020U series models were followed by the release of Ryzen/Athlon 7020C series for Chromebooks on May 23, 2023. Unlike prior Athlon generations, AMD has not released desktop variants of Mendocino. Raven Ridge (14 nm), Picasso (12 nm) (see

6552-401: The execution units with the decode steps opens up possibilities for more analysis of the (buffered) code stream, and therefore permits detection of operations that can be performed in parallel, simultaneously feeding more than one execution unit. The latest processors also do the opposite when appropriate; they combine certain x86 sequences (such as a compare followed by a conditional jump) into

6656-549: The first two actively produce modern 64-bit designs, leading to what has been called a "duopoly" of Intel and AMD in x86 processors. However, in 2014 the Shanghai-based Chinese company Zhaoxin , a joint venture between a Chinese company and VIA Technologies, began designing VIA based x86 processors for desktops and laptops. The release of its newest "7" family of x86 processors (e.g. KX-7000), which are not quite as fast as AMD or Intel chips but are still state of

6760-528: The formula: Addressing modes for 32-bit x86 processor modes can be summarized by the formula: Addressing modes for the 64-bit processor mode can be summarized by the formula: Instruction relative addressing in 64-bit code (RIP + displacement, where RIP is the instruction pointer register ) simplifies the implementation of position-independent code (as used in shared libraries in some operating systems). The 8086 had 64 KB of eight-bit (or alternatively 32 K-word of 16-bit ) I/O space, and

6864-399: The frequently occurring cases or contexts where a −128..127 range is enough. Typical instructions are therefore 2 or 3 bytes in length (although some are much longer, and some are single-byte). To further conserve encoding space, most registers are expressed in opcodes using three or four bits, the latter via an opcode prefix in 64-bit mode, while at most one operand to an instruction can be

6968-501: The implementation of position-independent code , used in shared libraries in some operating systems. SIMD registers XMM0–XMM15 (XMM0–XMM31 when AVX-512 is supported). SIMD registers YMM0–YMM15 (YMM0–YMM31 when AVX-512 is supported). Lower half of each of the YMM registers maps onto the corresponding XMM register. SIMD registers ZMM0–ZMM31. Lower half of each of the ZMM registers maps onto

7072-408: The instruction pointer (IP) points to the next instruction that will be fetched from memory and then executed; this register cannot be directly accessed (read or written) by a program. The Intel 80186 and 80188 are essentially an upgraded 8086 or 8088 CPU, respectively, with on-chip peripherals added, and they have the same CPU registers as the 8086 and 8088 (in addition to interface registers for

7176-456: The largest L1 caches at 128 KB (which was not reduced in the Duron) and also introduced AMD's switch to an exclusive cache design which effectively unified the L1 and L2 caches. Because of this, the Duron behaved as if it had a high speed 128 KB cache combined with a somewhat slower 64 KB segment giving an effective 192 KB cache, versus the traditional inclusive cache design where

7280-422: The list article for more details) Mendocino (6 nm) (see the list article for more details) A number of supercomputers have been built using Athlon chips, largely at universities. Among them: X86 x86 (also known as 80x86 or the 8086 family ) is a family of complex instruction set computer (CISC) instruction set architectures initially developed by Intel based on

7384-447: The lower 16 bits of the new 32-bit EAX register, SI corresponds to the lower 16 bits of ESI, and so on. The general-purpose registers, base registers, and index registers can all be used as the base in addressing modes, and all of those registers except for the stack pointer can be used as the index in addressing modes. Two new segment registers (FS and GS) were added. With a greater number of registers, instructions and operands,

7488-473: The name EM64T and finally using Intel 64. Microsoft and Sun Microsystems / Oracle also use term "x64", while many Linux distributions , and the BSDs also use the "amd64" term. Microsoft Windows, for example, designates its 32-bit versions as "x86" and 64-bit versions as "x64", while installation files of 64-bit Windows versions are required to be placed into a directory called "AMD64". In 2023, Intel proposed

7592-454: The peripherals). The 8086, 8088, 80186, and 80188 can use an optional floating-point coprocessor, the 8087 . The 8087 appears to the programmer as part of the CPU and adds eight 80-bit wide registers, st(0) to st(7), each of which can hold numeric data in one of seven formats: 32-, 64-, or 80-bit floating point, 16-, 32-, or 64-bit (binary) integer, and 80-bit packed decimal integer. It also has its own 16-bit status register accessible through

7696-475: The processor to service both front-side bus requests and cache accesses simultaneously, as compared to pushing everything through the front-side bus. The Argon-based Athlon contained 22 million transistors and measured 184 mm . It was fabricated by AMD in a version of their CS44E process, a 250 nm complementary metal–oxide–semiconductor (CMOS) process with six levels of aluminium interconnect . "Pluto" and "Orion" Athlons were fabricated in

7800-535: The processor to the motherboard . The cartridge assembly allowed the use of higher-speed cache memory modules than could be put on (or reasonably bundled with) motherboards at the time. Similar to the Pentium II and the Katmai-based Pentium ;III, the Athlon Classic contained 512 KB of L2 cache. This high-speed SRAM cache was run at a divisor of the processor clock and was accessed via its own 64-bit back-side bus , allowing

7904-406: The release, AMD began using the Athlon brand name to refer to "low-cost, high-volume products", in a situation similar to both Intel's Celeron and Pentium Gold. The modern Athlon 3000G was introduced in 2019 and was positioned as AMD's highest-performance entry-level processor. AMD positions the Athlon against its rival, the Intel Pentium . While CPU processing performance is in the same ballpark,

8008-403: The same as the then current Socket A Athlons. Later with the introduction of motherboard chipsets offering higher FSB speeds of 133 MHz (FSB 266) and AMD's matching introduction of Athlon "C" processors supporting this speed, the Duron initially retained the 100 MHz FSB for purposes of market segmentation . Later Durons were given official support for 133 MHz bus operation only after

8112-468: The same clock for business applications and 20% faster for gaming workloads. In commercial terms, the Athlon "Classic" was an enormous success. The Athlon Classic is a cartridge-based processor, named Slot A and similar to Intel's cartridge Slot 1 used for Pentium II and Pentium III. It used the same, commonly available, physical 242-pin connector used by Intel Slot 1 processors but rotated by 180 degrees to connect

8216-418: The same order as given in the instruction stream. Some Intel CPUs ( Xeon Foster MP , some Pentium 4 , and some Nehalem and later Intel Core processors) and AMD CPUs (starting from Zen ) are also capable of simultaneous multithreading with two threads per core ( Xeon Phi has four threads per core). Some Intel CPUs support transactional memory ( TSX ). When introduced, in the mid-1990s, this method

8320-443: The same simplified segmentation as long mode. The x86 architecture is a variable instruction length, primarily " CISC " design with emphasis on backward compatibility . The instruction set is not typical CISC, however, but basically an extended version of the simple eight-bit 8008 and 8080 architectures. Byte-addressing is enabled and words are stored in memory with little-endian byte order. Memory access to unaligned addresses

8424-454: The stack. Much work has therefore been invested in making such accesses as fast as register accesses—i.e., a one cycle instruction throughput, in most circumstances where the accessed data is available in the top-level cache. A dedicated floating-point processor with 80-bit internal registers, the 8087 , was developed for the original 8086 . This microprocessor subsequently developed into the extended 80387 , and later processors incorporated

8528-580: The surface on the chip, a practice widely known as "the pencil trick". Overall, there are four main variants of the Athlon XP desktop CPU: the Palomino , the Thoroughbred , the Thorton , and the Barton . A number of mobile processors were also released, including the Corvette models, and the Dublin model among others. On May 14, 2001, AMD released the Athlon XP processor. It debuted as

8632-430: The x86 architecture family, while mobile categories such as smartphones or tablets are dominated by ARM . At the high end, x86 continues to dominate computation-intensive workstation and cloud computing segments. In the 1980s and early 1990s, when the 8088 and 80286 were still in common use, the term x86 usually represented any 8086-compatible CPU. Today, however, x86 usually implies binary compatibility with

8736-490: The x86 naming scheme now legally cleared, other x86 vendors had to choose different names for their x86-compatible products, and initially some chose to continue with variations of the numbering scheme: IBM partnered with Cyrix to produce the 5x86 and then the very efficient 6x86 (M1) and 6x86 MX ( MII ) lines of Cyrix designs, which were the first x86 microprocessors implementing register renaming to enable speculative execution . AMD meanwhile designed and manufactured

8840-432: The x86-compatible VIA C7 , VIA Nano , AMD 's Geode , Athlon Neo and Intel Atom are examples of 32- and 64-bit designs used in some relatively low-power and low-cost segments. There have been several attempts, including by Intel, to end the market dominance of the "inelegant" x86 architecture designed directly from the first simple 8-bit microprocessors. Examples of this are the iAPX 432 (a project originally named

8944-459: The years following its introduction and the withdrawal of the Duron line from the market, the spelling "Appalbred" gradually became replaced by the phonetically similar "Applebred", as "Appaloosa" and the etymology of "Appalbred" were mostly forgotten. Duron was often a favorite of computer builders looking for performance while on a tight budget. In 2003, the "Appalbred" Duron was available in 1.4 GHz, 1.6 GHz and 1.8 GHz grades, all on

9048-484: The years, almost consistently with full backward compatibility . The architecture family has been implemented in processors from Intel, Cyrix , AMD , VIA Technologies and many other companies; there are also open implementations, such as the Zet SoC platform (currently inactive). Nevertheless, of those, only Intel, AMD, VIA Technologies, and DM&P Electronics hold x86 architectural licenses, and from these, only

9152-415: Was a 130 nm "Thoroughbred" Athlon XP with only 64 KiB (¼) of L2 cache enabled. The name "Appalbred" was a portmanteau of "Appaloosa" and "Thoroughbred", much like the contemporary "Thorton" Athlon XP, a "Barton" with only 256 KiB (½) of L2 cache enabled, was a portmanteau of "Thoroughbred" and "Barton". Neither "Appalbred" nor "Thorton" ever appeared on an official AMD processor roadmap. In

9256-494: Was a huge step forward for AMD, helping compete with Intel's P6 FPU. The 3DNow! floating-point SIMD technology, again present, received some revisions and was renamed "Enhanced 3DNow!" Additions included DSP instructions and the extended MMX subset of Intel SSE . The second-generation Athlon, the Thunderbird or T-Bird , debuted on June 4, 2000. This version of the Athlon was available in

9360-450: Was a subsequent family of microprocessors based on the Athlon 64 X2. The original Brisbane  Athlon X2 models used 65 nm architecture and were released in 2007. Athlon II is a family of central processing units. Initially a dual-core version of the Athlon II, the K-10 -based Regor was released in June 2009 with 45-nanometer architecture. This

9464-537: Was also affected by a few minor compatibility problems, the Nx586 lacked a floating-point unit (FPU) and (the then crucial) pin-compatibility, while the K5 had somewhat disappointing performance when it was (eventually) introduced. Customer ignorance of alternatives to the Pentium series further contributed to these designs being comparatively unsuccessful, despite the fact that the K5 had very good Pentium compatibility and

9568-607: Was created that could unlock the CPU. AMD designed the CPU with more robust x86 instruction decoding capabilities than that of K6, to enhance its ability to keep more data in-flight at once. The critical branch-predictor unit was enhanced compared to the K6. Deeper pipelining with more stages allowed higher clock speeds to be attained. Like the AMD K5 and K6, the Athlon dynamically buffered internal micro-instructions at runtime resulting from parallel x86 instruction decoding. The CPU

9672-586: Was followed by a single-core version Sargas , followed by the quad-core Propus , the triple-core Rana in November 2009, and the Llano 32 nm version released in 2011. Various Steamroller-based Athlon X4 and X2 FM2+ socketed processors were released in 2014 and the years after. The preceding Piledriver-based Athlon X4 and X2 processors were released before 2014, and are socket compatible with both FM2+ and FM2 mainboards. The Bristol Ridge Athlon X4 lineup

9776-423: Was marketed using a performance rating (PR) system comparing it to the Thunderbird predecessor core. Among other changes, Palomino consumed 20% less power than the Thunderbird, comparatively reducing heat output, and was roughly 10% faster than Thunderbird. Palomino also had enhanced K7's TLB architecture and included a hardware data prefetch mechanism to take better advantage of memory bandwidth. Palomino

9880-487: Was not always reliable. Barton (130 nm) Thorton (130 nm) The Palomino core debuted in the mobile market before the PC market in May 2001, where it was branded as Mobile Athlon 4 with the codename "Corvette". It distinctively used a ceramic interposer much like the Thunderbird instead of the organic pin grid array package used on all later Palomino processors. In November 2001, AMD released

9984-454: Was only possible for a period of approximately 4 weeks, as shortly after "Appalbred" was released, AMD made changes to the OPGA package that made these configuration modifications ineffective. Athlon#Athlon Thunderbird Athlon is the brand name applied to a series of x86-compatible microprocessors designed and manufactured by AMD . The original Athlon (now called Athlon Classic)

10088-403: Was originally referred to as the i386 architecture (like its first implementation) but Intel later dubbed it IA-32 when introducing its (unrelated) IA-64 architecture. In 1999–2003, AMD extended this 32-bit architecture to 64 bits and referred to it as x86-64 in early documents and later as AMD64 . Intel soon adopted AMD's architectural extensions under the name IA-32e, later using

10192-534: Was released in 2017. It is based on the Excavator microarchitecture and uses 2 Excavator modules totalling 4 cores. It has a dual-channel DDR4 -2400 memory controller with clock speeds up to 4.0 GHz. It runs on the new Socket AM4 platform that was later used for Zen 1 to Zen 3 CPUs. The Zen -based Athlon with Radeon graphics processors was launched in September 2018 with the Athlon 200GE. Based on AMD's Raven Ridge core previously used in variants of

10296-477: Was sold to Compaq in 1998 and discontinued Alpha processor development, Sanders brought most of the Alpha design team to the K7 project. This added to the previously acquired NexGen K6 team, which already included engineers such as Vinod Dham . The AMD Athlon processor launched on June 23, 1999, with general availability by August 1999. Subsequently, from August 1999 until January 2002, this initial K7 processor

10400-436: Was sometimes referred to as a "RISC core" or as "RISC translation", partly for marketing reasons, but also because these micro-operations share some properties with certain types of RISC instructions. However, traditional microcode (used since the 1950s) also inherently shares many of the same properties; the new method differs mainly in that the translation to micro-operations now occurs asynchronously. Not having to synchronize

10504-474: Was the fastest x86 chip in the world. Wrote the Los Angeles Times on October 5, 1999: "AMD has historically trailed Intel’s fastest processors, but has overtaken the industry leader with the new Athlon. Analysts say the Athlon, which will be used by Compaq , IBM and other manufacturers in their most powerful PCs, is significantly faster than Intel’s flagship Pentium III , which runs at

10608-596: Was the first K7 core to include the full SSE instruction set from the Intel Pentium ;III, as well as AMD's 3DNow! Professional . Palomino was also the first socketed Athlon officially supporting dual processing, with chips certified for that purpose branded as the Athlon MP (multi processing), which had different specifications. According to HardwareZone , it was possible to modify the Athlon XP to function as an MP. The fourth-generation of Athlon was introduced with

10712-600: Was the first seventh-generation x86 processor and the first desktop processor to reach speeds of one gigahertz (GHz). It made its debut as AMD's high-end processor brand on June 23, 1999. Over the years AMD has used the Athlon name with the 64-bit Athlon 64 architecture, the Athlon II , and Accelerated Processing Unit (APU) chips targeting the Socket AM1 desktop SoC architecture, and Socket AM4 Zen (microarchitecture) . The modern Zen-based Athlon with

10816-424: Was to be manufactured with AMD’s upcoming 130 nm process . Despite rumors of early limited circulation however, "Appaloosa"-based Durons never reached the market, and by the end of 2001, "Appaloosa" had been removed from the roadmap. Instead of the canceled "Appaloosa" core, the Duron line eventually saw a final generation in 2003, in the form of the "Appalbred" core (later typically misspelled as "Applebred"), which

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