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65-464: Development of the EPROM memory cell started with investigation of faulty integrated circuits where the gate connections of transistors had broken. Stored charge on these isolated gates changes their threshold voltage . In 1957, Frosch and Derick were able to manufacture the first silicon dioxide field effect transistors at Bell Labs , the first transistors in which drain and source were adjacent at

130-482: A 3 μm process . The HM6147 chip was able to match the performance of the fastest NMOS memory chip at the time, while the HM6147 also consumed significantly less power. With comparable performance and much less power consumption, the twin-well CMOS process eventually overtook NMOS as the most common semiconductor manufacturing process for computer memory in the 1980s. The two most common types of DRAM memory cells since

195-454: A "signature mode", allowing the manufacturer and device to be identified by the EPROM programmer. It was implemented by forcing +12 V on pin A9 and reading out two bytes of data. However, as this was not universal, programmer software also would allow manual setting of the manufacturer and device type of the chip to ensure proper programming. Memory cell (computing) The memory cell

260-480: A +25 V pulse in Programming mode. The n-MOS technology evolution introduced single-rail V CC = +5 V power supply and single V PP = +25 V programming voltage without pulse in the third generation. The unneeded V BB and V DD pins were reused for additional address bits allowing larger capacities (2716/2732) in the same 24-pin package, and even larger capacities with larger packages. Later

325-543: A 16K (2K word × 8) bit Intel 2816 chip with a thin silicon dioxide layer, which was less than 200 Å . In 1980, this structure was publicly introduced as FLOTOX ; floating gate tunnel oxide . The FLOTOX structure improved reliability of erase/write cycles per byte up to 10,000 times. But this device required additional 20–22V V PP bias voltage supply for byte erase, except for 5V read operations. In 1981, Perlegos and 2 other members left Intel to form Seeq Technology , which used on-device charge pumps to supply

390-466: A chip in weeks, and indoor fluorescent lighting over several years. Generally, the EPROMs must be removed from equipment to be erased, since it is not usually practical to build in a UV lamp to erase parts in-circuit. Electrically Erasable Programmable Read-Only Memory (EEPROM) was developed to provide an electrical erase function and has now mostly displaced ultraviolet-erased parts. As the quartz window

455-464: A limited life for erasing and reprogramming, reaching a million operations in modern EEPROMs. In an EEPROM that is frequently reprogrammed, the life of the EEPROM is an important design consideration. Flash memory is a type of EEPROM designed for high speed and high density, at the expense of large erase blocks (typically 512 bytes or larger) and limited number of write cycles (often 10,000). There

520-497: A single-transistor DRAM memory cell. In 1967, Dennard filed a patent for a single-transistor DRAM memory cell, based on MOS technology. The first commercial bipolar 64-bit SRAM was released by Intel in 1969 with the 3101 Schottky TTL . One year later, it released the first DRAM integrated circuit chip, the Intel 1103 , based on MOS technology. By 1972, it beat previous records in semiconductor memory sales. DRAM chips during

585-560: A windowed part used for development to a non-windowed part for production. The first generation 1702 devices were fabricated with the p-MOS technology. They were powered with V CC = V BB = +5 V and V DD = V GG = -9 V in Read mode, and with V DD = V GG = -47 V in Programming mode. The second generation 2704/2708 devices switched to n-MOS technology and to three-rail V CC = +5 V, V BB = -5 V, V DD = +12 V power supply with V PP = 12 V and

650-420: Is always available for reading as an output. The value remains stored until it is changed through the set or reset process. Flip-flops are typically implemented using MOSFETs . Floating-gate memory cells, based on floating-gate MOSFETs , are used for most non-volatile memory (NVM) technologies, including EPROM , EEPROM and flash memory . According to R. Bez and A. Pirovano: A floating-gate memory cell

715-467: Is available. Today, an academic explanation of the FLOTOX device structure can be found in several sources. Nowadays, EEPROM is used for embedded microcontrollers as well as standard EEPROM products. EEPROM still requires a 2-transistor structure per bit to erase a dedicated byte in the memory, while flash memory has 1 transistor per bit to erase a region of the memory. Because EEPROM technology

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780-447: Is basically an MOS transistor with a gate completely surrounded by dielectrics (Fig. 1.2), the floating-gate (FG), and electrically governed by a capacitive-coupled control-gate (CG). Being electrically isolated, the FG acts as the storing electrode for the cell device. Charge injected into the FG is maintained there, allowing modulation of the ‘apparent’ threshold voltage (i.e. VT seen from

845-497: Is built mainly out of DRAM cells; since the layout is much smaller than SRAM, it can be more densely packed yielding cheaper memory with greater capacity. Since the DRAM memory cell stores its value as the charge of a capacitor, and there are current leakage issues, its value must be constantly rewritten. This is one of the reasons that make DRAM cells slower than the larger SRAM (static RAM) cells, which has its value always available. That

910-493: Is completely insulated by the surrounding layers of oxide. A control gate electrode is deposited and further oxide covers it. To retrieve data from the EPROM, the address represented by the values at the address pins of the EPROM is decoded and used to connect one word (usually an 8-bit byte) of storage to the output buffer amplifiers . Each bit of the word is a 1 or 0, depending on the storage transistor being switched on or off, conducting or non-conducting. The switching state of

975-415: Is described in former section, old EEPROMs are based on avalanche breakdown -based hot-carrier injection with high reverse breakdown voltage . But FLOTOX theoretical basis is Fowler–Nordheim tunneling hot-carrier injection through a thin silicon dioxide layer between the floating gate and the wafer. In other words, it uses a tunnel junction . Theoretical basis of the physical phenomenon itself

1040-450: Is expensive to make, OTP (one-time programmable) chips were introduced; here, the die is mounted in an opaque package so it cannot be erased after programming – this also eliminates the need to test the erase function, further reducing cost. OTP versions of both EPROMs and EPROM-based microcontrollers are manufactured. However, OTP EPROM (whether separate or part of a larger chip) is being increasingly replaced by EEPROM for small sizes, where

1105-424: Is exposure to UV light at 253.7 nm of at least 15 Ws/cm, usually achieved in 20 to 30 minutes with the lamp at a distance of about 2.5 cm. Erasure can also be accomplished with X-rays : Erasure, however, has to be accomplished by non-electrical methods, since the gate electrode is not accessible electrically. Shining ultraviolet light on any part of an unpackaged device causes a photocurrent to flow from

1170-478: Is no clear boundary dividing the two, but the term "EEPROM" is generally used to describe non-volatile memory with small erase blocks (as small as one byte) and a long lifetime (typically 1,000,000 cycles). Many past microcontrollers included both (flash memory for the firmware and a small EEPROM for parameters), though the trend with modern microcontrollers is to emulate EEPROM using flash. As of 2020, flash memory costs much less than byte-programmable EEPROM and

1235-485: Is not electrically reversible. To erase the data stored in the array of transistors, ultraviolet light is directed onto the die . Photons of the UV light cause ionization within the silicon oxide, which allows the stored charge on the floating gate to dissipate. Since the whole memory array is exposed, all the memory is erased at the same time. The process takes several minutes for UV lamps of convenient sizes; sunlight would erase

1300-548: Is the basis for modern DRAM. In 1966, Robert H. Dennard at the IBM Thomas J. Watson Research Center was working on MOS memory. While examining the characteristics of MOS technology, he found it was capable of building capacitors , and that storing a charge or no charge on the MOS capacitor could represent the 1 and 0 of a bit, while the MOS transistor could control writing the charge to the capacitor. This led to his development of

1365-447: Is the dominant memory type wherever a system requires a significant amount of non-volatile solid-state storage . EEPROMs, however, are still used on applications that only require small amounts of storage, like in serial presence detect . In the early 1970s, some studies, inventions , and development for electrically re-programmable non-volatile memories were performed by various companies and organizations. In 1971, early research

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1430-530: Is the fundamental building block of computer memory . The memory cell is an electronic circuit that stores one bit of binary information and it must be set to store a logic 1 ( high voltage level) and reset to store a logic 0 (low voltage level). Its value is maintained/stored until it is changed by the set/reset process. The value in the memory cell can be accessed by reading it. Over the history of computing , different memory cell architectures have been used, including core memory and bubble memory . Today ,

1495-503: Is the reason why SRAM memory is used for on- chip cache included in modern microprocessor chips. On December 11, 1946 Freddie Williams applied for a patent on his cathode-ray tube (CRT) storing device ( Williams tube ) with 128 40- bit words. It was operational in 1947 and is considered the first practical implementation of random-access memory (RAM). In that year, the first patent applications for magnetic-core memory were filed by Frederick Viehe. Practical magnetic-core memory

1560-413: Is the same as today's flash memory . But each FLOTOX structure is in conjunction with another read-control transistor because the floating gate itself is just programming and erasing one data bit. Intel's FLOTOX device structure improved EEPROM reliability, in other words, the endurance of the write and erase cycles, and the data retention period. A material of study for single-event effect about FLOTOX

1625-535: Is used for some security gadgets, such as credit cards, SIM cards, key-less entry, etc., some devices have security protection mechanisms, such as copy-protection. EEPROM devices use a serial or parallel interface for data input/output. The common serial interfaces are SPI , I²C , Microwire , UNI/O , and 1-Wire . These use from 1 to 4 device pins and allow devices to use packages with 8 pins or less. A typical EEPROM serial protocol consists of three phases: OP-code phase , address phase and data phase. The OP-code

1690-531: Is usually the first 8 bits input to the serial input pin of the EEPROM device (or with most I²C devices, is implicit); followed by 8 to 24 bits of addressing, depending on the depth of the device, then the read or write data. Each EEPROM device typically has its own set of OP-code instructions mapped to different functions. Common operations on SPI EEPROM devices are: Other operations supported by some EEPROM devices are: Parallel EEPROM devices typically have an 8-bit data bus and an address bus wide enough to cover

1755-515: The Intel 8048 , the Freescale 68HC11 , and the "C" versions of the PIC microcontroller . Like EPROM chips, such microcontrollers came in windowed (expensive) versions that were used for debugging and program development. The same chip came in (somewhat cheaper) opaque OTP packages for production. Leaving the die of such a chip exposed to light can also change behavior in unexpected ways when moving from

1820-536: The 1980s have been trench-capacitor cells and stacked-capacitor cells. Trench-capacitor cells are where holes (trenches) are made in a silicon substrate, whose side walls are used as a memory cell, whereas stacked-capacitor cells are the earliest form of three-dimensional memory (3D memory), where memory cells are stacked vertically in a three-dimensional cell structure. Both debuted in 1984, when Hitachi introduced trench-capacitor memory and Fujitsu introduced stacked-capacitor memory. The floating-gate MOSFET (FGMOS)

1885-767: The CG) of the cell transistor. EEPROM EEPROM or E PROM ( electrically erasable programmable read-only memory ) is a type of non-volatile memory . It is used in computers, usually integrated in microcontrollers such as smart cards and remote keyless systems , or as a separate chip device, to store relatively small amounts of data by allowing individual bytes to be erased and reprogrammed. EEPROMs are organized as arrays of floating-gate transistors . EEPROMs can be programmed and erased in-circuit, by applying special programming signals. Originally, EEPROMs were limited to single-byte operations, which made them slower, but modern EEPROMs allow multi-byte page operations. An EEPROM has

1950-529: The ROMs. Initially, it was thought that the EPROM would be too expensive for mass production use and that it would be confined to development only. It was soon found that small-volume production was economical with EPROM parts, particularly when the advantage of rapid upgrades of firmware was considered. Some microcontrollers , from before the era of EEPROMs and flash memory , use an on-chip EPROM to store their program. Such microcontrollers include some versions of

2015-513: The X-rays). The effects of this process on the reliability of the part would have required extensive testing so they decided on the window instead. EPROMs have a limited but large number of erase cycles; the silicon dioxide around the gates accumulates damage from each cycle, making the chip unreliable after several thousand cycles. EPROM programming is slow compared to other forms of memory. Because higher-density parts have little exposed oxide between

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2080-454: The cell cost isn't too important, and flash for larger sizes. A programmed EPROM retains its data for a minimum of ten to twenty years, with many still retaining data after 35 or more years, and can be read an unlimited number of times without affecting the lifetime. The erasing window must be kept covered with an opaque label to prevent accidental erasure by the UV found in sunlight or camera flashes. Old PC BIOS chips were often EPROMs, and

2145-461: The cell of a reprogrammable ROM (read-only memory). Building on this concept, Dov Frohman of Intel invented EPROM in 1971, and was awarded U.S. patent 3,660,819 in 1972. Frohman designed the Intel 1702, a 2048-bit EPROM, which was announced by Intel in 1971. Each storage location of an EPROM consists of a single field-effect transistor . Each field-effect transistor consists of a channel in

2210-697: The complete memory. Most devices have chip select and write protect pins. Some microcontrollers also have integrated parallel EEPROM. Operation of a parallel EEPROM is simple and fast when compared to serial EEPROM, but these devices are larger due to the higher pin count (28 pins or more) and have been decreasing in popularity in favor of serial EEPROM or flash. EEPROM memory is used to enable features in other types of products that are not strictly memory products. Products such as real-time clocks , digital potentiometers , digital temperature sensors , among others, may have small amounts of EEPROM to store calibration information or other data that needs to be available in

2275-545: The data retention periods and the number of erase/write cycles. Most of the major semiconductor manufactures, such as Toshiba , Sanyo (later, ON Semiconductor ), IBM , Intel , NEC (later, Renesas Electronics ), Philips (later, NXP Semiconductors ), Siemens (later, Infineon Technologies ), Honeywell (later, Atmel ), Texas Instruments , studied, invented, and manufactured some electrically re-programmable non-volatile devices until 1977. The first EEPROM that used Fowler-Nordheim tunnelling to erase data

2340-511: The decreased cost of the CMOS technology allowed the same devices to be fabricated using it, adding the letter "C" to the device numbers (27xx(x) are n-MOS and 27Cxx(x) are CMOS). While parts of the same size from different manufacturers are compatible in read mode, different manufacturers added different and sometimes multiple programming modes leading to subtle differences in the programming process. This prompted larger capacity devices to introduce

2405-447: The early 1970s had three-transistor cells, before single-transistor cells became standard since the mid-1970s. CMOS memory was commercialized by RCA , which launched a 288-bit CMOS SRAM memory chip in 1968. CMOS memory was initially slower than NMOS memory, which was more widely used by computers in the 1970s. In 1978, Hitachi introduced the twin-well CMOS process, with its HM6147 (4   kb SRAM) memory chip, manufactured with

2470-403: The electrons in the floating gate, lowering the window between threshold voltages for zeros vs ones. After sufficient number of rewrite cycles, the difference becomes too small to be recognizable, the cell is stuck in programmed state, and endurance failure occurs. The manufacturers usually specify the maximum number of rewrites being 1 million or more. During storage, the electrons injected into

2535-522: The erasing window was often covered with an adhesive label containing the BIOS publisher's name, the BIOS revision, and a copyright notice. Often this label was foil-backed to ensure its opacity to UV. Erasure of the EPROM begins to occur with wavelengths shorter than 400 nm . Exposure time for sunlight of one week or three years for room fluorescent lighting may cause erasure. The recommended erasure procedure

2600-411: The event of power loss. It was also used on video game cartridges to save game progress and configurations, before the usage of external and internal flash memories. There are two limitations of stored information: endurance and data retention. During rewrites, the gate oxide in the floating-gate transistors gradually accumulates trapped electrons. The electric field of the trapped electrons adds to

2665-409: The field-effect transistor is controlled by the voltage on the control gate of the transistor. Presence of a voltage on this gate creates a conductive channel in the transistor, switching it on. In effect, the stored charge on the floating gate allows the threshold voltage of the transistor to be programmed. Storing data in the memory requires selecting a given address and applying a higher voltage to

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2730-437: The first 64-bit p-channel MOS ( PMOS ) static random-access memory (SRAM). SRAM typically has six- transistor cells, whereas DRAM (dynamic random-access memory) typically has single-transistor cells. In 1965, Toshiba 's Toscal BC-1411 electronic calculator used a form of capacitive bipolar DRAM, storing 180-bit data on discrete memory cells, consisting of germanium bipolar transistors and capacitors. MOS technology

2795-541: The first silicon dioxide field effect transistors at Bell Labs, the first transistors in which drain and source were adjacent at the surface. Subsequently, a team demonstrated a working MOSFET at Bell Labs 1960. The invention of the MOSFET enabled the practical use of metal–oxide–semiconductor (MOS) transistors as memory cell storage elements, a function previously served by magnetic cores . The first modern memory cells were introduced in 1964, when John Schmidt designed

2860-622: The floating gate back to the silicon substrate, thereby discharging the gate to its initial, uncharged condition ( photoelectric effect ). This method of erasure allows complete testing and correction of a complex memory array before the package is finally sealed. Once the package is sealed, information can still be erased by exposing it to X radiation in excess of 5*10 rads , a dose which is easily attained with commercial X-ray generators. In other words, to erase your EPROM, you would first have to X-ray it and then put it in an oven at about 600 degrees Celsius (to anneal semiconductor alterations caused by

2925-462: The floating gate may drift through the insulator, especially at increased temperature, and cause charge loss, reverting the cell into erased state. The manufacturers usually guarantee data retention of 10 years or more. Flash memory is a later form of EEPROM. In the industry, there is a convention to reserve the term EEPROM to byte-wise erasable memories compared to block-wise erasable flash memories. EEPROM occupies more die area than flash memory for

2990-488: The high voltages necessary for programming E PROMs. In 1984, Perlogos left Seeq Technology to found Atmel , then Seeq Technology was acquired by Atmel. Electrically alterable read-only memory (EAROM) is a type of EEPROM that can be modified one or a few bits at a time. Writing is a very slow process and again needs higher voltage (usually around 12 V ) than is used for read access. EAROMs are intended for applications that require infrequent and only partial rewriting. As

3055-513: The implementation technology used, the purpose of the binary memory cell is always the same. It stores one bit of binary information that can be accessed by reading the cell and it must be set to store a 1 and reset to store a 0. Logic circuits without memory cells are called combinational , meaning the output depends only on the present input. But memory is a key element of digital systems . In computers, it allows to store both programs and data and memory cells are also used for temporary storage of

3120-447: The layers of interconnects and gate, ultraviolet erasing becomes less practical for very large memories. Even dust inside the package can prevent some cells from being erased. For large volumes of parts (thousands of pieces or more), mask-programmed ROMs are the lowest cost devices to produce. However, these require many weeks lead time to make, since the artwork or design in an IC mask layer or photomask must be altered to store data on

3185-424: The most common memory cell architecture is MOS memory , which consists of metal–oxide–semiconductor (MOS) memory cells. Modern random-access memory (RAM) uses MOS field-effect transistors (MOSFETs) as flip-flops, along with MOS capacitors for certain types of RAM. The SRAM ( static RAM ) memory cell is a type of flip-flop circuit, typically implemented using MOSFETs. These require very low power to maintain

3250-517: The other hand, is based on floating-gate memory cell architectures. Non-volatile memory technologies such as EPROM , EEPROM , and flash memory utilize floating-gate memory cells, which rely on floating-gate MOSFET transistors. The memory cell is the fundamental building block of memory. It can be implemented using different technologies, such as bipolar , MOS , and other semiconductor devices . It can also be built from magnetic material such as ferrite cores or magnetic bubbles. Regardless of

3315-506: The output of combinational circuits to be used later by digital systems. Logic circuits that use memory cells are called sequential circuits , meaning the output depends not only on the present input, but also on the history of past inputs. This dependence on the history of past inputs makes these circuits stateful and it is the memory cells that store this state. These circuits require a timing generator or clock for their operation. Computer memory used in most contemporary computer systems

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3380-444: The same capacity, because each cell usually needs a read, a write, and an erase transistor , while flash memory erase circuits are shared by large blocks of cells (often 512×8). Newer non-volatile memory technologies such as FeRAM and MRAM are slowly replacing EEPROMs in some applications, but are expected to remain a small fraction of the EEPROM market for the foreseeable future. The difference between EPROM and EEPROM lies in

3445-402: The semiconductor body of the device. Source and drain contacts are made to regions at the end of the channel. An insulating layer of oxide is grown over the channel, then a conductive (silicon or aluminum) gate electrode is deposited, and a further thick layer of oxide is deposited over the gate electrode. The floating-gate electrode has no connections to other parts of the integrated circuit and

3510-424: The stored value when not being accessed. A second type, DRAM ( dynamic RAM ), is based on MOS capacitors. Charging and discharging a capacitor can store either a '1' or a '0' in the cell. However, since the charge in the capacitor slowly dissipates, it must be refreshed periodically. Due to this refresh process, DRAM consumes more power, but it can achieve higher storage densities. Most non-volatile memory (NVM), on

3575-512: The surface. Following the invention of the MOSFET at Bell Labs, Frank Wanlass studied MOSFET structures in the early 1960s. In 1963, he noted the movement of charge through oxide onto a gate . While he did not pursue it, this idea would later become the basis for EPROM technology. In 1967, Dawon Kahng and Simon Min Sze at Bell Labs proposed that the floating gate of a MOSFET could be used for

3640-442: The transistors. This creates an avalanche discharge of electrons, which have enough energy to pass through the insulating oxide layer and accumulate on the gate electrode. When the high voltage is removed, the electrons are trapped on the electrode. Because of the high insulation value of the silicon oxide surrounding the gate, the stored charge cannot readily leak away and the data can be retained for decades. The programming process

3705-412: The way that the memory programs and erases. EEPROM can be programmed and erased electrically using field electron emission (more commonly known in the industry as "Fowler–Nordheim tunneling"). EPROMs can't be erased electrically and are programmed by hot-carrier injection onto the floating gate. Erase is by an ultraviolet light source, although in practice many EPROMs are encapsulated in plastic that

3770-544: Was developed by An Wang in 1948, and improved by Jay Forrester and Jan A. Rajchman in the early 1950s, before being commercialised with the Whirlwind computer in 1953. Ken Olsen also contributed to its development. Semiconductor memory began in the early 1960s with bipolar memory cells, made of bipolar transistors . While it improved performance, it could not compete with the lower price of magnetic-core memory. In 1957, Frosch and Derick were able to manufacture

3835-476: Was disclosed by Fairchild and Siemens . They used SONOS ( polysilicon - oxynitride - nitride - oxide - silicon ) structure with thickness of silicon dioxide less than 30 Å , and SIMOS (stacked-gate injection MOS ) structure, respectively, for using Fowler-Nordheim tunnelling hot-carrier injection . Around 1976 to 1978, Intel's team, including George Perlegos , made some inventions to improve this tunneling E PROM technology. In 1978, they developed

3900-408: Was first announced by Toshiba in 2007, and first commercially manufactured by Samsung Electronics in 2013. The following schematics detail the three most used implementations for memory cells: The flip-flop has many different implementations, its storage element is usually a latch consisting of a NAND gate loop or a NOR gate loop with additional gates used to implement clocking. Its value

3965-453: Was invented by Dawon Kahng and Simon Sze at Bell Labs in 1967. They proposed the concept of floating-gate memory cells, using FGMOS transistors, which could be used to produce reprogrammable ROM (read-only memory). Floating-gate memory cells later became the basis for non-volatile memory (NVM) technologies including EPROM (erasable programmable ROM), EEPROM (electrically erasable programmable ROM) and flash memory . Flash memory

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4030-436: Was invented by Fujio Masuoka at Toshiba in 1980. Masuoka and his colleagues presented the invention of NOR flash in 1984, and then NAND flash in 1987. Multi-level cell (MLC) flash memory was introduced by NEC , which demonstrated quad-level cells in a 64   Mb flash chip storing 2-bit per cell in 1996. 3D V-NAND , where flash memory cells are stacked vertically using 3D charge trap flash (CTP) technology,

4095-455: Was invented by Bernward and patented by Siemens in 1974. In February 1977, Israeli-American Eliyahou Harari at Hughes Aircraft Company patented in the US a modern EEPROM technology, based on Fowler-Nordheim tunnelling through a thin silicon dioxide layer between the floating-gate and the wafer . Hughes went on to produce this new EEPROM devices. In May 1977, some important research result

4160-584: Was patented by Fujio Masuoka , the inventor of flash memory , at Toshiba and IBM patented another later that year. In 1974, NEC patented a electrically erasable carrier injection device. The next year, NEC applied for the trademark "EEPROM®" with the Japan Patent Office. The trademark was granted in 1978. The theoretical basis of these devices is avalanche hot-carrier injection . In general, programmable memories, including EPROM, of early 1970s had reliability and endurance problems such as

4225-612: Was presented at the 3rd Conference on Solid State Devices , Tokyo in Japan by Yasuo Tarui, Yutaka Hayashi, and Kiyoko Nagai at Electrotechnical Laboratory ; a Japanese national research institute. They fabricated an electrically re-programmable non-volatile memory in 1972, and continued this study for more than 10 years. However this early memory depended on capacitors to work, which modern EEPROM lacks. In 1972 IBM patented an electrically re-programmable non-volatile memory invention. Later that year, an avalanche injection type MOS

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