Misplaced Pages

#229770

69-425: Jitter is the deviation in frequency of a signal. Jitter may also refer to: Jitter Jitter can be quantified in the same terms as all time-varying signals, e.g., root mean square (RMS), or peak-to-peak displacement. Also, like other time-varying signals, jitter can be expressed in terms of spectral density . Jitter period is the interval between two times of maximum effect (or minimum effect) of

138-487: A Gaussian distribution , it is usually quantified using the standard deviation of this distribution. This translates to an RMS measurement for a zero-mean distribution. Often, jitter distribution is significantly non-Gaussian. This can occur if the jitter is caused by external sources such as power supply noise. In these cases, peak-to-peak measurements may be more useful. Many efforts have been made to meaningfully quantify distributions that are neither Gaussian nor have

207-491: A capacitor to store the analog voltage at the input, and using an electronic switch or gate to disconnect the capacitor from the input. Many ADC integrated circuits include the sample and hold subsystem internally. An ADC works by sampling the value of the input at discrete intervals in time. Provided that the input is sampled above the Nyquist rate , defined as twice the highest frequency of interest, then all frequencies in

276-437: A digital encoder logic circuit that generates a binary number on the output lines for each voltage range. ADCs of this type have a large die size and high power dissipation. They are often used for video , wideband communications , or other fast signals in optical and magnetic storage . The circuit consists of a resistive divider network, a set of op-amp comparators and a priority encoder. A small amount of hysteresis

345-410: A digital signal . An ADC may also provide an isolated measurement such as an electronic device that converts an analog input voltage or current to a digital number representing the magnitude of the voltage or current. Typically the digital output is a two's complement binary number that is proportional to the input, but there are other possibilities. There are several ADC architectures . Due to

414-433: A digital-to-analog converter , the time between samples varies and instantaneous signal error arises. The error is proportional to the slew rate of the desired signal and the absolute value of the clock error. The effect of jitter on the signal depends on the nature of the jitter. Random jitter tends to add broadband noise while periodic jitter tends to add errant spectral components, "birdys". In some conditions, less than

483-438: A saw-tooth signal that ramps up or down then quickly returns to zero. When the ramp starts, a timer starts counting. When the ramp voltage matches the input, a comparator fires, and the timer's value is recorded. Timed ramp converters can be implemented economically, however, the ramp time may be sensitive to temperature because the circuit generating the ramp is often a simple analog integrator . A more accurate converter uses

552-470: A 500 Hz sine wave. To avoid aliasing, the input to an ADC must be low-pass filtered to remove frequencies above half the sampling rate. This filter is called an anti-aliasing filter , and is essential for a practical ADC system that is applied to analog signals with higher frequency content. In applications where protection against aliasing is essential, oversampling may be used to greatly reduce or even eliminate it. Although aliasing in most systems

621-402: A burst of traffic at a high rate followed by an interval or period of lower or zero rate transmission may also be seen as a form of jitter, as it represents a deviation from the average transmission rate. However, unlike the jitter caused by variation in latency, transmitting in bursts may be seen as a desirable feature, e.g. in variable bitrate transmissions. Video or image jitter occurs when

690-541: A change in the output code level is called the least significant bit (LSB) voltage. The resolution Q of the ADC is equal to the LSB voltage. The voltage resolution of an ADC is equal to its overall voltage measurement range divided by the number of intervals: where M is the ADC's resolution in bits and E FSR is the full-scale voltage range (also called 'span'). E FSR is given by where V RefHi and V RefLow are

759-491: A clocked counter driving a DAC. A special advantage of the ramp-compare system is that converting a second signal just requires another comparator and another register to store the timer value. To reduce sensitivity to input changes during conversion, a sample and hold can charge a capacitor with the instantaneous input voltage and the converter can time the time required to discharge with a constant current . An integrating ADC (also dual-slope or multi-slope ADC) applies

SECTION 10

#1732772379230

828-525: A constant current source . The time required to discharge the capacitor is proportional to the amplitude of the input voltage. While the capacitor is discharging, pulses from a high-frequency oscillator clock are counted by a register. The number of clock pulses recorded in the register is also proportional to the input voltage. If the analog value to measure is represented by a resistance or capacitance, then by including that element in an RC circuit (with other resistances or capacitances fixed) and measuring

897-409: A continuous-time and continuous-amplitude analog signal to a discrete-time and discrete-amplitude digital signal . The conversion involves quantization of the input, so it necessarily introduces a small amount of quantization error . Furthermore, instead of continuously performing the conversion, an ADC does the conversion periodically, sampling the input, and limiting the allowable bandwidth of

966-409: A de-jitter buffer is equal to the buffering delay introduced before starting the play-out of the media stream. In the context of packet-switched networks, the term packet delay variation is often preferred over jitter . Some systems use sophisticated delay-optimal de-jitter buffers that are capable of adapting the buffering delay to changing network characteristics. The adaptation logic is based on

1035-432: A faithful reproduction of the original signal is only possible if the sampling rate is higher than twice the highest frequency of the signal. Since a practical ADC cannot make an instantaneous conversion, the input value must necessarily be held constant during the time that the converter performs a conversion (called the conversion time ). An input circuit called a sample and hold performs this task—in most cases by using

1104-422: A known voltage charging and discharging curve that can be used to solve for an unknown analog value. The Wilkinson ADC was designed by Denys Wilkinson in 1950. The Wilkinson ADC is based on the comparison of an input voltage with that produced by a charging capacitor. The capacitor is allowed to charge until a comparator determines it matches the input voltage. Then, the capacitor is discharged linearly by using

1173-452: A linear function (or some other function, in the case of a deliberately nonlinear ADC) of their input. These errors can sometimes be mitigated by calibration , or prevented by testing. Important parameters for linearity are integral nonlinearity and differential nonlinearity . These nonlinearities introduce distortion that can reduce the signal-to-noise ratio performance of the ADC and thus reduce its effective resolution. When digitizing

1242-436: A longer time to measure than smaller one. And the accuracy is limited by the accuracy of the microcontroller clock and the amount of time available to measure the value, which potentially might even change during measurement or be affected by external parasitics . A direct-conversion or flash ADC has a bank of comparators sampling the input signal in parallel, each firing for a specific voltage range. The comparator bank feeds

1311-453: A meaningful peak level. All have shortcomings but most tend to be good enough for the purposes of engineering work. In computer networking , jitter can refer to packet delay variation , the variation ( statistical dispersion ) in the delay of the packets . One of the main differences between random and deterministic jitter is that deterministic jitter is bounded and random jitter is unbounded. Random jitter, also called Gaussian jitter,

1380-425: A nanosecond of jitter can reduce the effective bit resolution of a converter with a Nyquist frequency of 22 kHz to 14 bits. Sampling jitter is an important consideration in high-frequency signal conversion, or where the clock signal is especially prone to interference. In digital antenna arrays ADC and DAC jitters are the important factors determining the direction of arrival estimation accuracy and

1449-409: A pulse of a particular amplitude is always converted to the same digital value. The problem lies in that the ranges of analog values for the digitized values are not all of the same widths, and the differential linearity decreases proportionally with the divergence from the average width. The sliding scale principle uses an averaging effect to overcome this phenomenon. A random, but known analog voltage

SECTION 20

#1732772379230

1518-429: A signal characteristic that varies regularly with time. Jitter frequency , the more commonly quoted figure, is its inverse. ITU-T G.810 classifies deviation lower frequencies below 10 Hz as wander and higher frequencies at or above 10 Hz as jitter . Jitter may be caused by electromagnetic interference and crosstalk with carriers of other signals. Jitter can cause a display monitor to flicker, affect

1587-426: A sine wave x ( t ) = A sin ⁡ ( 2 π f 0 t ) {\displaystyle x(t)=A\sin {(2\pi f_{0}t)}} , the use of a non-ideal sampling clock will result in some uncertainty in when samples are recorded. Provided that the actual sampling time uncertainty due to clock jitter is Δ t {\displaystyle \Delta t} ,

1656-535: Is added to the sampled input voltage. It is then converted to digital form, and the equivalent digital amount is subtracted, thus restoring it to its original value. The advantage is that the conversion has taken place at a random point. The statistical distribution of the final levels is decided by a weighted average over a region of the range of the ADC. This in turn desensitizes it to the width of any specific level. These are several common ways of implementing an electronic ADC. Resistor-capacitor (RC) circuits have

1725-428: Is built into the comparator to resolve any problems at voltage boundaries. At each node of the resistive divider, a comparison voltage is available. The purpose of the circuit is to compare the analog input voltage with each of the node voltages. The circuit has the advantage of high speed as the conversion takes place simultaneously rather than sequentially. Typical conversion time is 100 ns or less. Conversion time

1794-400: Is caused by phase noise . The resolution of ADCs with a digitization bandwidth between 1 MHz and 1 GHz is limited by jitter. For lower bandwidth conversions such as when sampling audio signals at 44.1 kHz, clock jitter has a less significant impact on performance. An analog signal is continuous in time and it is necessary to convert this to a flow of digital values. It

1863-585: Is extremely small compared to parallel bus architectures with equivalent performance, which may have eye openings on the order of 1000 picoseconds . Jitter is measured and evaluated in various ways depending on the type of circuit under test. In all cases, the goal of jitter measurement is to verify that the jitter will not disrupt normal operation of the circuit. Testing of device performance for jitter tolerance may involve injection of jitter into electronic components with specialized test equipment. A less direct approach—in which analog waveforms are digitized and

1932-408: Is introduced by the quantization inherent in an ideal ADC. It is a rounding error between the analog input voltage to the ADC and the output digitized value. The error is nonlinear and signal-dependent. In an ideal ADC, where the quantization error is uniformly distributed between − 1 ⁄ 2 LSB and + 1 ⁄ 2 LSB, and the signal has a uniform distribution covering all quantization levels,

2001-427: Is limited only by the speed of the comparator and of the priority encoder. This type of ADC has the disadvantage that the number of comparators required almost doubles for each added bit. Also, the larger the value of n, the more complex is the priority encoder. A successive-approximation ADC uses a comparator and a binary search to successively narrow a range that contains the input voltage. At each successive step,

2070-411: Is often applied when quantizing photographic images to a fewer number of bits per pixel—the image becomes noisier but to the eye looks far more realistic than the quantized image, which otherwise becomes banded . This analogous process may help to visualize the effect of dither on an analog audio signal that is converted to digital. An ADC has several sources of errors. Quantization error and (assuming

2139-510: Is often summarized in terms of its effective number of bits (ENOB), the number of bits of each measure it returns that are on average not noise . An ideal ADC has an ENOB equal to its resolution. ADCs are chosen to match the bandwidth and required SNDR of the signal to be digitized. If an ADC operates at a sampling rate greater than twice the bandwidth of the signal, then per the Nyquist–Shannon sampling theorem , near-perfect reconstruction

Jitter (disambiguation) - Misplaced Pages Continue

2208-471: Is possible. The presence of quantization error limits the SNDR of even an ideal ADC. However, if the SNDR of the ADC exceeds that of the input signal, then the effects of quantization error may be neglected, resulting in an essentially perfect digital representation of the bandlimited analog input signal. The resolution of the converter indicates the number of different, i.e. discrete, values it can produce over

2277-417: Is therefore required to define the rate at which new digital values are sampled from the analog signal. The rate of new values is called the sampling rate or sampling frequency of the converter. A continuously varying bandlimited signal can be sampled and then the original signal can be reproduced from the discrete-time values by a reconstruction filter . The Nyquist–Shannon sampling theorem implies that

2346-480: Is unpredictable electronic timing noise. Random jitter typically follows a normal distribution due to being caused by thermal noise in an electrical circuit . Deterministic jitter is a type of clock or data signal jitter that is predictable and reproducible. The peak-to-peak value of this jitter is bounded, and the bounds can easily be observed and predicted. Deterministic jitter has a known non-normal distribution. Deterministic jitter can either be correlated to

2415-404: Is unwanted, it can be exploited to provide simultaneous down-mixing of a band-limited high-frequency signal (see undersampling and frequency mixer ). The alias is effectively the lower heterodyne of the signal frequency and sampling frequency. For economy, signals are often sampled at the minimum rate required with the result that the quantization error introduced is white noise spread over

2484-406: Is zero for DC, small at low frequencies, but significant with signals of high amplitude and high frequency. The effect of jitter on performance can be compared to quantization error: Δ t < 1 2 q π f 0 {\displaystyle \Delta t<{\frac {1}{2^{q}\pi f_{0}}}} , where q is the number of ADC bits. Clock jitter

2553-422: The analog-to-digital converter and digital-to-analog converter . Examples of anti-jitter circuits include phase-locked loop and delay-locked loop . Jitter buffers or de-jitter buffers are buffers used to counter jitter introduced by queuing in packet-switched networks to ensure continuous playout of an audio or video media stream transmitted over the network. The maximum jitter that can be countered by

2622-448: The signal-to-quantization-noise ratio (SQNR) is given by where Q is the number of quantization bits. For example, for a 16-bit ADC, the quantization error is 96.3 dB below the maximum level. Quantization error is distributed from DC to the Nyquist frequency . Consequently, if part of the ADC's bandwidth is not used, as is the case with oversampling , some of the quantization error will occur out-of-band , effectively improving

2691-429: The ADC is correlated with the signal and sounds distorted and unpleasant. With dithering, the distortion is transformed into noise. The undistorted signal may be recovered accurately by averaging over time. Dithering is also used in integrating systems such as electricity meters . Since the values are added together, the dithering produces results that are more exact than the LSB of the analog-to-digital converter. Dither

2760-423: The ADC is intended to be linear) non- linearity are intrinsic to any analog-to-digital conversion. These errors are measured in a unit called the least significant bit (LSB). In the above example of an eight-bit ADC, an error of one LSB is 1 ⁄ 256 of the full signal range, or about 0.4%. All ADCs suffer from nonlinearity errors caused by their physical imperfections, causing their output to deviate from

2829-470: The SQNR for the bandwidth in use. In an oversampled system, noise shaping can be used to further increase SQNR by forcing more quantization error out of band. In ADCs, performance can usually be improved using dither . This is a very small amount of random noise (e.g. white noise ), which is added to the input before conversion. Its effect is to randomize the state of the LSB based on the signal. Rather than

Jitter (disambiguation) - Misplaced Pages Continue

2898-410: The allowed range of analog input values. Thus a particular resolution determines the magnitude of the quantization error and therefore determines the maximum possible signal-to-noise ratio for an ideal ADC without the use of oversampling . The input samples are usually stored electronically in binary form within the ADC, so the resolution is usually expressed as the audio bit depth . In consequence,

2967-446: The complexity and the need for precisely matched components , all but the most specialized ADCs are implemented as integrated circuits (ICs). These typically take the form of metal–oxide–semiconductor (MOS) mixed-signal integrated circuit chips that integrate both analog and digital circuits . A digital-to-analog converter (DAC) performs the reverse function; it converts a digital signal into an analog signal. An ADC converts

3036-415: The converter compares the input voltage to the output of an internal digital-to-analog converter (DAC) which initially represents the midpoint of the allowed input voltage range. At each step in this process, the approximation is stored in a successive approximation register (SAR) and the output of the digital-to-analog converter is updated for a comparison over a narrower range. A ramp-compare ADC produces

3105-409: The data stream ( data-dependent jitter ) or uncorrelated to the data stream (bounded uncorrelated jitter). Examples of data-dependent jitter are duty-cycle dependent jitter (also known as duty-cycle distortion) and intersymbol interference . Total jitter ( T ) is the combination of random jitter ( R ) and deterministic jitter ( D ) and is computed in the context to a required bit error rate (BER) for

3174-476: The depth of jammers suppression. In the context of computer networks, packet jitter or packet delay variation (PDV) is the variation in latency as measured in the variability over time of the end-to-end delay across a network. A network with constant delay has no packet jitter. Packet jitter is expressed as an average of the deviation from the network mean delay. PDV is an important quality of service factor in assessment of network performance. Transmitting

3243-421: The effect of sampling jitter. A jitter signal can be decomposed into intrinsic mode functions (IMFs), which can be further applied for filtering or dejittering. Analog-to-digital converter In electronics , an analog-to-digital converter ( ADC , A/D , or A-to-D ) is a system that converts an analog signal , such as a sound picked up by a microphone or light entering a digital camera , into

3312-490: The error caused by this phenomenon can be estimated as E a p ≤ | x ′ ( t ) Δ t | ≤ 2 A π f 0 Δ t {\displaystyle E_{ap}\leq |x'(t)\Delta t|\leq 2A\pi f_{0}\Delta t} . This will result in additional recorded noise that will reduce the effective number of bits (ENOB) below that predicted by quantization error alone. The error

3381-531: The horizontal lines of video image frames are randomly displaced due to the corruption of synchronization signals or electromagnetic interference during video transmission. Model-based dejittering study has been carried out under the framework of digital image and video restoration. Jitter in serial bus architectures is measured by means of eye patterns . There are standards for jitter measurement in serial bus architectures. The standards cover jitter tolerance , jitter transfer function and jitter generation , with

3450-427: The input signal. The performance of an ADC is primarily characterized by its bandwidth and signal-to-noise and distortion ratio (SNDR). The bandwidth of an ADC is characterized primarily by its sampling rate . The SNDR of an ADC is influenced by many factors, including the resolution , linearity and accuracy (how well the quantization levels match the true analog signal), aliasing and jitter . The SNDR of an ADC

3519-428: The jitter estimates computed from the arrival characteristics of the media packets. Adjustments associated with adaptive de-jittering involves introducing discontinuities in the media play-out which may be noticeable to the listener or viewer. Adaptive de-jittering is usually carried out for audio play-outs that include voice activity detection that allows the lengths of the silence periods to be adjusted, thus minimizing

SECTION 50

#1732772379230

3588-408: The jitter in terms of a fraction of the transmission unit period. This unit is useful because it scales with clock frequency and thus allows relatively slow interconnects such as T1 to be compared to higher-speed internet backbone links such as OC-192 . Absolute units such as picoseconds are more common in microprocessor applications. Units of degrees and radians are also used. If jitter has

3657-494: The logarithm of the resolution, i.e. the number of bits. Flash ADCs are certainly the fastest type of the three; The conversion is basically performed in a single parallel step. There is a potential tradeoff between speed and precision. Flash ADCs have drifts and uncertainties associated with the comparator levels results in poor linearity. To a lesser extent, poor linearity can also be an issue for successive-approximation ADCs. Here, nonlinearity arises from accumulating errors from

3726-465: The number of discrete values available is usually a power of two. For example, an ADC with a resolution of 8 bits can encode an analog input to one in 256 different levels (2  = 256). The values can represent the ranges from 0 to 255 (i.e. as unsigned integers) or from −128 to 127 (i.e. as signed integer), depending on the application. Resolution can also be defined electrically, and expressed in volts . The change in voltage required to guarantee

3795-411: The perceptual impact of the adaptation. A dejitterizer is a device that reduces jitter in a digital signal . A dejitterizer usually consists of an elastic buffer in which the signal is temporarily stored and then retransmitted at a rate based on the average rate of the incoming signal. A dejitterizer may not be effective in removing low-frequency jitter (wander). A filter can be designed to minimize

3864-428: The performance of processors in personal computers, introduce clicks or other undesired effects in audio signals, and cause loss of transmitted data between network devices. The amount of tolerable jitter depends on the affected application. For clock jitter, there are three commonly used metrics: In telecommunications , the unit used for the above types of jitter is usually the unit interval (UI) which quantifies

3933-410: The performance of the ADC can be greatly increased at little or no cost. Furthermore, as any aliased signals are also typically out of band, aliasing can often be eliminated using very low cost filters. The speed of an ADC varies by type. The Wilkinson ADC is limited by the clock rate which is processable by current digital circuits. For a successive-approximation ADC , the conversion time scales with

4002-598: The required values for these attributes varying among different applications. Where applicable, compliant systems are required to conform to these standards. Testing for jitter and its measurement is of growing importance to electronics engineers because of increased clock frequencies in digital electronic circuitry to achieve higher device performance. Higher clock frequencies have commensurately smaller eye openings, and thus impose tighter tolerances on jitter. For example, modern computer motherboards have serial bus architectures with eye openings of 160 picoseconds or less. This

4071-446: The resulting data stream analyzed—is employed when measuring pixel jitter in frame grabbers . Anti-jitter circuits (AJCs) are a class of electronic circuits designed to reduce the level of jitter in a clock signal. AJCs operate by re-timing the output pulses so they align more closely to an idealized clock. They are widely used in clock and data recovery circuits in digital communications , as well as for data sampling systems such as

4140-504: The signal can be reconstructed. If frequencies above half the Nyquist rate are sampled, they are incorrectly detected as lower frequencies, a process referred to as aliasing. Aliasing occurs because instantaneously sampling a function at two or fewer times per cycle results in missed cycles, and therefore the appearance of an incorrectly lower frequency. For example, a 2 kHz sine wave being sampled at 1.5 kHz would be reconstructed as

4209-404: The signal simply getting cut off altogether at low levels, it extends the effective range of signals that the ADC can convert, at the expense of a slight increase in noise. Dither can only increase the resolution of a sampler. It cannot improve the linearity, and thus accuracy does not necessarily improve. Quantization distortion in an audio signal of very low level with respect to the bit depth of

SECTION 60

#1732772379230

4278-406: The subtraction processes. Wilkinson ADCs have the best linearity of the three. The sliding scale or randomizing method can be employed to greatly improve the linearity of any type of ADC, but especially flash and successive approximation types. For any ADC the mapping from input voltage to digital output value is not exactly a floor or ceiling function as it should be. Under normal conditions,

4347-476: The system: in which the value of n is based on the BER required of the link. A common BER used in communication standards such as Ethernet is 10 . In analog-to-digital and digital-to-analog conversion of signals, the sampling is normally assumed to be periodic with a fixed period—the time between every two samples is the same. If there is jitter present on the clock signal to the analog-to-digital converter or

4416-415: The time it takes to charge (and/or discharge) its capacitor from 1 ⁄ 3   V supply to 2 ⁄ 3   V supply . By sending this pulse into a microcontroller with an accurate clock, the duration of the pulse can be measured and converted using the capacitor charging equation to produce the value of the unknown resistance or capacitance. Larger resistances and capacitances will take

4485-550: The time to charge the capacitance from a known starting voltage to another known ending voltage through the resistance from a known voltage supply, the value of the unknown resistance or capacitance can be determined using the capacitor charging equation: V capacitor ( t ) = V supply ( 1 − e − t R C ) {\displaystyle V_{\text{capacitor}}(t)=V_{\text{supply}}\left(1-e^{-{\frac {t}{RC}}}\right)} and solving for

4554-411: The unknown input voltage to the input of an integrator and allows the voltage to ramp for a fixed time period (the run-up period). Then a known reference voltage of opposite polarity is applied to the integrator and is allowed to ramp until the integrator output returns to zero (the run-down period). The input voltage is computed as a function of the reference voltage, the constant run-up time period, and

4623-471: The unknown resistance or capacitance using those starting and ending datapoints. This is similar but contrasts to the Wilkinson ADC which measures an unknown voltage with a known resistance and capacitance, by instead measuring an unknown resistance or capacitance with a known voltage. For example, the positive (and/or negative) pulse width from a 555 Timer IC in monostable or astable mode represents

4692-459: The upper and lower extremes, respectively, of the voltages that can be coded. Normally, the number of voltage intervals is given by where M is the ADC's resolution in bits. That is, one voltage interval is assigned in between two consecutive code levels. Example: In many cases, the useful resolution of a converter is limited by the signal-to-noise ratio (SNR) and other errors in the overall system expressed as an ENOB. Quantization error

4761-433: The whole passband of the converter. If a signal is sampled at a rate much higher than the Nyquist rate and then digitally filtered to limit it to the signal bandwidth produces the following advantages: Oversampling is typically used in audio frequency ADCs where the required sampling rate (typically 44.1 or 48 kHz) is very low compared to the clock speed of typical transistor circuits (>1 MHz). In this case,

#229770