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151-527: The 6809 was among the most powerful (and most expensive) 8-bit processors of its era. In 1981 a 6809 in single-unit quantities was $ 37 compared to $ 9 for a Zilog Z80 and $ 6 for a 6502. It was launched when a new generation of 16-bit processors were coming to market, like the Intel 8086 , and 32-bit designs were on the horizon, including Motorola's own 68000 . It was not feature competitive with newer designs and not price competitive with older ones. The 6809

302-601: A MOS Technology 8502 . Zilog was later producing a low-power Z80 suitable for the growing laptop computer market of the early 1980s. Intel produced a CMOS 8085 (80C85) used in battery-powered portable computers, such as the Kyocera -designed laptop from April 1983, also sold by Tandy (as TRS-80 Model 100 ), Olivetti, and NEC. In following years, however, CMOS versions of the Z80 (from both Zilog and Japanese manufacturers) would dominate this market as well, in products such as

453-450: A piezoelectric crystal directly connected to it, and a built-in clock generator generates the internal high-amplitude two-phase clock signals at half the crystal frequency (a 6.14 MHz crystal would yield a 3.07 MHz clock, for instance). The internal clock is available on an output pin, to drive peripheral devices or other CPUs in lock-step synchrony with the CPU from which the signal

604-657: A 16-bit address register HL. In the 8080, this pairing was added to the BC and DE pairs as well, while HL was generalized to allow use as a 16-bit accumulator, not just an address register. The 8080 also introduced immediate 16-bit data for BC, DE, HL, and SP loads. Furthermore, direct 16-bit copying between HL and memory was now possible, using a direct address. The Z80 orthogonalized this further by making all 16-bit register pairs, including IX and IY, more general purpose, as well as allowing 16-bit copying directly to and from memory for all of these pairs. The 16-bit IX and IY registers in

755-476: A European second-source manufacturer SGS . The design was also copied by several Japanese, Eastern European and Soviet manufacturers. This won the Z80 acceptance in the world market since large companies like NEC , Toshiba , Sharp , and Hitachi started to manufacture the device (or their own Z80-compatible clones or designs). The Z80 continued to be used in embedded systems for decades after its introduction, with ongoing advancements. The latest addition to

906-532: A Unix-like operating system uniFlex which ran only on such machines. OS-9 Level II, also took advantage of such memory management facilities. Most other computers of the time with more than 64 KB of memory addressing were limited to bank switching where much if not all the 64 KB was simply swapped for another section of memory, although in the case of the 6809, Motorola offered their own MC6829 MMU design mapping 2 megabytes in 2 KB pages. The 6809 also saw use in various videogame systems. Notable among these, in

1057-565: A branch to a computed pointer can be done with PCHL. These abilities make it feasible to compile languages such as PL/M , Pascal , or C with 16-bit variables and produce 8085 machine code. Subtraction and bitwise logical operations on 16 bits is done in 8-bit steps. Operations that have to be implemented by program code (subroutine libraries) include comparisons of signed integers as well as multiplication and division. A number of undocumented instructions and flags were discovered by two software engineers, Wolfgang Dehnhardt and Villy M. Sorensen in

1208-485: A byte and two T-states for each occurrence. This naturally makes the index register unavailable for any other use, or else the need to constantly reload it would negate its efficiency. Intel 8085 The Intel 8085 (" eighty-eighty-five ") is an 8-bit microprocessor produced by Intel and introduced in March 1976. It is the last 8-bit microprocessor developed by Intel. It is software- binary compatible with

1359-654: A copy from the HL-addressed cell into itself (i.e., MOV M,M ) instead encodes the HLT instruction, halting execution until an external reset or unmasked interrupt occurs. Although the 8085 is an 8-bit processor, it has some 16-bit operations. Any of the three 16-bit register pairs (BC, DE, HL) or SP can be loaded with an immediate 16-bit value (using LXI), incremented or decremented (using INX and DCX), or added to HL (using DAD). LHLD loads HL from directly addressed memory and SHLD stores HL likewise. The XCHG operation exchanges

1510-405: A copyright on their assembly mnemonics, a new assembly syntax had to be developed for the Z80. This time a more systematic approach was used: These principles made it straightforward to find names and forms for all new Z80 instructions, as well as orthogonalizations of old ones, such as LD BC,1234 . Apart from naming differences, and despite a certain discrepancy in basic register structure,

1661-473: A day later, Faggin and Ungermann were kicking around ideas based on "integrated logic" when Ungermann said "how about Zilog?" Faggin immediately agreed, stating they could say it was the "last word in integrated logic". When they met the next day and both immediately recalled it, the company had its name. The first samples were returned from Mostek on March 9, 1976. By the end of the month, they had also completed an assembler -based development system . Some of

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1812-405: A debugging monitor program, an 8155 RAM and 22 I/O ports, an 8279 hex keypad and 8-digit 7-segment LED, and a TTY (Teletype) 20  mA current loop serial interface. Pads are available for one more 2K×8 8755 EPROM, and another 256  byte RAM 8155 I/O Timer/Counter can be optionally added. All data, control, and address signals are available on dual pin headers, and a large prototyping area

1963-500: A high-level design, adding several concepts of his own. In particular, he used his experience on NEC minicomputers to add the concept of two sets of processor registers so they could quickly respond to interrupts . Ungerman began the development of a series of related controllers and peripheral chips that would complement the design. Through this period, Shima developed a legendary reputation for being able to convert logic concepts into physical design in realtime; while discussing

2114-411: A last minute decision to leave 10 out of 12 new 8085 instructions undocumented to speed up and simplify the design of the upcoming 8086 CPU. The 8085 supports both port-mapped and memory-mapped I/O . It supports up to 256 input/output (I/O) ports via dedicated Input/Output instructions, with port addresses as operands. Port-mapped IO can be an advantage on processors with limited address space. During

2265-466: A low-cost product like this would not be able to compete with a design from a company with its own production lines, like Intel. They then began considering a more complex microprocessor instead, initially known as the Super 80, with the main feature being its use of a +5 V bus instead of the more common −5, +5 and 12 V used by designs like the 8080. The new design was intended to be compatible with

2416-443: A memory address, or a port number. A NOP "no operation" instruction exists, but does not modify any of the registers or flags. Like larger processors, it has CALL and RET instructions for multi-level procedure calls and returns (which can be conditionally executed, like jumps) and instructions to save and restore any 16-bit register-pair on the machine stack. There are also eight one-byte call instructions (RST) for subroutines located at

2567-458: A method using only the 8080-model registers. The Z80 also introduced a new signed overflow flag and complemented the fairly simple 16-bit arithmetics of the 8080 with dedicated instructions for signed 16-bit arithmetics. The 8080-compatible registers AF, BC, DE, HL are duplicated as a separate register file in the Z80, where the processor can quickly (four t-states, the least possible execution time for any Z80 instruction) switch from one bank to

2718-668: A number of programming languages and program editors in ROM. The result was later picked up by Commodore, who sold it as the SuperPET , or MicroMainframe in Europe. These were relatively popular in the mid-1980s before the introduction of the PC clone market took over the programming role for most users. Other popular home computer uses include the Fujitsu FM-7 , Canon CX-1, Dragon 32/64 , and

2869-472: A port-mapped I/O bus cycle, the 8-bit I/O address is output by the CPU on both the lower and upper halves of the 16-bit address bus. Devices designed for memory mapped I/O can also be accessed by using the LDA (load accumulator from a 16-bit address) and STA (store accumulator at a 16-bit address specified) instructions, or any other instructions that have memory operands. A memory-mapped IO transfer cycle appears on

3020-459: A profit on the small number of chips that did work, the prices for the working models had to be fairly high, on the order of hundreds of dollars in small quantities. Some of the 6800's designers were convinced that a lower-cost system would be key to widespread acceptance. Notable among them was Chuck Peddle , who was sent on sales trips and saw prospective customers repeatedly reject the design as being too expensive for their intended uses. He began

3171-499: A program calling a floating-point routine in ROM would place its data on the U stack and then call the routine, which could then perform the calculations using data on its own private stack pointed to by S, and then return, leaving the U stack untouched. Another reason for the expanded stack access was to support reentrant code, code that can be called from various different programs concurrently without concern for coordination between them, or that can recursively call itself. This makes

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3322-516: A project to produce a much less costly design, but Motorola's management proved uninterested and eventually told him to stop working on it. Peddle and some other members of the 6800 team left Motorola for MOS Technology and introduced this design in 1975 as the MOS Technology 6502 . The 6800 was initially sold at $ 360 in single-unit quantities, but had been lowered to $ 295 . The 6502 was introduced at $ 25 , and Motorola immediately reduced

3473-460: A proposed feature, he would often interrupt and state how much room that would take on the chip and veto its addition if it was too large. The first pass at the design was complete by April 1975. Shima had completed a logic layout by the beginning of May. A second version of the logic design was issued on August 7 and the bus details by September 16. Tape-out was completed in November and converting

3624-422: A regular encoding (common with the 8080) is that each of the 8-bit registers can be loaded from themselves (e.g. LD A,A ). This is effectively a NOP . New block transfer instructions can move up to 64 kilobytes from memory to memory or between memory and I/O peripheral ports. Block instructions LDIR and LDDR ( l oa d , i ncrement/ d ecrement, r epeat) use HL to point to the source address, DE to

3775-506: A relative address ( JR instead of JP ) using a signed 8-bit displacement. Only the zero and carry flags can be tested for these new two-byte JR instructions. (All 8080 jumps and calls, conditional or not, are three-byte instructions.) A two-byte instruction specialized for program looping is also new to the Z80: DJNZ ( d ecrement j ump if n on- z ero) takes a signed 8-bit displacement as an immediate operand. The B register

3926-477: A second index register, Y, a second stack pointer, U (while renaming the original S), and allowed the A and B registers to be treated as a single 16-bit accumulator, D. It also added another 8-bit register, DP, to set the base address of the direct page. These additions were invisible to 6800 code, and the 6809 was 100% source-compatible with earlier code. Another significant addition was program-counter-relative addressing for all data manipulation instructions. This

4077-548: A separate pin on the processor, a feature which permits simple systems to avoid the cost of a separate interrupt controller. The RST 7.5 interrupt is edge triggered (latched), while RST 5.5 and 6.5 are level-sensitive. All interrupts except TRAP are enabled by the EI instruction and disabled by the DI instruction. In addition, the SIM (Set Interrupt Mask) and RIM (Read Interrupt Mask) instructions,

4228-501: A series of 16-bit processors, which emerged as the Intel 8086 in 1978. Motorola also began the design of a similar high-end design, in the MACSS project, but did not initially consider an improved 8-bit design. But when they polled their existing 6800 customers, they found that many were not willing to pay for a 16-bit design for their simple needs. This led to the decision to produce a greatly improved but compatible 8-bit design that became

4379-586: A share of the booming home-computer market in the early-to-mid-1980s. The 8085 had a long life as a controller, no doubt thanks to its built-in serial I/O and five prioritized interrupts, arguably microcontroller-like features that the Z80 CPU did not have. Once designed into such products as the DECtape II controller and the VT102 video terminal in the late 1970s, the 8085 served for new production throughout

4530-436: A significant amount of those math operations were being performed on 16-bit values. This led to the decision to include basic 16-bit mathematics in the new design: load, store, add, and subtract. Similarly, increments and decrements accounted for only 6.1% of the code, but these almost always occurred within loops where each one was performed many times. This led to the addition of post-incrementing and pre-decrementing modes using

4681-513: A single 8-inch floppy disk drive. Later an external box was made available with two more floppy drives. It runs the ISIS operating system and can also operate an emulator pod and an external EPROM programmer. This unit uses the Multibus card cage which was intended just for the development system. A surprising number of spare card cages and processors were being sold, leading to the development of

Motorola 6809 - Misplaced Pages Continue

4832-530: A system not using interrupts) it can be used as simply another 8-bit data register. The instructions LD A,R and LD A,I affect the Z80 flags register, unlike all the other LD (load) instructions. The Sign (bit 7) and Zero (bit 6) flags are set according to the data loaded from the Refresh or Interrupt source registers. For both instructions, the Parity/Overflow flag (bit 2) is set according to

4983-553: A total of $ 10 million for the entire industry being spent in all of 1975 (equivalent to $ 57 million in 2023). Someone from Exxon contacted the still-unnamed company, and arranged a meeting that eventually led to them providing an initial $ 500,000 funding in June 1975 (equivalent to $ 2.8 million in 2023). With funding being discussed, and a design to be built, Shima joined in February 1975. Shima immediately set about producing

5134-428: A variable base address (as in recursive stack frames ) and can also reduce code size by removing the need for multiple short instructions using non-indexed registers. However, although they may save speed in some contexts when compared to long/complex "equivalent" sequences of simpler operations, they incur a lot of additional CPU time (e.g., 19 T-states to access one indexed memory location vs. as little as 11 to access

5285-521: A week in order to meet the tight schedule given by the financial investors. The Z80 offered many improvements over the 8080: The Z80 took over from the 8080 and its offspring, the 8085 , in the processor market and became one of the most popular and widely used 8-bit CPUs. Some organizations such as British Telecom remained loyal to the 8085 for embedded applications, owing to their familiarity with it and to its on-chip serial interface and interrupt architecture. Likewise, Zenith Data Systems paired

5436-610: A while) while files are edited in the other. It has a bubble memory option and various programming modules, including EPROM, and Intel 8048 and 8051 programming modules which are plugged into the side, replacing stand-alone device programmers. In addition to an 8080/8085 assembler, Intel produced a number of compilers including those for PL/M-80 and Pascal , and a set of tools for linking and statically locating programs to enable them to be burned into EPROMs and used in embedded systems . A lower cost "MCS-85 System Design Kit" (SDK-85) board contains an 8085 CPU, an 8355 ROM containing

5587-557: Is an 8-bit microprocessor designed by Zilog that played an important role in the evolution of early computing. Launched in 1976 and software-compatible with the Intel 8080 , it offered a compelling alternative due to its better integration and increased performance. As well as the 8080's seven registers and flags register, the Z80 had an alternate register set that duplicated them, two 16-bit index registers and additional instructions including bit manipulation and block copy/search. Initially intended for use in embedded systems like

5738-553: Is decremented, and if the result is nonzero, then program execution jumps relative to PC; the flags remain unaltered. To perform an equivalent loop on an 8080 requires separate DEC and conditional jump (to a two-byte absolute address) instructions (totalling four bytes), and the DEC alters the flag register. The index register (IX/IY, often abbreviated XY) instructions can be useful for accessing data organised in fixed heterogenous structures (such as records ) or at fixed offsets relative

5889-695: Is generally written starting at a base address , combining pre-written modules normally required a lengthy process of changing constants (or equates) that pointed to key locations in the code. Motorola's idea was to eliminate this task and make the building-block concept much more practical. System integrators would simply combine off-the-shelf code in ROMs to handle common tasks. Libraries of common routines like floating point arithmetic, graphics primitives, Lempel-Ziv compression , and so forth would be available to license, combine together along with custom code, and burn to ROM. In previous processor designs, including

6040-510: Is in context unless carefully commented. Thus it is advisable that exchange instructions be used directly and in short discrete code segments. The Zilog Z280 instruction set includes JAF and JAR instructions which jump to a destination address if the alternate registers are in context (thus officially recognizing this programming complication). As on the 8080, 8-bit registers are typically paired to provide 16-bit versions. The 8080 compatible registers are: The new registers introduced with

6191-618: Is of course possible that the actual 8080 and/or 8085 differs from the published specifications, especially in subtle details. (The same is not true of the Z80.) As mentioned already, only the SIM and RIM instructions were new to the 8085. The processor has seven 8-bit registers accessible to the programmer, named A, B, C, D, E, H, and L, where A is also known as the accumulator. The other six registers can be used as independent byte-registers or as three 16-bit register pairs, BC, DE, and HL (or B, D, H, as referred to in Intel documents), depending on

Motorola 6809 - Misplaced Pages Continue

6342-591: Is often referred to as the "alternate register set" (by some, the "primed" register file since the apostrophe character is used to denote them in assembler source code and the Zilog documentation). This emphasizes that only one set is addressable at any time. However, the 8-bit accumulator A with its flag register F is bifurcated from the "general purpose" register pairs HL, DE and BC. This is accomplished with two separate instructions used to swap their accessibilities: EX AF,AF' exchanges only register pair AF with AF', while

6493-421: Is output. The 8085 can also be clocked by an external oscillator (making it feasible to use the 8085 in synchronous multi-processor systems using a system-wide common clock for all CPUs, or to synchronize the CPU to an external time reference such as that from a video source or a high-precision time reference). The 8085 is a binary compatible follow-up on the 8080. It supports the complete instruction set of

6644-720: Is provided. The 8085 processor was used in a few early personal computers, for example, the TRS-80 Model 100 line used an OKI manufactured 80C85 (MSM80C85ARS). The CMOS version 80C85 of the NMOS/HMOS 8085 processor has several manufacturers. In the Soviet Union , an 80C85 clone was developed under the designation IM1821VM85A ( Russian : ИМ1821ВМ85А ) which in 2016 was still in production. Some manufacturers provide variants with additional functions such as additional instructions. The radiation hardened version of

6795-492: Is sensitive to the aforementioned difference in the AC flag setting or differences in undocumented CPU behavior.) 8085 instruction timings differ slightly from the 8080—some 8-bit operations, including INR, DCR, and the heavily used MOV r,r' instruction, are one clock cycle faster, but instructions that involve 16-bit operations, including stack operations (which increment or decrement the 16-bit SP register) generally one cycle slower. It

6946-547: Is set to 1 if the parity (number of 1-bits) of the accumulator is even; if odd, it is cleared. The zero flag is set if the result of the operation was 0. Lastly, the carry flag is set if a carryover from bit 7 of the accumulator (the MSB) occurred. As in many other 8-bit processors, all instructions are encoded in a single byte (including register-numbers, but excluding immediate data), for simplicity. Some of them are followed by one or two bytes of data, which can be an immediate operand,

7097-599: Is supported between any two 8-bit registers and between any 8-bit register and an HL-addressed memory cell, using the MOV instruction. An immediate value can also be moved into any of the foregoing destinations, using the MVI instruction. Due to the regular encoding of the MOV instruction (using nearly a quarter of the entire opcode space) there are redundant codes to copy a register into itself ( MOV B,B , for instance), which are of little use, except for delays. However, what would have been

7248-561: Is the ZX81 , which lets it keep track of character positions on the TV screen by triggering an interrupt at wrap around (by connecting INT to A6). The interrupt vector register , I , is used for the Z80 specific mode 2 interrupts (selected by the IM 2 instruction). It supplies the high byte of the base address for a 128-entry table of service routine addresses which are selected via an index sent to

7399-414: Is used as the byte counter. The Z80 can input and output any register to an I/O port using register C to designate the port. (The 8080 only performs I/O through the accumulator A, using a direct port address specified in the instruction; a self-modifying code technique is required to use a variable 8080 port address.) The last group of block instructions perform a CP compare operation between

7550-571: Is used for the power supply (+5 V) and pin 20 for ground. Pin 39 is used as the Hold pin. The Intel 8085 processor was designed using nMOS circuitry, with later "H" versions implemented in Intel's enhanced nMOS process known as HMOS II ("High-performance MOS"), which was originally developed for fast static RAM products. Unlike the 8080, the 8085 requires only a single 5-volt power supply, similar to its competing processors. The 8085 contains approximately 6,500 transistors . The 8085 incorporates

7701-598: Is used in the TRS-80 Color Computer , Dragon 32/64 , SuperPET , ENER 1000 , Fujitsu FM-7 , the Cybernex LC3, and Thomson MO/TO home computers, the Vectrex game console, and early 1980s arcade video games including Star Wars , Defender , Robotron: 2084 , Joust , and Gyruss . 1990s Williams pinball machines are equipped with WPC -series controller boards based on 68B09. Series II of

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7852-564: The EXX instruction exchanges the three general purpose register pairs HL, DE and BC with their alternates HL', DE' and BC'. Thus the accumulator A can interact independently with any of the general purpose 8-bit registers in the alternate (or primed) register file, or, if HL' contains a pointer to memory, some byte there (DE' and BC' can also transfer 8-bit data between memory and accumulator A). This can become confusing for programmers because after executing EX AF,AF' or EXX what were previously

8003-701: The 6811 , was discontinued as late as the second decade of the 21st century. The Hitachi 6309 is an enhanced version of the 6809 with extra registers and additional instructions, including block move, additional multiply instructions, and division. Motorola spun off its microprocessor division in 2004. The division changed its name to Freescale and was subsequently acquired by NXP . Neither Motorola nor Hitachi produce 6809 processors or derivatives anymore. 6809 cores are available in VHDL and can be programmed into an FPGA and used as an embedded processor with speed ratings up to 40 MHz. Some 6809 opcodes also live on in

8154-729: The Amstrad NC100 , Cambridge Z88 and Tandy's own WP-2. Perhaps a key to the initial success of the Z80 was the built-in DRAM refresh, at least in markets such as CP/M and other office and home computers. (Most Z80 embedded systems use static RAM that do not need refresh.) It may also have been its minimalistic two-level interrupt system, or conversely, its general multi-level daisy-chain interrupt system useful in servicing multiple Z80 IO chips. These features allowed systems to be built with less support hardware and simpler circuit board layouts. However, others claim that its popularity

8305-531: The CP/M operating system and Intel's PL/M compiler for 8080 (as well as its generated code), would run unmodified on the new Z80 CPU. Masatoshi Shima designed most of the microarchitecture as well as the gate and transistor levels of the Z80 CPU, assisted by a small number of engineers and layout people. CEO Federico Faggin was actually heavily involved in the chip layout work, together with two dedicated layout people. According to Faggin, he worked 80 hours

8456-535: The Fairlight CMI digital audio workstation and Konami's Time Pilot '84 arcade game each use dual 6809 processors. Hitachi was a major user of the 6809 and later produced an updated version as the Hitachi 6309 . The Motorola 6800 was designed beginning in 1971 and released in 1974. In overall design terms, it has a strong resemblance to other CPUs that were designed from the start as 8-bit designs, like

8607-611: The Freescale embedded processors. In 2015, Freescale authorized Rochester Electronics to start manufacturing the MC6809 once again as a drop-in replacement and copy of the original NMOS device. Freescale supplied Rochester the original GDSII physical design database. At the end of 2016, Rochester's MC6809 (including the MC68A09, and MC68B09) is fully qualified and available in production. Australian developer John Kent has synthesized

8758-626: The Game Boy and TI-83 series . The Z80 was the brainchild of Federico Faggin , a key figure behind the creation of the Intel 8080. After leaving Intel in 1974, Faggin co-founded Zilog with Ralph Ungermann . The Z80 was released in July 1976. With the revenue from the Z80, the company built its own chip factories . Zilog licensed the Z80 to the US-based Synertek and Mostek , which had helped them with initial production, as well as to

8909-411: The Intel 8080 . It was initially fabricated using early NMOS logic , which normally required several different power supply voltages. A key feature was an on-chip voltage doubler that allowed it to run on a single +5 V supply, a major advantage over its competitors like the Intel 8080 which required −5 V , +5 V , −12 V and ground . The 6800 was initially fabricated using

9060-554: The Thomson TO7 series. It was also available as an option on the Acorn System 2 , 3 and 4 computers. Most SS-50 bus designs that had been built around the 6800 also had options for the 6809 or switched to it exclusively. Examples include machines from SWTPC , Gimix , Smoke Signal Broadcasting , etc. Motorola also build a series of EXORmacs and EXORset development systems. Hitachi produced its own 6809-based machines,

9211-483: The direct page , which is normally at the bottom of memory - the 6502 refers to this as zero page addressing . The 6809 added a new 8-bit DP register, for direct page. Code that formerly had to be in the zero page can now be moved anywhere in memory as long as the DP is changed to point to its new location. Using DP solved the problem of referring to addresses within the code, but data is generally located some distance from

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9362-423: The index registers . The main goal for the new design was to support position-independent code . Motorola's market was mostly embedded systems and similar single-purpose systems, which often ran programs that were very similar to those on other platforms. Development for these systems often took the form of collecting a series of pre-rolled subroutines and combining them together. However, as assembly language

9513-426: The " Southbridge " chips. In many engineering schools the 8085 processor is used in introductory microprocessor courses. Trainer kits composed of a printed circuit board, 8085, and supporting hardware are offered by various companies. These kits usually include complete documentation allowing a student to go from soldering to assembly language programming in a single course. Also, the architecture and instruction set of

9664-610: The +5 V, −5 V and +12 V supplies needed by the 8080. This capability matched that of the competing Z80 , a popular 8080-derived CPU introduced the year before. These processors could be used in computers running the CP/M operating system . The 8085 is supplied in a 40-pin DIP package. To maximise the functions on the available pins, the 8085 uses a multiplexed address/data (AD -AD ) bus. However, an 8085 circuit requires an 8-bit address latch, so Intel manufactured several support chips with an address latch built in. These include

9815-429: The 6502 began to take over the 6800's market, Intel was experiencing the same problem when the upstart Zilog Z80 began to steal sales from the Intel 8080 . Both Motorola and Intel began new design cycles to leapfrog those designs. Intel responded by quickly introducing a small but practical upgrade of the 8080 as the 8085 , which made it less expensive to use and more competitive with the Z80. They also began to design

9966-455: The 6800 to $ 125. It remained uncompetitive and sales prospects dimmed. The introduction of the Micralign to Motorola's lines allowed further reductions and by 1981 the price of the then-current 6800P was slightly less than the equivalent 6502, at least in single-unit quantities. By that point, however, the 6502 had sold tens of millions of units and the 6800 had been largely forgotten. While

10117-486: The 6800, there was a mix of ways to refer to memory locations. Some of these were relative to the current location in memory or to a value in an index register, while others were absolute, a 16-bit value that referred to a physical location in memory. The former style allows code to be moved because the address it references will move along with the code. The absolute locations do not; code that uses this style of addressing will have to be recompiled if it moves. To address this,

10268-402: The 68000 rather than further improved versions of the 6809. Its first major use was in the TRS-80 Color Computer , which happened largely by accident. Motorola had been asked to design a color-capable computer terminal for an online farm-aid project, a system known as "AgVision". Tandy ( Radio Shack ) was brought in as a retail partner and sold them under the name "VideoTex", but the project

10419-412: The 6809 filled out its instruction opcodes so that there were more instances of relative addressing where possible. As an example, the 6800 includes a direct addressing mode used to make code smaller and faster; instead of a memory address having 16-bits and thus requiring two bytes to store, direct addresses are only 8-bits long. The downside is that it can only refer to memory within a 256-byte window,

10570-498: The 6809 implementation is a register-transfer level machine, using a central PLA to implement much of the instruction decoding as well as parts of the sequencing. Like the 6800 and 6502, the 6809 uses a two-phase clock to gate the latches. This two-phase clock cycle is used as a full machine cycle in these processors. Simple instructions can execute in as little as two or three such cycles. The 6809 has an internal two-phase clock generator (needing only an external crystal) whereas

10721-517: The 6809 was released, in 1976 Motorola had launched its own advanced CPU project, then known as Motorola Advanced Computer System on Silicon project, or MACSS. Although too late to be chosen for the IBM PC project, when MACSS appeared as the Motorola 68000 in 1979 it took any remaining interest in the 6809. Motorola soon announced that their future 8-bit systems would be powered by cut-down versions of

10872-412: The 6809 were costly; the CPU had approximately 9,000 transistors compared to the 6800's 4,100 or the 6502's 3,500. While process improvements meant it could be fabricated cheaper than the original 6800, those same improvements were being applied to the other designs and so the relative cost remained the same. Such was the case in practice; in 1981 the 6809 sold in single-unit quantities for roughly six times

11023-411: The 6809. Analysis of 6800 code demonstrated that loads and stores were the vast majority of all the time in CPU terms, accounting for 39% of all the operations in the code they examined. In contrast, mathematical operations were relatively rare, only 2.8% of the code. However, a careful examination of the loads and stores noted that many of these were being combined with adds and subtracts, revealing that

11174-526: The 6809E as their main CPU. The (E) version was used in order to synchronize the microprocessor's clock to the sound chip (Ensoniq 5503 DOC) in those machines; in the ESQ-1 and SQ-80 the 68B09E was used, requiring a dedicated arbiter logic in order to ensure 1 MHz bus timing when accessing the DOC chip. In contrast to earlier Motorola products, the 6809 did not see widespread use in the microcontroller field. It

11325-492: The 6809E needs an external clock generator. There are variants such as the 68A09(E) and 68B09(E); the internal letter indicates the processor's rated clock speed. The 6800, 6502, the 6809's clock system differs from other processors of the era. For instance, the Z80 uses a single external clock and the internal steps of the instruction process continue on each transition. This means that the external clock generally runs much faster; 680x designs generally ran at 1 or 2 MHz while

11476-660: The 68A09 incarnation, was the unique vector graphics -based Vectrex home videogame machine. It was also used in the Milton Bradley Expansion (MBX) system (an arcade console for the TI-99/4A home computer), and a series of arcade games released during the early to mid-1980s. Williams Electronics was a prolific user of the processor, which was deployed in Defender , Stargate , Joust , Robotron: 2084 , Sinistar , and other games. The 6809 CPU forms

11627-478: The 8-bit accumulator (the A register). For two-operand 8-bit operations, the other operand can be either an immediate value, another 8-bit register, or a memory cell addressed by the 16-bit register pair HL. The only 8-bit ALU operations that can have a destination other than the accumulator are the unary incrementation or decrementation instructions, which can operate on any 8-bit register or on memory addressed by HL, as for two-operand 8-bit operations. Direct copying

11778-406: The 8080); the four remaining codes are used extensively as opcode prefixes : CB and ED enable extra instructions, and DD or FD select IX+d or IY+d respectively (in some cases without displacement d) in place of HL. This scheme gives the Z80 a large number of permutations of instructions and registers; Zilog categorizes these into 158 different "instruction types", 78 of which are the same as those of

11929-430: The 8080, as the Z80 sometimes indicates signed overflow where the 8080 would indicate parity, possibly causing the logic of some practical 8080 software to fail on the Z80. ) This new overflow flag is used for all new Z80-specific 16-bit operations ( ADC , SBC ) as well as for 8-bit arithmetic operations, while the 16-bit operations inherited from the 8080 ( ADD , INC , DEC ) do not affect it. Also, bit 1 of

12080-445: The 8080, but add many of the nice features of the Motorola 6800 , including index registers and improved interrupts . While still being set up, the industry newsletter Electronic News heard of them and published a story on the newly formed company. This attracted the attention of Exxon Enterprises, Exxon 's high-tech investment arm. At the time, in the midst of the recession, there was very little venture capital available, with

12231-559: The 8080, the Z80's combination of compatibility, affordability, and superior performance propelled it to widespread adoption in video game systems and home computers during the late 1970s and early 1980s, fueling the personal computing revolution. Products it was used in include the Osborne 1 , Radio Shack TRS-80 , ColecoVision , ZX Spectrum and the Pac-Man cabinet; in later years it remained used in portables, best known for use in

12382-459: The 8080, with exactly the same instruction behavior, including all effects on the CPU flags (except for the AND/ANI operation, which sets the AC flag differently). This means that the vast majority of object code (any program image in ROM or RAM) that runs successfully on the 8080 can run directly on the 8085 without translation or modification. (Exceptions include timing-critical code and code that

12533-734: The 8085 has been in on-board instrument data processors for several NASA and ESA space physics missions in the 1990s and early 2000s, including CRRES , Polar , FAST , Cluster , HESSI , the Sojourner Mars Rover, and THEMIS . The Swiss company SAIA used the 8085 and the 8085–2 as the CPUs of their PCA1 line of programmable logic controllers during the 1980s. Pro-Log Corp. put the 8085 and supporting hardware on an STD Bus format card containing CPU, RAM, sockets for ROM/EPROM, I/O and external bus interfaces. The included Instruction Set Reference Card uses entirely different mnemonics for

12684-676: The 8085 with the 16-bit Intel 8088 in its first MS-DOS computer, the Zenith Z-100 , despite having previous experience with its pioneering Z80-based Heathkit H89 and Zenith Z-89 products. However, other computers were made integrating the Z80 with other CPUs: the Radio Shack TRS-80 Model ;16 with a Motorola 68000 , the DEC Rainbow with an 8088, and the Commodore ;128 with

12835-474: The 8755, with an address latch, 2 KB of EPROM and 16 I/O pins, and the 8155 with 256 bytes of RAM , 22 I/O pins and a 14-bit programmable timer/counter. The multiplexed address/data bus reduced the number of PCB tracks between the 8085 and such memory and I/O chips. Both the 8080 and the 8085 were eclipsed by the Zilog Z80 for desktop computers, which took over most of the CP/M computer market, as well as

12986-464: The CPU during an interrupt acknowledge cycle; this index is simply the low byte part of the pointer to the tabulated indirect address pointing to the service routine. The pointer identifies a particular peripheral chip or peripheral function or event, where the chips are normally connected in a so-called daisy chain for priority resolution. Like the refresh register, this register has also sometimes been used creatively; in interrupt modes 0 and 1 (or in

13137-412: The Intel 8080 (allowing operation of all 8080 programs on a Z80). The Zilog documentation further groups instructions into the following categories (most from the 8080, others entirely new like the block and bit instructions, and others 8080 instructions with more versatile addressing modes, like the 16-bit loads, I/O, rotates/shifts and relative jumps): No explicit multiply instructions are available in

13288-410: The Intel 8085 CPU. The product was a direct competitor to Intel's Multibus card offerings. The 8085 CPU is one part of a family of chips developed by Intel for building a complete system. Many of these support chips were also used with other processors. The original IBM PC based on the Intel 8088 processor used several of these chips; the equivalent functions today are provided by VLSI chips, namely

13439-737: The MB-6890 and later the S1. These were primarily for the Japanese market, but some were exported to and sold in Australia , where the MB-6890 was dubbed the "Peach", probably in reference to the Apple II . The S1 was notable in that it contained paging hardware extending the 6809's native 64 kilobyte addressing range to a full 1 megabyte in 4 KB pages. It was similar in this to machines produced by SWTPC, Gimix, and several other suppliers. TSC produced

13590-564: The Motorola 6809 CPU in hardware description language (HDL). This has made possible the use of the 6809 core at much higher clock speeds than were available with the original 6809. Gary Becker's CoCo3FPGA runs the Kent 6809 core at 25 MHz. Roger Taylor's Matchbox CoCo runs at 7.16 MHz. Dave Philipsen's CoCoDEV runs at 25 MHz. The 6809's internal design is closer to simpler, non- microcoded CPU designs. Like most 8-bit microprocessors,

13741-577: The Multibus as a separate product. The later iPDS is a portable unit, about 8" ×  16" ×  20", with a handle. It has a small green screen, a keyboard built into the top, a 5¼ inch floppy disk drive, and runs the ISIS-II operating system. It can also accept a second 8085 processor, allowing a limited form of multi-processor operation where both processors run simultaneously and independently. The screen and keyboard can be switched between them, allowing programs to be assembled on one processor (large programs took

13892-492: The SP to be the base of the block, and then refer to data within it using relative values. To aid this type of access, the 6809 renamed the SP to U for "user", and added a second stack pointer, S, for "system". The idea was user programs would use U while the CPU itself would use S to store data during subroutine calls . This allowed system code to be easily called by changing S without affecting any other running program. For instance,

14043-461: The Z80 and 8086 syntax are virtually isomorphic for a large portion of instructions. Only quite superficial similarities (such as the word MOV, or the letter X, for extended register) exist between the 8080 and 8086 assembly languages, although 8080 programs can be translated to 8086 assembly language by translator programs . The Z80 uses 252 out of the available 256 codes as single byte opcodes ("root instruction" most of which are inherited from

14194-584: The Z80 are fairly conventional, ultimately based on the register structure of the Datapoint 2200 . The Z80 was designed as an extension of the Intel 8080, created by the same engineers, which in turn was an extension of the 8008 . The 8008 was basically a PMOS implementation of the TTL-based CPU of the Datapoint 2200. The 2200 design allowed 8-bit registers H and L (High and Low) to be paired into

14345-469: The Z80 are primarily intended as base address-registers, where a particular instruction supplies a constant offset that is added to the previous values, but they are also usable as 16-bit accumulators, among other things. A limitation is that all operand references involving IX or IY require an extra instruction prefix byte, adding at least four clock cycles over the timing of an instruction using HL instead; this sometimes makes using IX or IY less efficient than

14496-424: The Z80 are: The refresh register , R , increments each time the CPU fetches an opcode (or an opcode prefix, which internally executes like a 1-byte instruction) and has no simple relationship with program execution. This has sometimes been used to generate pseudorandom numbers in games, and also in software protection schemes. It has also been employed as a "hardware" counter in some designs; an example of this

14647-522: The Z80 family is the eZ80 , which was offered alongside successor chips. Zilog announced the discontinuation of the Z80 in April 2024 after nearly five decades of production. At Fairchild Semiconductor , and later at Intel , physicist and engineer Federico Faggin had been working on fundamental transistor and semiconductor manufacturing technology. He also developed the basic design methodology used for memories and microprocessors at Intel and led

14798-417: The Z80 generally ran at 2 or 4. Internally, the 680x's divided the external clock frequency by four to create the system clock; so a 1 MHz 6809 would have a 4 MHz crystal or clock signal. Typically, on an instruction-for-instruction basis, they ran roughly twice as fast, when comparing the external clocks to other microprocessors. The advantage to the 680x style access was that dynamic RAM chips of

14949-455: The Z80 support and peripheral ICs were under development at this point, and many of them were launched during the following year. Among them were the Z80 CTC (counter/timer), Z80 DMA (direct memory access), Z80 DART (dual asynchronous receiver–transmitter), Z80 SIO (synchronous communication controller), and Z80 PIO (parallel input/output). The Z80 was officially launched in July 1976. One of

15100-470: The Z80. However, this would likely be erroneous code on the 8080, as DAA was defined for addition only on that processor. The Z80 has six new LD instructions that can load the DE, BC, and SP register pairs from memory, and load memory from these three register pairs—unlike the 8080. As on the 8080, load instructions do not affect the flags (except for the special-purpose I and R register loads). A result of

15251-464: The alternate (primed) registers are now the main registers, and vice versa. The only way for the programmer to tell which set(s) are in context (while "playing computer" while scrutinizing the assembler source text, or worse, poring over code with a debugger) is to trace where each register swap is made at each point in the program. Obviously if many jump and calls are made within these code segments it can quickly become difficult to tell which register file

15402-496: The bus as a normal memory access cycle. Intel produced a series of development systems for the 8080 and 8085, known as the MDS-80 Microprocessor System. The original development system had an 8080 processor. Later 8085 and 8086 support was added including ICE ( in-circuit emulators ). It is a large and heavy desktop box, about a 20" cube (in the Intel corporate blue color) which includes a CPU, monitor, and

15553-456: The byte at (HL) and the accumulator A. Register pair DE is not used. The repeating versions CPIR and CPDR only terminate if BC goes to zero or a match is found. HL is left pointing to the byte after ( CPIR ) or before ( CPDR ) the matching byte. If no match is found the Z ;flag is reset. There are non-repeating versions CPI and CPD . Unlike the 8080, the Z80 can jump to

15704-476: The code, outside ROM. To solve the problem of easily referring to data while remaining position independent, the 6809 added a variety of new addressing modes. Among these was program-counter-relative addressing which allowed any memory location to be referred to by its location relative to the instruction. Additionally, the stack was more widely used, so that a program in ROM could set aside a block of memory in RAM, set

15855-445: The construction of operating systems much easier; the operating system had its own stack, and the processor could quickly switch between a user application and the operating system simply by changing which stack pointer it was using. This also makes servicing interrupts much easier for the same reason. The 6809 adds a fast interrupt request (FIRQ) interrupt that saves only the program counter and condition code register before calling

16006-586: The core of the successful Williams Pinball Controller . The KONAMI-1 is a modified 6809 used by Konami in Roc'n Rope , Gyruss , and The Simpsons . Series II of the Fairlight CMI (computer musical instrument) used dual 6809 CPUs running OS-9 , and also used one 6809 CPU per voice card. The 6809 was often employed in music synthesizers from other manufacturers such as Oberheim ( Xpander , Matrix 6/12/1000 ), PPG (Wave 2/2.2/2.3, Waveterm A), and Ensoniq ( Mirage sampler, SDP-1, ESQ-1 , SQ-80 ). The latter used

16157-502: The current state of the IFF2 flip-flop. Although the Z80 is generally considered an eight-bit CPU, it has a four-bit ALU , so calculations are done in two steps. The first Intel 8008 assembly language was based on a very simple (but systematic) syntax inherited from the Datapoint 2200 design. This original syntax was later transformed into a new, somewhat more traditional, assembly language form for this same original 8008 chip. At about

16308-415: The design directly. Faggin thought this would mean they could never compete even if they set up their own lines, and the agreement fell through. He then turned to Mostek, who agreed to a term of exclusivity while Zilog got their lines set up, and were eventually given the second source agreement. After considering many names for the new company, and finding them so unmemorable they could not recall them even

16459-482: The design. Sometime later, Shima was told by an engineer within NEC that the traps had delayed their copying efforts by six months. The successful launch allowed Faggin and Ungermann to approach Exxon looking for funding to build their own fab. The company agreed, and Zilog built a production line very rapidly. This allowed them to capture about 60 to 70% of the total market for Z80 sales. With their own line running, Mostek

16610-571: The destination address, and BC as a byte counter. Bytes are copied from source to destination, the pointers are incremented or decremented, and the byte counter is decremented until BC reaches zero. Non-repeating versions LDI and LDD move a single byte and bump the pointers and byte counter, which if it becomes zero resets the P/V ;flag. Corresponding memory-to-I/O instructions INIR , INDR , OTIR , OTDR , INI , IND , OUTI and OUTD operate similarly, except that B, not BC,

16761-436: The era generally ran at 2 MHz. Due to the cycle timing, there were periods of the internal clock where the memory bus was guaranteed to be free. This allowed the computer designer to interleave access to memory between the CPU and an external device, say a direct memory access controller, or more commonly, a graphics chip . By running both chips at 1 MHz and stepping them one after the other, they could share access to

16912-430: The first customers was a buyer who, unknown to Zilog, worked for NEC. At the time, the Japanese electronics companies were well known for taking US chip designs and producing them without a license. The Zilog team had worried about this, and Faggin had come up with the idea of adding transistors that would be subtly modified to operate differently than a visual inspection would suggest. Shima added six of these "traps" around

17063-439: The fixed addresses 00h, 08h, 10h,...,38h. These are intended to be supplied by external hardware in order to invoke a corresponding interrupt-service routine, but are also often employed as fast system calls. One sophisticated instruction is XTHL, which is used for exchanging the register pair HL with the value stored at the address indicated by the stack pointer. All two-operand 8-bit arithmetic and logical (ALU) operations work on

17214-513: The flags register (a spare bit on the 8080) is used as a flag N that indicates whether the last arithmetic instruction executed was a subtraction or addition. The Z80 version of the DAA instruction (decimal adjust accumulator for BCD arithmetic) checks the N ;flag and behaves accordingly, so a (hypothetical) subtraction followed later by DAA will yield a different result on an old 8080 than on

17365-566: The formerly independent sections under the direction of Les Vadasz, further diluting the microprocessor's place in the company. That year, the 1973–1975 recession reached a peak and Intel laid off a number of employees. All of this led to Faggin becoming restless, and he invited Ungermann out for drinks and asked if he would be interested in starting their own company. Ungermann immediately agreed, and as he had less to do at Intel, left in August or September, followed by Faggin, whose last day at Intel

17516-697: The functions of the 8224 (clock generator) and the 8228 (system controller) on chip, increasing the level of integration. A downside compared to similar contemporary designs (such as the Z80) is the fact that the buses require demultiplexing; however, address latches in the Intel 8155, 8355, and 8755 memory chips allow a direct interface, so an 8085 along with these chips is almost a complete system. The 8085 has extensions to support new interrupts , with three maskable vectored interrupts (RST 7.5, RST 6.5 and RST 5.5), one non-maskable interrupt (TRAP), and one externally serviced interrupt (INTR). Each of these five interrupts has

17667-499: The interrupt code, whereas the IRQ interrupt saves all registers, taking additional cycles, then more to unwind the stack on exit. The 6809 includes one of the earliest dedicated hardware multipliers. It takes 8-bit numbers in the A and B accumulators and produces a result in A:B, known collectively as D. Much of the design had been based around the market concept of building-block code. But

17818-631: The introductory 2.5  MHz , via the well known 4 MHz (Z80A), up to 6 MHz (Z80B) and 8 MHz (Z80H). The NMOS version has been produced as a 10 MHz part since the late 1980s. CMOS versions were developed with specified upper frequency limits ranging from 4 MHz up to 20 MHz for the version sold today. The CMOS versions allowed low-power standby with internal state retained, having no lower frequency limit. The fully compatible derivatives HD64180 / Z180 and eZ80 are currently specified for up to 33 MHz and 50 MHz, respectively. The programming model and register set of

17969-509: The lifetime of those products. This was typically longer than the product life of desktop computers. The 8085 is a conventional von Neumann design based on the Intel 8080. Unlike the 8080 it does not multiplex state signals onto the data bus, but the 8-bit data bus is instead multiplexed with the lower eight bits of the 16-bit address bus to limit the number of pins to 40. State signals are provided by dedicated bus control signal pins and two dedicated bus state ID pins named S0 and S1. Pin 40

18120-507: The market for pre-rolled ROM modules never materialized: Motorola's only released example was the MC6839 floating-point ROM. The industry as a whole solved the problem of integrating code modules from separate sources by using automatic relocating linkers and loaders , which is the solution used today. However, the decisions made by the design team enabled multi-user, multitasking operating systems like OS-9 and UniFlex . The added features of

18271-423: The memory without any additional complexity or circuitry. Depending on version and speed grade, approximately 40–60% of a single clock cycle is typically available for memory access in a 6800, 6502, or 6809. The original 6800 included two 8-bit accumulators , A and B, a single 16-bit index register , X, a 16-bit program counter , PC, a 16-bit stack pointer , SP, and an 8-bit status register . The 6809 added

18422-416: The more-famous Intel 8080 with only two minor instructions added to support its added interrupt and serial input/output features. However, it requires less support circuitry, allowing simpler and less expensive microcomputer systems to be built. The "5" in the part number highlighted the fact that the 8085 uses a single +5- volt (V) power supply by using depletion-mode transistors, rather than requiring

18573-529: The number of instructions from the 6800's 78 instructions to the 6809's 59. These new modes had the same opcodes as the previously separate instruction, so these changes were only visible to the programmer working on new code. The instruction set and register complement are highly orthogonal , making the 6809 easier to program than contemporaries. Like the 6800, the 6809 includes an undocumented address bus test instruction which came to be nicknamed Halt and Catch Fire (HCF) . Zilog Z80 The Zilog Z80

18724-491: The only instructions of the 8085 that are not from the 8080 design, allow each of the three maskable RST interrupts to be individually masked. All three are masked after a normal CPU reset. SIM and RIM also allow the global interrupt mask state and the three independent RST interrupt mask states to be read, the pending-interrupt states of those same three interrupts to be read, the RST 7.5 trigger-latch flip-flop to be reset (cancelling

18875-426: The original Z80 (being 1 clock slower than in the 8080/8085); nonetheless, they are about twice as fast as performing the same calculations using 8-bit operations, and equally important, they reduce register usage. It was not uncommon for programmers to "poke" different offset displacement bytes (which were typically calculated dynamically) into indexed instructions; this is an example of self-modifying code , which

19026-407: The original Z80, though registers A and HL can be multiplied by powers of two with ADD A,A and ADD HL,HL instructions (similarly IX and IY also). Shift instructions can also multiply or divide by powers of two. Different sizes and variants of additions, shifts, and rotates have somewhat differing effects on flags because most of the flag-changing properties of the 8080 were copied. However,

19177-483: The other; a feature useful for speeding up responses to single-level, high-priority interrupts. A similar feature was present in the 2200, but was never implemented at Intel. The dual register-set is very useful in the embedded role, as it improves interrupt handling performance, but found widespread use in the personal computer role as an additional set of general registers for complex code like floating-point arithmetic or home computer games. The duplicate register file

19328-418: The parity flag bit P of the 8080 (bit 2) is called P/V (parity/overflow) in the Z80 as it serves the additional purpose of a twos complement overflow indicator, a feature lacking in the 8080. Arithmetic instructions on the Z80 set it to indicate overflow rather than parity, while bitwise instructions still use it as a parity flag. (This introduces a subtle incompatibility of the Z80 with code written for

19479-503: The particular instruction. Some instructions use HL as a (limited) 16-bit accumulator. As in the 8080, the contents of the memory address pointed to by HL can be accessed as pseudo register M. It also has a 16-bit program counter and a 16-bit stack pointer to memory (replacing the 8008's internal stack ). Instructions such as PUSH PSW, POP PSW affect the Program Status Word (accumulator and flags). The accumulator stores

19630-459: The pending interrupt without servicing it), and serial data to be sent and received via the SOD and SID pins, respectively, all under program control and independently of each other. SIM and RIM each execute in four clock cycles (T states), making it possible to sample SID and/or toggle SOD considerably faster than it is possible to toggle or sample a signal via any I/O or memory-mapped port, e.g. one of

19781-456: The port of an 8155. (In this way, SID can be compared to the SO ["Set Overflow"] pin of the 6502 CPU contemporary to the 8085.) Like the 8080, the 8085 can accommodate slower memories through externally generated wait states (pin 35, READY), and has provisions for Direct Memory Access (DMA) using HOLD and HLDA signals (pins 39 and 38). An improvement over the 8080 is that the 8085 can itself drive

19932-415: The price of a 6502. For those systems that needed some of its special features, like the hardware multiplier, the system could justify its price, but in most roles, it was overlooked. Another factor in its low use was the presence of newer designs with significantly higher performance. Among these was the Intel 8086 , released the same year, and its lower-cost version, the Intel 8088 of 1979. A feeling for

20083-515: The problem can be seen in the Byte Sieve assembly language results against other common designs from the era (taken from 1981 and 1983): Although the 6809 did offer a performance improvement over the likes of the 6502 and Z80, the improvement was not in line with the increase in price. For those where price was not the primary concern, but outright performance was, the new designs outperformed it by as much as an order of magnitude . Even before

20234-402: The process of developing an 8085 assembler. These instructions use 16-bit operands and include indirect loading and storing of a word, a subtraction, a shift, a rotate, and offset operations. By the time 8085 was designed but not yet announced, many designers found it to be inferior to the competing products already on the market. A next generation 8086 CPU was already in development. Intel made

20385-406: The results of arithmetic and logical operations, and the flags register bits (sign, zero, auxiliary carry, parity, and carry flags) are set or cleared according to the results of these operations. The sign flag is set if the result has a negative sign (i.e. it is set if bit 7 of the accumulator is set). The auxiliary or half carry flag is set if a carryover from bit 3 to bit 4 occurred. The parity flag

20536-535: The same memory using HL and INC to point to the next). Thus, for simple or linear accesses of data, use of IX and IY tend to be slower and occupy more memory. Still, they may be useful in cases where the "main" registers are all occupied, by removing the need to save/restore registers. Their officially undocumented 8-bit halves (see below) can be especially useful in this context, for they incur less slowdown than their 16-bit parents. Similarly, instructions for 16-bit additions are not particularly fast (11 clocks) in

20687-517: The same time, the new assembly language was also extended to accommodate the additional addressing modes in the more advanced Intel 8080 chip (the 8008 and 8080 shared a language subset without being binary compatible ; however, the 8008 was binary compatible with the Datapoint 2200). In this process, the mnemonic L , for LOAD , was replaced by various abbreviations of the words LOAD , STORE and MOVE , intermixed with other symbolic letters. The mnemonic letter M , for memory (referenced by HL),

20838-438: The tape into a production mask required two more months. Faggin had already started looking for a production partner. By this time, Synertek and Mostek had both set up the depletion-mode production lines that could be used to produce the design. Having talked to Synertek previously, Faggin approached them first. However, the president of Synertek demanded that the company be given a second source license, allowing them to sell

20989-428: The then-current contact lithography process. In this process, the photomask is placed in direct contact with the wafer , exposed, and then lifted off. There was a small chance that some of the etching material would be left on the wafer when it was lifted, causing future chips patterned with the mask to fail. For complex multi-patterned designs like a CPU, this led to about 90% of the chips failing when tested. To make

21140-409: The value should be used as a memory address (as mentioned below), while the 8086 syntax uses brackets instead of ordinary parentheses for this purpose. Both Z80 and 8086 use the + sign to indicate that a constant is added to a base register to form an address. Note that the 8086 is not a complete superset of the Z80. BX is the only 8086 register pair that can be used as a pointer. Because Intel claimed

21291-485: The values of HL and DE. XTHL exchanges last item pushed on stack with HL. Adding HL to itself performs a 16-bit arithmetic left shift with one instruction. The only 16-bit instruction that affects any flag is DAD (adding BC, DE, HL, or SP to HL), which updates the carry flag to facilitate 24-bit or larger additions and left shifts. Adding the stack pointer to HL is useful for indexing variables in (recursive) stack frames. A stack frame can be allocated using DAD SP and SPHL, and

21442-478: The work on the Intel 4004 , the Intel 8080 and several other ICs. Masatoshi Shima was the principal logic and transistor-level designer of the 4004 and the 8080 under Faggin's supervision, while Ralph Ungermann was in charge of custom integrated circuit design. In early 1974, Intel viewed their microprocessors not so much as products to be sold on their own but as a way to sell more of their main products, static RAM and ROM . A reorganization placed many of

21593-407: Was Halloween 1974. When Shima heard, he asked to come to the new company as well, but having no actual product design or money, they told him to wait. The newly formed and unnamed company initially began designing a single-chip microcontroller called the 2001. They met with Synertek to discuss fabrication on their lines, and when Faggin began to understand the costs involved it became clear that

21744-454: Was a key addition for position-independent code , as it allows data to be referred to relative to the instruction, and as long as the resulting memory location exists then the instructions can be moved in memory freely. The system retained its previous addressing modes as well, although in the new assembler language , what were previously separate instructions were now considered to be different addressing modes on other instructions. This reduced

21895-454: Was due to the duplicated registers that allowed fast context switches or more efficient processing of things like floating-point math compared to 8-bit CPUs with fewer registers. (The Z80 can keep several such numbers internally, using HL'HL, DE'DE and BC'BC as 32-bits registers, avoiding having to access them from slower RAM during computation.) For the original NMOS design, the specified upper clock-frequency limit increased successively from

22046-460: Was given the go-ahead to start sales of their own versions, the MK3880, which provided a second-source for customers which Intel lacked. At the time, a second-source was considered extremely important as a start-up like Zilog might go out of business and leave potential customers stranded. Faggin designed the instruction set to be binary compatible with the 8080 so that most 8080 code, notably

22197-546: Was lifted out from within the instruction mnemonic to become a syntactically freestanding operand , while registers and combinations of registers became very inconsistently denoted; either by abbreviated operands (MVI D, LXI H and so on), within the instruction mnemonic itself (LDA, LHLD and so on), or both at the same time (LDAX B, STAX D and so on). Illustration of four syntaxes, using samples of equivalent, or (for 8086) very similar, load and store instructions. The Z80 syntax uses parentheses around an expression to indicate that

22348-426: Was originally produced in 1 MHz, 1.5 MHz (68A09) and 2 MHz (68B09) speed ratings. Faster versions were produced later by Hitachi. With little to improve, the 6809 marks the end of the evolution of Motorola's 8-bit processors; Motorola intended that future 8-bit products would be based on an 8-bit data bus version of the 68000 (the 68008 ). A microcontroller version with a slightly modified instruction set,

22499-531: Was regular practice on nearly all early 8-bit processors with non- pipelined execution units. The index registers have a parallel instruction to JP (HL) , which is JP (XY) . This is often seen in stack-oriented languages like Forth , which at the end of every Forth word (atomic subroutines comprising the language) must jump unconditionally back to their thread interpreter routines. Typically this jump instruction appears many hundreds of times in an application, and using JP (XY) rather than JP THREAD saves

22650-457: Was ultimately canceled shortly after its introduction in 1980. Tandy then re-worked the design to produce a home computer , which became one of the 6809's most notable design wins. Looking for a low-cost programming platform for computer science students, the University of Waterloo developed a system that combined a 6809-based computer-on-a-card with an existing Commodore PET , including

22801-432: Was used in traffic signal controllers made in the 1980s by several different manufacturers, as well as Motorola's SMARTNET and SMARTZONE Trunked Central Controllers (so dubbed the "6809 Controller"). These controllers were used as the central processors in many of Motorola's trunked two-way radio communications systems. The 6809 was used by Mitel as the main processor in its SX20 Office Telephone System. The Motorola 6809

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