Since 1985, many processors implementing some version of the MIPS architecture have been designed and used widely.
72-559: The first MIPS microprocessor, the R2000 , was announced in 1985. It added multiple-cycle multiply and divide instructions in a somewhat independent on-chip unit. New instructions were added to retrieve the results from this unit back to the processor register file; these result-retrieving instructions were interlocked . The R2000 could be booted either big-endian or little-endian . It had thirty-one 32-bit general purpose registers, but no status register ( condition code register (CCR),
144-414: A HyperTransport port. The R8000 (1994) was the first superscalar MIPS design, able to execute two integer or floating point and two memory instructions per cycle. The design was spread over six chips: an integer unit (with 16 KB instruction and 16 KB data caches), a floating-point unit, three fully-custom secondary cache tag RAMs (two for secondary cache accesses, one for bus snooping), and
216-516: A 2.0 μm double-metal CMOS process. MIPS was a fabless semiconductor company, that is, they did not have the capability to fabricate integrated circuits. The chip set was initially fabricated for MIPS by Sierra Semiconductor and Toshiba . In December 1987, MIPS licensed Integrated Device Technology , LSI Logic , and Performance Semiconductor to also fabricate and market the R2000. Sierra and Toshiba continued to serve as foundries. LSI fabricated
288-455: A 32-byte line size, and are virtually indexed, physically tagged . Instructions were predecoded as they enter the instruction cache by appending four bits to each instruction. These four bits specify whether can be issued together and which execution unit they are executed by. This assisted superscalar instruction issue by moving some of the dependency and conflict checking out of the critical path. The integer unit executes most instructions with
360-506: A cache controller ASIC. The design had two fully pipelined double precision multiply-add units, which could stream data from the 4 MB off-chip secondary cache. The R8000 powered SGI's POWER Challenge servers in the mid-1990s and later became available in the POWER Indigo2 workstation. Although its FPU performance fit scientific users quite well, its limited integer performance and high cost dampened appeal for most users. The R8000
432-460: A four-transistor SRAM cell, resulting in a transistor count of 3.6 million and a die that measured 8.7 mm by 9.7 mm (84.39 mm ). NEC and NKK fabricated the R5000 in a process with one level of polysilicon and three levels of aluminium interconnect. Without an extra level of polysilicon, both companies had to use a six-transistor SRAM cell, resulting in a transistor count of 5.0 million and
504-495: A large cash payment. Two companies have emerged that specialize in building multi-core processor devices using the MIPS architecture. Raza Microelectronics, Inc. bought the product line from failing SandCraft and later produced devices that contained eight cores for the telecommunication and networking markets. Cavium , originally a security processor vendor also produced devices with eight CPU cores, and later up to 32 cores, for
576-442: A larger die with an area of around 87 mm . Die sizes in the range of 80 to 90 mm were claimed by MTI. 0.8 million of the transistors in both versions were for logic, and the remainder contained in the caches. It was packaged in a 272-ball plastic ball grid array (BGA) or 223-pin ceramic pin grid array (PGA). It was not pin-compatible with any previous MIPS microprocessor. In the late 1990s, Quantum Effect Design acquired
648-517: A lesser extent the Clipper architecture and SPARC . However, as Intel quickly released faster versions of their Pentium class CPUs, Microsoft Windows NT v4.0 dropped support for anything but IA-32 and Alpha. With SGI 's decision to transition to the Itanium and IA-32 architectures in 2007 (following a 2006 Chapter 11 bankruptcy) and 2009 acquisition by Rackable Systems, Inc. , support ended for
720-515: A license to manufacture and sell MIPS microprocessors from MTI and became a microprocessor vendor, changing its name to Quantum Effect Devices to reflect its new business model. The company's first products were members of the RM52xx family, which initially consisted of two models, the RM5230 and RM5260. These were announced on 24 March 1997. The RM5230 was initially available at 100 and 133 MHz, and
792-548: A massively parallel MIPS-based supercomputer in 2007. The machines are based on the MIPS64 architecture and a high performance interconnect using a Kautz graph topology. The system is very power efficient and computationally powerful. The most innovative aspect of the system was its multicore processing node which integrates six MIPS64 cores, a crossbar switch memory controller , interconnect direct memory access (DMA) engine, Gigabit Ethernet and PCI Express controllers all on
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#1732779534068864-404: A microprocessor (microAptiv UP) with instruction and data caches and a memory management unit or as a microcontroller (microAptiv UC) with a memory protection unit (MPU). The CPU integrates DSP and SIMD functionality to address signal processing requirements for entry-level embedded segments including industrial control, smart meters, automotive and wired/wireless communications. interAptiv
936-610: A new architecture that was also named MIPS , and introduced the first MIPS implementation, the R2000 , in 1985. The R2000 was improved, and the design was introduced as the R3000 in 1988. These 32-bit CPUs formed the basis of their company through the 1980s, used primarily in Silicon Graphics ' (SGI) series of workstations and later Digital Equipment Corporation DECstation workstations and servers. The SGI commercial designs deviated from Stanford MIPS by implementing most of
1008-574: A one cycle latency and throughput except for multiply and divide. 32-bit multiplies have a five-cycle latency and a four-cycle throughput. 64-bit multiplies have an extra four cycles of latency and half the throughput. Divides have a 36-cycle latency and throughput for 32-bit integers, and for 64-bit integers, they are increased to 68 cycles. The floating-point unit (FPU) was a fast single-precision (32-bit) design, for reduced cost and to benefit SGI, whose mid-range 3D graphics workstations relied mostly on single-precision math for 3D graphics applications. It
1080-643: A projected performance of over 1 P FLOPS , will use the Loongson processor. The Dawning 6000 is currently being jointly developed by the ICT and Dawning Information Industry Company. Li Guojie, chairman of Dawning Information Industry Company and director and academician of the ICT, said research and development of the Dawning 6000 is expected to be completed in two years. By then, Chinese-made high-performance computers will be expected to achieve two major goals: first,
1152-598: A single chip which consumes only 10 watts of power, yet has a peak floating point performance of 6 giga FLOPS . The most powerful configuration, the SC5832, is a single cabinet supercomputer consisting of 972 such node chips for a total of 5832 MIPS64 processor cores and 8.2 teraFLOPS of peak performance. Loongson is a family of MIPS-compatible microprocessors designed by the Chinese Academy of Sciences ' Institute of Computing Technology (ICT). Independently designed by
1224-525: A static approach, utilizing the hints encoded by the compiler in the branch-likely instructions first introduced in the MIPS II architecture to determine how likely a branch is taken. The R5000 had large L1 caches , a distinct characteristic of QED, whose designers favored simple designs with large caches. The R5000 had two L1 caches, one for instructions and the other for data. Both have a capacity of 32 KB. The caches are two-way set-associative , have
1296-489: Is a multiprocessor core leveraging a nine-stage pipeline with multi-threading. The core can be used for highly-parallel tasks requiring cost and power optimization, such as smart gateways, baseband processing in LTE user equipment and small cells, solid-state drive (SSD) controllers, and automotive equipment. proAptiv is a superscalar, out-of-order processor core that is available in single and multi-core product versions. proAptiv
1368-662: Is designed for application processing in connected consumer electronics, and control plane processing in networking. Announced in June 2013, the MIPS Warrior family includes multiple 32-bit and 64-bit CPU products based on the MIPS Release 5 and 6 architectures. 32-bit MIPS cores for embedded and microcontroller uses: 64-bit MIPS CPUs for high-performance, low-power embedded uses: 32-bit and 64-bit MIPS application processors: The MIPS rabbit character from Super Mario 64
1440-603: The 4K and 5K . These cores can be mixed with add-in units such as floating-point units (FPU), single instruction, multiple data ( SIMD ) systems, various input/output (I/O) devices, etc. MIPS cores have been commercially successful, now having many consumer and industrial uses. MIPS cores can be found in newer Cisco , Linksys and Mikrotik's routerboard routers, cable modems and asymmetric digital subscriber line (ADSL) modems, smartcards , laser printer engines, set-top boxes , robots , and hand-held computers. In cellphones and PDAs, MIPS has been largely unable to displace
1512-634: The Cobalt Qube and Cobalt RaQ used a derivative model, the RM5230 and RM5231. The Qube 2700 used the RM5230 microprocessor, whereas the Qube 2 used the RM5231. The original RaQ systems were equipped with RM5230 or RM5231 CPUs but later models used AMD K6-2 chips and then eventually Intel Pentium III CPUs for the final models. The original roadmap called for 200 MHz operation in early 1996, 250 MHz in late 1996, succeeded in 1997 by R5000A. The R5000
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#17327795340681584-451: The 64-bit MIPS64 (based on MIPS V) for licensing. Nippon Electric Corporation ( NEC ), Toshiba , and SiByte (later acquired by Broadcom ) each obtained licenses for the MIPS64 as soon as it was announced. Philips , LSI Logic and Integrated Device Technology (IDT) have since joined them. Today, the MIPS cores are one of the most-used "heavyweight" cores in the market for computer-like devices: handheld PCs , set-top boxes, etc. Since
1656-675: The Chinese, early models lacked support for four instructions that had been patented by MIPS Technologies. In June 2009, ICT licensed the MIPS32 and MIPS64 architectures from MIPS Technologies. Starting in 2006, many companies released Loongson-based computers, including nettops and netbooks designed for low-power use. In recent years, the Loongson space dedicated chip (1E04/1E0300/1E1000,1F04/1F0300,1J) has been used on 3–5 Beidou navigation satellites. The Dawning 6000 supercomputer , which has
1728-531: The MIPS architecture is in massive processor count supercomputers. Silicon Graphics (SGI) refocused its business from desktop graphics workstations to the high-performance computing market in the early 1990s. The success of the company's first foray into server systems, the Challenge series based on the R4400 and R8000 , and later R10000 , motivated SGI to form a vastly more powerful system. The introduction of
1800-575: The MIPS architecture is licensable, it has attracted several processor start-up companies over the years. One of the first start-ups to design MIPS processors was Quantum Effect Devices (see next section). The MIPS design team that designed the R4300i started the company SandCraft , which designed the R5432 for NEC and later produced the SR71000 , one of the first out-of-order execution processors for
1872-555: The MIPS family include the R6000 , an emitter-coupled logic (ECL) implementation produced by Bipolar Integrated Technology . The R6000 introduced the MIPS II architecture. Its translation lookaside buffer (TLB) and cache architecture are different from all other members of the MIPS family. The R6000 did not deliver the promised performance benefits, and although it saw some use in Control Data machines, it quickly disappeared from
1944-731: The MIPS/IRIX consumer market in December, 2013 as originally scheduled. However, a support team still exists for special circumstances and refurbished systems that are still available on a limited basis. Through the 1990s, the MIPS architecture was widely adopted by the embedded market, including for use in computer networking , telecommunications , video arcade games , video game consoles , computer printers , digital set-top boxes , digital televisions , DSL and cable modems , and personal digital assistants . The low power-consumption and heat characteristics of embedded MIPS implementations,
2016-554: The QED designs emphasized large caches which could be accessed in just two cycles and efficient use of silicon area. The R4600 and R4700 were used in low-cost versions of the SGI Indy workstation as well as the first MIPS-based Cisco routers, such as the 36x0 and 7x00-series routers. The R4650 was used in the original WebTV set-top boxes (now Microsoft TV). The R5000 FPU had more flexible single precision floating-point scheduling than
2088-612: The R10000 preferable for most customers. Some later designs have been based upon R10000 core. The R12000 used a 0.25 micrometre process to shrink the chip and achieve higher clock rates . The revised R14000 allowed higher clock rates with added support for double data rate synchronous dynamic random-access memory ( DDR SDRAM ) static random access memory (SRAM) in the off-chip cache . Later iterations are named R16000 and R16000A , and feature higher clock rates and smaller die manufacturing compared with before. Other members of
2160-467: The R2000 microprocessor, R2010 floating-point accelerator, and four R2020 write buffer chips. The core R2000 chip executed all non-floating-point instructions with a simple short pipeline. This chip also controlled the external code and data caches, made of fast standard SRAM chips organized with direct indexing and one-cycle read latency. The R2000 chip contained a small translation lookaside buffer for mapping virtual memory addresses. The R2010 chip held
2232-519: The R2000 was followed by the R3000 , using a similar overall system design but faster chip implementation. R5000 The R5000 is a 64-bit, bi-endian , superscalar , in-order execution 2-issue design microprocessor that implements the MIPS IV instruction set architecture (ISA) developed by Quantum Effect Design (QED) in 1996. The project was funded by MIPS Technologies, Inc (MTI), also
MIPS architecture processors - Misplaced Pages Continue
2304-644: The R3000 running up to 40 MHz, the R3000A delivered a performance of 32 million instructions per second (MIPS), or VAX Unit of Performance (VUPs). The MIPS R3000A -compatible R3051 running at 33.8688 MHz was the processor used in the Sony PlayStation though it didn't have FPU or MMU. Third-party designs include Performance Semiconductor's R3400 and IDT's R3500 , both of them were R3000As with an integrated R3010 FPU. Toshiba 's R3900
2376-457: The R3000s multiprocessing support, it was successfully used in several successful multiprocessor computers. The R3000 also included a built-in memory management unit (MMU), a common feature on CPUs of the era. The R3000, like the R2000, could be paired with a R3010 FPU. The R3000 was the first successful MIPS design in the market, and eventually over one million were made. A faster version of
2448-514: The R4000, and as a result, R5000-based SGI Indys had much better graphics performance than similarly clocked R4400 Indys with the same graphics hardware. SGI gave the old graphics board a new name when it was combined with R5000 , to emphasize the improvement. QED later designed the RM7000 and RM9000 family of devices for embedded system markets like computer networking and laser printers. QED
2520-462: The R5000 are still in production today for embedded systems. Users of the R5000 in workstation and server computers were Silicon Graphics, Inc. (SGI) and Siemens-Nixdorf . SGI used the R5000 in their O2 and Indy low-end workstations. The R5000 was also used in embedded systems such as network routers and high-end printers. The R5000 found its way into the arcade gaming industry, R5000 powered mainboards were used by Atari and Midway. Initially
2592-563: The RM5231A and RM5261A, on 4 April 2001. These microprocessors were fabricated by TSMC in its 0.18 μm process and differ from the previous devices by featuring higher clock rates and lower power consumption. The RM5231A was available at clock rates of 250 to 350 MHz, and the RM5261A from 250 to 400 MHz. R5900 used in Sony's PlayStation 2 is a modified version of R5000 CPU dubbed
2664-481: The RM5260 at 133 and 150 MHz. On 29 September 1997, new 150 and 175 MHz RM5230s were introduced, as were 175 and 200 MHz RM5260s. Both the RM5230 and RM5260 are derivatives of the R5000 and differ in the size of their primary caches (16 KB each instead of 32 KB), the width of their system interfaces (the RM5230 has a 32-bit 67 MHz SysAD bus, and the RM5260 a 64-bit 75 MHz SysAD bus), and
2736-521: The RM5261 and RM5271 were available at 250 and 266 MHz. On 6 July 1999, a 300 MHz RM5271 was introduced, priced at US$ 140 in quantities of 10,000. The RM52x1 improved upon the previous family with larger 32 KB primary caches and a faster SysAD bus that supported clock rates up to 125 MHz. After QED was acquired by PMC-Sierra , the RM52xx and RM52x1 families were continued as PMC-Sierra products. PMC-Sierra introduced two RM52x1 derivatives,
2808-473: The SysAD bus with the external interface. The cache was built with custom synchronous SRAMs (SSRAMs). The microprocessor uses the SysAD bus that is also used by several other MIPS microprocessors. The bus is multiplexed (address and data share the same set of wires) and can operate at clock frequencies up to 100 MHz. The initial R5000 did not support multiprocessing , but the package reserved eight pins for
2880-535: The addition of multiply-add and three-operand multiply instructions for digital signal processing applications. These microprocessors were fabricated by the Taiwan Semiconductor Manufacturing Company (TSMC) in its 0.35 μm process with three levels of interconnect. They were packaged by Amkor Technology in its Power-Quad 4 packages, the RM5230 in a 128-pin version, and the RM5260 in a 208-pin version. The RM52xx family
2952-607: The adoption of domestically made processors; second, the existing cluster-based system structure of high-performance computers will be changed once performance reaches 1 PFLOPS. Announced in 2012, the MIPS Aptiv family includes three 32-bit CPU products based on the MIPS32 Release 3 architecture. microAptiv is a compact, real-time embedded processor core with a five-stage pipeline and the microMIPS code compression instruction set. microAptiv can be either configured as
MIPS architecture processors - Misplaced Pages Continue
3024-541: The architecture include SGI's IRIX , Microsoft 's Windows NT (through v4.0), Windows CE , Linux , FreeBSD , NetBSD , OpenBSD , UNIX System V , SINIX , QNX , and MIPS Computer Systems' own RISC/os . In the early 1990s, speculation occurred that MIPS and other powerful RISC processors would overtake the Intel IA-32 architecture. This was encouraged by the support of the first two versions of Microsoft 's Windows NT for Alpha , MIPS and PowerPC , and to
3096-620: The chip set in its 2.0 μm double-metal CMOS process and marketed it as the LR2000. Performance Semiconductor fabricated the chip set in its PACE-I 0.8 μm double-metal CMOS process and marketed it as the PR2000. In 1988, an improved version was introduced, the R2000A. It was composed of the R2000A and R2010A ICs. It operated at 12.5 and 16.67 MHz. It has been used extensively in embedded applications such as printer controllers. In 1988,
3168-432: The clock frequency, the caches were reduced to 8 KB each and they took three cycles to access. The high clock rates were achieved through the method of deep pipelining (called super-pipelining then). The improved R4400 followed in 1993. It had larger 16 KB primary caches, largely bug-free 64-bit operation, and support for a larger L2 cache. MIPS, now a division of Silicon Graphics (SGI) named MTI, designed
3240-566: The designers considered it a potential bottleneck), a feature it shares with the AMD 29000 , the DEC Alpha , and RISC-V . Unlike other registers, the program counter is not directly accessible. The R2000 also had support for up to four co-processors, one of which was built into the main central processing unit (CPU) and handled exceptions, traps and memory management, while the other three were left for other uses. One of these could be filled by
3312-555: The embedded market. The original DEC StrongARM team eventually split into two MIPS-based start-ups: SiByte which produced the SB-1250 , one of the first high-performance MIPS-based systems-on-a-chip (SOC); while Alchemy Semiconductor (later acquired by AMD ) produced the Au-1000 SoC for low-power uses. Lexra used a MIPS- like architecture and added DSP extensions for the audio chip market and multithreading support for
3384-471: The first Acorn RISC Machine (ARM) evaluation kits shipping to developers. Overall speed was limited by the cache size and cache cycle time. The R2000 chip set and SRAM was initially sold only as a complete circuit board to ensure good cache bus timings. In 1987 system builders began using the chip set in arbitrary new board designs. The R2000 was available in 8.3, 12.5 and 15 MHz grades. The die contained 110,000 transistors and measured 80 mm in
3456-478: The floating point registers, floating point data paths, and their longer simple pipeline. Writes to main memory DRAM took tens of cycles to fully complete. But the R2020 chips queued and completed up to 4 pending writes to main memory, allowing the R2000 core to proceed without stalling itself. In the absence of cache misses, this chip set sustained an instruction completion rate of one instruction per ALU cycle. This
3528-481: The future addition of this feature. QED was a fabless company and did not fabricate their own designs. The R5000 was fabricated by IDT, NEC and NKK. All three companies fabricated the R5000 in a 0.35 μm complementary metal–oxide–semiconductor (CMOS) process, but with different process features. IDT fabricated the R5000 in a process with two levels of polysilicon and three levels of aluminium interconnect . The two levels of polysilicon enabled IDT to use
3600-675: The incumbent, competing ARM architecture . MIPS architecture processors include: IDT RC32438; ATI/AMD Xilleon ; Alchemy Au1000, 1100, 1200; Broadcom Sentry5; RMI XLR7xx, Cavium Octeon CN30xx, CN31xx, CN36xx, CN38xx and CN5xxx; Infineon Technologies EasyPort, Amazon, Danube, ADM5120, WildPass, INCA-IP, INCA-IP2; Microchip Technology PIC32; NEC EMMA and EMMA2, NEC VR4181A, VR4121, VR4122, VR4181A, VR4300, VR5432, VR5500; Oak Technologies Generation; PMC-Sierra RM11200; QuickLogic QuickMIPS ESP; Toshiba Donau , Toshiba TMPR492x, TX4925, TX9956, TX7901; KOMDIV-32 , KOMDIV-64 , ELVEES Multicore from Russia. One interesting, less common use of
3672-620: The integrated R10000 allowed SGI to produce a system, the Origin 2000 , eventually scalable to 1024 CPUs using its NUMAlink cc-NUMA interconnect. The Origin 2000 begat the Origin 3000 series which topped out with the same 1,024 maximum CPU count but using the R14000 and R16000 chips up to 700 MHz. Its MIPS-based supercomputers were withdrawn in 2005 when SGI made the strategic decision to move to Intel's Itanium IA-64 architecture. A high-performance computing startup named SiCortex introduced
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#17327795340683744-532: The interlocks in hardware, supplying full multiply and divide instructions (among others). The designs were guided, in part, by software architect Earl Killian who designed the MIPS III 64-bit instruction-set extension, and led the work on the R4000 microarchitecture. In 1991 MIPS released the first 64-bit microprocessor , the R4000 . However, MIPS had financial difficulties while bringing it to market. The design
3816-572: The licensor. MTI then licensed the design to Integrated Device Technology (IDT), NEC , NKK , and Toshiba . The R5000 succeeded the QED R4600 and R4700 as their flagship high-end embedded microprocessor. IDT marketed its version of the R5000 as the 79RV5000, NEC as VR5000, NKK as the NR5000, and Toshiba as the TX5000. The R5000 was sold to PMC-Sierra when the company acquired QED. Derivatives of
3888-743: The low-cost R4200 , the basis for the even cheaper R4300i . A derivative of this microprocessor, the NEC VR4300, was used in the Nintendo 64 game console. Quantum Effect Devices (QED), a separate company started by former MIPS employees, designed the R4600 Orion , the R4700 Orion , the R4650 and the R5000 . Where the R4000 had pushed clock frequency and sacrificed cache capacity,
3960-474: The mainstream market. In 1981, John L. Hennessy began the Microprocessor without Interlocked Pipeline Stages ( MIPS ) project at Stanford University to investigate reduced instruction set computer (RISC) technology. The results of his research convinced him of the future commercial potential of the technology, and in 1984, he took a sabbatical to found MIPS Computer Systems . The company designed
4032-484: The networking market. Due to Lexra not licensing the architecture, two lawsuits were started between the two companies. The first was quickly resolved when Lexra promised not to advertise their processors as MIPS-compatible. The second (about MIPS patent 4814976 for handling unaligned memory access) was protracted, hurt both companies' business, and culminated in MIPS Technologies giving Lexra a free license and
4104-400: The optional R2010 floating-point unit (FPU), which had thirty-two 32-bit registers that could be used as sixteen 64-bit registers for double-precision. The R3000 succeeded the R2000 in 1988, adding 32 KB (soon raised to 64 KB) caches for instructions and data, and support for shared-memory multiprocessing in the form of a cache coherence protocol. While there were flaws in
4176-430: The same markets. Both of these firms designed their cores in-house, only licensing the architecture instead of buying cores from MIPS. Among the manufacturers which have made computer workstation systems using MIPS processors are SGI , MIPS Computer Systems, Inc. , Whitechapel Workstations , Olivetti , Siemens-Nixdorf , Acer , Digital Equipment Corporation , NEC , and DeskStation . Operating systems ported to
4248-485: The two are strongly related: the price of a CPU is generally related to the number of gates and the number of external pins. Sun Microsystems attempted to enjoy similar success by licensing their SPARC core but was not nearly as successful. By the late 1990s, MIPS was a powerhouse in the embedded processor field. According to MIPS Technologies Inc., there was an exponential growth, with 48-million MIPS-based CPU shipments and 49% of total RISC CPU market share in 1997. MIPS
4320-437: The wide availability of embedded development tools, and knowledge about the architecture means use of MIPS microprocessors in embedded roles is likely to remain common. In recent years most of the technology used in the various MIPS generations has been offered as semiconductor intellectual property cores (IP cores), as building blocks for embedded processor designs. Both 32-bit and 64-bit basic cores are offered, known as
4392-558: Was a virtually first system on a chip (SoC) for the early handheld PCs that ran Windows CE . A radiation-hardened variant for outer space use, the Mongoose-V , is a R3000 with an integrated R3010 FPU. The R4000 series, released in 1991, extended MIPS to a full 64-bit word design, moved the FPU onto the main die to form a single-chip microprocessor, and had a then high clock rate of 100 MHz at introduction. However, to achieve
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#17327795340684464-476: Was acquired by the semiconductor manufacturer PMC-Sierra in August 2000, the latter company continuing to invest in the MIPS architecture. The RM7000 included an integrated 256 KB L2 cache and a controller for optional L3 cache. The RM9xx0 were a family of SOC devices which included northbridge peripherals such as memory controller , PCI controller, Gigabit Ethernet controller and fast I/O such as
4536-539: Was fully pipelined, which made it significantly better than that of the R4700 . The R5000 implements the multiply-add instruction of the MIPS IV ISA. Single-precision adds, multiplies and multiply-adds have a four-cycle latency and a one cycle throughput. Single-precision divides have a 21-cycle latency and a 19-cycle throughput, while square roots have a 26-cycle latency and a 38-cycle throughput. Division and square-root
4608-883: Was introduced in January 1996 and failed to achieve 200 MHz, topping out at 180 MHz. When positioned as a low-end workstation microprocessor, the competition included the IBM and Motorola PowerPC 604 , the HP PA-7300LC and the Intel Pentium Pro . The R5000 is a two-way superscalar design that executes instructions in-order . The R5000 could simultaneously issue an integer and a floating-point instruction. It had one simple pipeline for integer instructions and another for floating-point to save transistors and die area to reduce cost. The R5000 did not perform dynamic branch prediction for cost reasons. Instead it uses
4680-621: Was later joined by the RM5270, which was announced at the Embedded Systems Conference on 29 September 1997. Intended for high-end embedded applications, the RM5270 was available at 150 and 200 MHz. Improvements were the addition of an on-chip secondary cache controller that supported up to 2 MB of cache. The SysAD bus is 64 bits wide and can operate at 100 MHz. It was packaged in a 304-pin Super-BGA (SBGA) that
4752-544: Was more efficient than non-RISC microprocessors of that time, which needed several cycles per instruction. The initial R2000A, clocked at 12.5 MHz, offered 8-10 Million integer Instructions Per Second (MIPS), or 0.9 Million FLoating Point Operations Per Second (MFLOPS), and would appear in the like of the 1987 SGI IRIS 4D and 1988 DECstation 2100 workstations. 1986 also saw similar technology in Sun's first SPARC microprocessor, Hewlett Packard's first PA-RISC microprocessor, and
4824-755: Was named after the MIPS microprocessor. R2000 (microprocessor) The R2000 is a 32-bit microprocessor chip set developed by MIPS Computer Systems that implemented the MIPS I instruction set architecture (ISA). Introduced in January 1986, it was, by a few months, the first commercial implementation of the RISC architecture. The R2000 competed with Digital Equipment Corporation (DEC) VAX minicomputers and with Motorola 68000 and Intel Corporation 80386 microprocessors. R2000 users included Ardent Computer , DEC, Silicon Graphics , Northern Telecom and MIPS's own Unix workstations. The chip set consisted of
4896-551: Was not pipelined. Instructions that operate on double precision numbers have a significantly higher latency and lower throughput except for add, which has identical latency and throughput with single-precision add. Multiply and multiply-add have a five-cycle latency and a two-cycle throughput. Divide has a 36-cycle latency and a 34-cycle throughput. Square root has a 68-cycle latency and a 66-cycle throughput. The R5000 had an integrated L2 cache controller that supported capacities of 512 KB, 1 MB and 2 MB. The L2 cache shares
4968-583: Was pin-compatible with the RM7000 and was offered as a migration path to the RM7000. On 20 July 1998, the RM52x1 family was announced. The family consisted of the RM5231, RM5261, and RM5271. These microprocessors were derivatives of the corresponding devices from the RM52x0 family fabricated in a 0.25 μm process with four levels of metal. The RM5231 was initially available at 150, 200, and 250 MHz; whereas
5040-517: Was so important to SGI, at the time one of MIPS' few major customers, that SGI bought the company in 1992 to guarantee the design would not be lost. The new SGI subsidiary was named MIPS Technologies . In the early 1990s, MIPS began to license their designs to third-party vendors. This proved fairly successful due to the simplicity of the core, which allowed it to have many uses that would have formerly used much less able complex instruction set computer (CISC) designs of similar gate count and price;
5112-428: Was so successful that SGI spun off MIPS Technologies in 1998. In 2000s fully half of MIPS's income came from licensing their designs, while much of the rest came from contract design work on cores for third parties. In 1999, MIPS Technologies replaced the previous versions of the MIPS architecture with two architectures, the 32-bit MIPS32 (based on MIPS II with some added features from MIPS III, MIPS IV, and MIPS V) and
5184-549: Was sold for only a year and remains fairly rare. In 1995, the R10000 was released. This processor was a single-chip design, ran at a higher clock frequency than the R8000, and had larger 32 KB primary instruction and data caches. It was also superscalar, but its major innovation was out-of-order execution . Even with one memory pipeline and simpler FPU, the vastly improved integer performance, lower price, and higher density made
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