Misplaced Pages

#333666

56-482: MIPS Tech LLC , formerly MIPS Computer Systems, Inc. and MIPS Technologies, Inc. , is an American fabless semiconductor design company that is most widely known for developing the MIPS architecture and a series of RISC CPU chips based on it. MIPS provides processor architectures and cores for digital home, networking, embedded, Internet of things and mobile applications. MIPS was founded in 1984 to commercialize

112-587: A Unix workstation based on the MIPS design. After developing the R2000 and R3000 microprocessors, a management change brought along the larger dreams of being a computer vendor. The company found itself unable to compete in the computer market against much larger companies and was struggling to support the costs of developing both the chips and the systems ( MIPS Magnum ). To secure the supply of future generations of MIPS microprocessors (the 64-bit R4000 ), SGI acquired

168-427: A cache miss , the data must be loaded from the streaming cache with an eight-cycle penalty. The cache is virtually indexed, physically tagged , direct mapped , has a 32-byte line size and uses a write-through with allocate protocol. If the loads hit in the data cache, the result is written to the integer register file in stage five. The R8010 executed floating-point instructions provided by an instruction queue on

224-418: A 32-byte line size. Instruction decoding and register reads occur during stage two, and branch instructions are resolved as well, leading to a one-cycle branch mispredict penalty. Load and store instructions begin execution in stage three, and integer instructions in stage four. Integer execution was delayed until stage four so that integer instructions which use the result of a load as an operand may be issued in

280-498: A decade, Microchip Technology , which leverages MIPS processors for its 32-bit PIC32 microcontrollers, Qualcomm Atheros , MediaTek and Mobileye , whose EyeQ chips are based on cores licensed from MIPS. The first announced licensee for MIPS' RISC-V CPUs is Mobileye , who adopted the MIPS eVocore P8700 for autonomous driving SoCs. MIPS is widely supported by Unix-like systems, including Linux , FreeBSD , NetBSD , and OpenBSD . Google's processor-agnostic Android operating system

336-556: A floating-point throughput of 300 million instructions per second, a SPECfp92 rating of 310, and a more modest SPECint92 rating of 108. The chip set consisted of the R8000 microprocessor, the R8010 floating-point unit, two Tag RAMs, and the streaming cache. The R8000 is superscalar , capable of issuing up to four instructions per cycle, and executes instructions in program order. It has a five-stage integer pipeline . The R8000 controlled

392-457: A fraction of the cost and size, making computers with this level of performance more accessible and enabling deskside workstations and servers to replace supercomputers in many situations. First details of the R8000 emerged in April 1992 in an announcement by MIPS Computer Systems detailing future MIPS microprocessors. In March 1992, SGI announced it was acquiring MIPS Computer Systems, which became

448-424: A high-performance 32-bit instruction set architecture (ISA) that is used in applications such as 32-bit microcontrollers, home entertainment, home networking devices and mobile designs. MIPS customers license the architecture to develop their own processors or license off-the-shelf cores from MIPS that are based on the architecture. The MIPS64 architecture is a high performance 64-bit instruction set architecture that

504-604: A load queue, a store queue, and two identical floating-point units. All instructions except for divide and square-root are pipelined. The R8010 implements an iterative division and square-root algorithm that uses the multiplier for a key part, requiring the pipeline to be stalled the unit for the duration of the operation. Arithmetic instructions except for compares have a four-cycle latency. Single and double precision divides have latencies of 14 and 20 cycles, respectively; and single and double precision square-roots have latencies of 14 and 23 cycles, respectively. The streaming cache

560-563: A project called MIPS (for Microprocessor without Interlocked Pipeline Stages ), one of the projects that pioneered the RISC concept. Other principal founders were Skip Stritter, formerly a Motorola technologist, and John Moussouris, formerly of IBM. The initial CEO was Vaemond Crane, formerly President and CEO of Computer Consoles Inc. , who arrived in February 1985 and departed in June 1989. He

616-513: A standard CDC Aerospace Computer and was used in the Spy in the Sky Satellites in addition to other classified satellite programs. GIM was reluctant to proceed with the next phase of the program, which it deemed to be too technically challenging. The GIM engineers who had worked on the project were encouraged by CDC to form their own company to provide five new custom circuits. This resulted in

SECTION 10

#1732787551334

672-513: A subsidiary of SGI called MIPS Technologies, Inc. (MTI) in mid-1992. Development of the R8000 was transferred to MTI, where it continued. The R8000 was expected to be introduced in 1993, but it was delayed until mid-1994. The first R8000, a 75 MHz part, was introduced on 7 June 1994. It was priced at US$ 2,500 at the time. In mid-1995, a 90 MHz part appeared in systems from SGI. The R8000's high cost and narrow market (technical and scientific computing) restricted its market share, and although it

728-522: Is a microprocessor chipset developed by MIPS Technologies, Inc. (MTI), Toshiba , and Weitek . It was the first implementation of the MIPS IV instruction set architecture . The R8000 is also known as the TFP , for Tremendous Floating-Point , its name during development. Development of the R8000 started in the early 1990s at Silicon Graphics , Inc. (SGI). The R8000 was specifically designed to provide

784-926: Is an embedded operating system based on the Linux kernel. While it currently runs on a variety of processor architectures, it was originally developed for the Linksys WRT54G , which used a 32-bit MIPS processor from Broadcom. The OpenWrt Table of Hardware now includes MIPS-based devices from Atheros, Broadcom, Cavium, Lantiq, MediaTek, etc. Real-time operating systems that run on MIPS include CMX Systems , eCosCentric 's eCos , ENEA OSE , Express Logic's ThreadX , FreeRTOS , Green Hills Software 's Integrity , LynuxWorks ' LynxOS , Mentor Graphics , Micrium's Micro-Controller Operating Systems (μC/OS) , QNX Software Systems ' QNX , Quadros Systems Inc.'s RTXC Quadros RTOS, Segger 's embOS and Wind River 's VxWorks . Fabless semiconductor company Fabless manufacturing

840-491: Is an external 1 to 16 MB cache that serves as the R8000's L2 unified cache and the R8010's L1 data cache. It operates at the same clock rate as the R8000 and is built from commodity synchronous static RAMs . This scheme was used to attain sustained floating point performance, which requires frequent access to data. A small low-latency primary cache would not contain enough data and frequently miss, necessitating long latency refiles that reduce performance. The streaming cache

896-488: Is built on the Linux kernel. MIPS originally ported Android to its architecture for embedded products beyond the mobile handset , where it was originally targeted by Google but MIPS support was dropped in 2018. In 2010, MIPS and its licensee Sigma Designs announced the world's first Android set-top boxes. By porting to Android, MIPS processors power smartphones and tablets running on the Android operating system. OpenWrt

952-477: Is the design and sale of hardware devices and semiconductor chips while outsourcing their fabrication (or fab ) to a specialized manufacturer called a semiconductor foundry . These foundries are typically, but not exclusively, located in the United States , China , and Taiwan . Fabless companies can benefit from lower capital costs while concentrating their research and development resources on

1008-459: Is two-way interleaved . It has two independent banks , each containing data from even or odd addresses. It can therefore perform two reads, two writes, or a read and a write every cycle, provided that the two accesses are to separate banks. Each bank is accessed via two 64-bit unidirectional buses, one for reads, and the other for writes. This scheme was used to avoid bus turnover , which is required by bidirectional buses. By avoiding bus turnover,

1064-549: Is widely used in networking infrastructure equipment through MIPS licensees such as Cavium Networks and Broadcom. SmartCE (Connected Entertainment) is a reference platform that integrates Android , Adobe Flash platform for TV, Skype , the Home Jinni ConnecTV application and other applications. SmartCE lets OEM customers create integrated products more quickly. The MIPS processor cores are divided by Imagination into three major families: The MIPS eVocore CPUs are

1120-668: The Itanium architecture in 1998. As a result, MIPS was spun out as an intellectual property licensing company, offering licences to the MIPS architecture as well as microprocessor core designs. On June 30, 1998, MIPS held an IPO after raising about $ 16.3 million with an offering price of $ 14 a share. In 1999, SGI announced it would overhaul its operations; it planned to continue introducing new MIPS processors until 2002, but its server business would include Intel's processor architectures as well. SGI spun MIPS out completely on June 20, 2000, by distributing all its interest as stock dividend to

1176-485: The game console space. In 1998, SGI announced they would be transitioning off MIPS and spun off the company. After several years operating as an independent design house, in 2013 the company was purchased by Imagination Technologies , best known for their PowerVR graphics processor family. They were sold to Tallwood Venture Capital in 2017 and then purchased soon after by Wave Computing in 2018. Wave declared bankruptcy in 2020, emerging in 2021 as MIPS and announcing that

SECTION 20

#1732787551334

1232-459: The Cruz tablets from Velocity Micro. TCL Corporation is using MIPS processors for the development of smartphones. Companies can also obtain an MIPS architectural licence for designing their own CPU cores using the MIPS architecture. Distinct MIPS architecture implementations by licensees include Broadcom's BRCM 5000. Other licensees include Broadcom , which has developed MIPS-based CPUs for over

1288-568: The ICs. These parts were given the designation LSI3201, LSI3202, LSI3203, LSI3204 and LSI3205. Another successful space program completed by LSI/CSI was the upgrade to class S of a Standard Brushless DC Motor Commutator/Controller Chip, LS7262, which was implemented in satellites. In 1994, Jodi Shelton , along with a half a dozen CEOs of fabless companies, established the Fabless Semiconductor Association (FSA) to promote

1344-471: The MIPS architecture was being abandoned in favor of RISC-V designs. In May 2022, MIPS previewed its first RISC-V CPU IP cores, the eVocore P8700 and I8500 multiprocessors. In December 2022, MIPS announced availability of the P8700. MIPS Computer Systems Inc. was founded in 1984 by a group of researchers from Stanford University including John L. Hennessy and Chris Rowen . These researchers had worked on

1400-505: The MIPS processor business to a California-based investment company, Tallwood Venture Capital. Tallwood in turn sold the business to Wave Computing in 2018, both of these companies reportedly having their origins with, or ownership links to, a co-founder of Chips and Technologies and S3 Graphics . Despite the regulatory obstacles that had forced Imagination to divest itself of the MIPS business prior to its own acquisition by Canyon Bridge, bankruptcy proceedings for Wave Computing indicated that

1456-699: The Motorola 68000 series of processors was "at the end of its price-performance curve". Identifying the "time-to-market issues" of companies introducing workstation products, MIPS introduced a range of component kits, processor boards and memory boards, intended as "building blocks" for such companies to build into systems. Additionally, development systems such as the M/500 were sold, intended to support software development at systems vendors building MIPS-based hardware products. In December 1989, MIPS held its first IPO . That year, Digital Equipment Corporation (DEC) released

1512-411: The R8000. The queue decoupled the floating-point pipeline from the integer pipeline, implementing a limited form of out-of-order execution by allowing floating-point instructions to execute when possible after or before the integer instructions from the same group are issued. The pipelines were decoupled to help mitigate some of the streaming cache latency. It contained the floating-point register file,

1568-433: The assembly and testing of their own chips. As with most technology-intensive industries, the silicon manufacturing process presents high barriers to entry into the market, especially for small start-up companies. But integrated device manufacturers (IDMs) had excess production capacity. This presented an opportunity for smaller companies, relying on IDMs, to design but not manufacture silicon. These conditions underlay

1624-472: The base(register) + index(register) address style added in the MIPS IV ISA. The R8000 issues at most one integer store per cycle, and one final read port delivers the integer store data. Two register file write ports are used to write results from the two integer functional units. The R8000 issues two integer loads per cycle, and the other two write ports are used to write the results of integer loads to

1680-466: The birth of the fabless business model . Engineers at new companies began designing and selling integrated circuits (ICs) without owning a fabrication plant. Simultaneously, the foundry industry was established by Dr. Morris Chang with the founding of Taiwan Semiconductor Manufacturing Corporation (TSMC). Foundries became the cornerstone of the fabless model, providing a non-competitive manufacturing partner for fabless companies. The co-founders of

1736-519: The cache can be read from in one cycle and then written to in the next cycle without an intervening cycle for turnover, resulting in improved performance. The streaming cache's tags are contained on two Tag RAM chips, one for each bank. Both chips contain identical data. Each chip contains 1.189 Mbit of cache tags implemented by four-transistor SRAM cells. The chips are implemented in a 0.7 μm BiCMOS process with two levels of polysilicon and two levels of aluminium interconnect . BiCMOS circuitry

MIPS Technologies - Misplaced Pages Continue

1792-415: The chip set and executed integer instructions. It contained the integer execution units, integer register file , primary caches and hardware for instruction fetch, branch prediction the translation lookaside buffers (TLBs). In stage one, four instructions are fetched from the instruction cache. The instruction cache is 16 kB large, direct-mapped , virtually tagged and virtually indexed , and has

1848-625: The company had in 2018 and 2019 transferred full licensing rights for the MIPS architecture for China, Hong Kong and Macau to CIP United, a Shanghai-based company. In 2021, MIPS announced it would begin making chips based on the RISC-V architecture. In 2022, the company announced availability of its first RISC-V CPU IP core, the eVocore P8700. In September 2023, MIPS named former Texas Instruments (TI) executive Sameer Wasson CEO. Wasson spent 18 years at TI, most recently as vice president, Business Unit (BU) Manager, Processors. MIPS Technologies created

1904-565: The company in 1992 for $ 333 million and renamed it as MIPS Technologies Inc., a wholly owned subsidiary of SGI. During SGI's ownership of MIPS, the company introduced the R8000 in 1994 and the R10000 in 1996 and a follow-up the R12000 in 1997. During this time, two future microprocessors code-named The Beast and Capitan were in development; these were cancelled after SGI decided to migrate to

1960-410: The cycle after the load. Results are written to the integer register file in stage five. The integer register file has nine read ports and four write ports. Four read ports supply operands to the two integer execution units (the branch unit was considered part of an integer unit). Another four read ports supply operands to the two address generators. Four ports are needed, rather than two, because of

2016-648: The digital home, the company's processors were predominantly found in digital TVs and set-top boxes. The Sony PlayStation Portable used two processors based on the MIPS32 4K processor. Within the networking segment, licensees include Cavium Networks and Broadcom. Cavium has used up to 48 MIPS cores for its OCTEON family network reference designs. Broadcom ships Linux-ready MIPS64-based XLP, XLR, and XLS multicore, multithreaded processors. Licensees using MIPS to build smartphones and tablets include Actions Semiconductor and Ingenic Semiconductor . Tablets based on MIPS include

2072-420: The end market. Some fabless companies and pure play foundries (like TSMC ) may offer integrated-circuit design services to third parties. Prior to the 1980s, the semiconductor industry was vertically integrated . Semiconductor companies owned and operated their own silicon-wafer fabrication facilities and developed their own process technology for manufacturing their chips. These companies also carried out

2128-780: The fabless business-model globally. In December 2007, the FSA transitioned to the GSA, the Global Semiconductor Alliance . The organizational transition reflected the role FSA had played as a global organization that collaborated with other organizations to co-host international events. The fabless manufacturing model has been further validated by the conversion of major IDMs to a completely fabless model, including (for example) Conexant Systems , Semtech , and most recently, LSI Logic . Today most major IDMs including Apple Inc. , Infineon and Cypress Semiconductor have adopted

2184-412: The first RISC-V CPU IP cores from MIPS. Both cores provide support for privileged hardware virtualization, user defined custom extensions, multi-threading, hybrid debug, and functional safety. They include: MIPS Technologies had a strong customer licensee base in home electronics and portable media players ; for example, 75 percent of Blu-ray Disc players were running on MIPS Technologies processors. In

2240-463: The first fabless semiconductor company, LSI Computer Systems, Inc. (LSI/CSI) LSI/CSI, worked together at General Instrument Microelectronics (GIM) in the 1960s. In 1969 GIM was hired to develop three full custom CPU circuits for Control Data Corporation (CDC). These CPU ICs operated at 5 MHz (state of the art at the time) and were incorporated in the CDC Computer 469. The Computer 469 became

2296-471: The first quarter of 2013, 498 out of 580 of MIPS patents were sold to Bridge Crossing which was created by Allied Security Trust , with all processor-specific patents and the other parts of the company sold to Imagination Technologies . Imagination had outbid Ceva Inc to buy MIPS with an offer of $ 100 million, and was investing to develop the architecture for the embedded processor market. In 2017, under financial pressure itself, Imagination Technologies sold

MIPS Technologies - Misplaced Pages Continue

2352-455: The following: CDC's Aerospace Computer 469 weighed one pound, consumed a total of 10 watts and ran at 5 MHz. CDC ran a parallel program, developing a chipset of eight similar parts that were to operate at 2.5 MHz with the identical environmental and Class S requirements. CDC had initial difficulties with this project, but eventually awarded another contract to LSI/CSI to manage the processing, inspection, visuals, assembly, and testing of

2408-452: The formation of LSI Computer Systems, Inc. (LSI/CSI) in 1969. The new chips were power-efficient random logic circuits with extremely high circuit densities. These new circuits also operated at 5 MHz. These devices were designated LSI0101, LSI0102, LSI0103, LSI0104, and LSI0105 and were manufactured in compact 40-pin metal flat packs with 0.050 inches (1.3 mm) spacing. In creating the fabless semiconductor industry, LSI/CSI had to do

2464-470: The multiply-divide unit, which is not pipelined. As a result, the latency for a multiply instruction is four cycles for 32-bit operands and six cycles for 64-bit. The latency for a divide instruction depends on the number of significant digits in the result and thus it varies from 21 to 73 cycles. Loads and stores begin execution in stage three. The R8000 has two address generation units (AGUs) that calculate virtual address for loads and stores. In stage four,

2520-450: The performance of circa 1990s supercomputers with a microprocessor instead of a central processing unit (CPU) built from many discrete components such as gate arrays . At the time, the performance of traditional supercomputers was not advancing as rapidly as reduced instruction set computer (RISC) microprocessors. It was predicted that RISC microprocessors would eventually match the performance of more expensive and larger supercomputers at

2576-634: The practice of outsourcing chip manufacturing as a significant manufacturing strategy. The top 5 sales leaders for fabless companies in 2023 were: The top 5 sales leaders for fabless companies in 2020 were: The top 5 sales leaders for fabless companies in 2019 were: The top 5 sales leaders for fabless companies in 2017 were: The top 5 sales leaders for fabless companies in 2013 were: The top 5 sales leaders for fabless companies in 2011 were: The top 5 sales leaders for fabless companies in 2010 were: The top 5 sales leaders for fabless companies in 2003 were: R8000 The R8000

2632-399: The processor architecture that is licensed to chip makers. Before the acquisition, the company had 125+ licensees who ship more than 500 million MIPS-based processors each year. MIPS processor architectures and cores are used in home entertainment, networking and communications products. The company licensed its 32- and 64-bit architectures as well as 32-bit cores. The MIPS32 architecture is

2688-420: The register file. The level 1 data cache was organized as two redundant arrays, each of which had one read port and one write port. Integer stores were written to both arrays. Two loads could be processed in parallel, one on each array. Integer functional units consisted of two integer units, a shift unit, a multiply-divide unit, and two address generator units. Multiply and divide instructions are executed in

2744-665: The stockholders. In early 2008 MIPS laid off 28 employees from its processor business group. On August 13, 2008, MIPS announced a loss of $ 108.5 million for their fiscal fourth-quarter and that they would lay off another 15% of their workforce. At the time MIPS had 512 employees. In May 2018, according to the company's presence on LinkedIn, there may be less than 50 employees. Notable people who have worked at MIPS include James Billmaier , Steve Blank , Joseph DiNucci, John L. Hennessy , Todd Bezenek , David Hitz , Earl Killian, Dan Levin, John Mashey , John P. McCaskey, Bob Miller, Stratton Sclavos , and Skip Stritter . In 2010, Sandeep Vij

2800-688: The usual way of implementing set-associative caches. Access to the streaming cache is pipelined to mitigate some of the latency. The pipeline has five stages: in stage one, addresses are sent to the Tag RAMs, which are accessed in stage two. Stage three is for the signals from the Tag RAMs to propagate to the SSRAMs. In stage four, the SSRAMs are accessed and data is returned to the R8000 or R8010 in stage five. The R8000 contained 2.6 million transistors and measured 17.34 mm by 17.30 mm (299.98 mm ). The R8010 contained 830,000 transistors. In total,

2856-407: The virtual addresses are translated to physical addresses by a dual-ported TLB that contains 384 entries and is three-way set associative. The 16 kB data cache is accessed in the same cycle. It is dual-ported, and is accessed via two 64-bit buses. It can service two loads or one load and one store per cycle. The cache is not protected by parity or by error correcting code (ECC). In the event of

SECTION 50

#1732787551334

2912-484: The work being carried out at Stanford University on the MIPS architecture , a pioneering RISC design. The company generated intense interest in the late 1980s, seeing design wins with Digital Equipment Corporation (DEC) and Silicon Graphics (SGI), among others. By the early 1990s the market was crowded with new RISC designs and further design wins were limited. The company was purchased by SGI in 1992, by that time its only major customer, and won several new designs in

2968-1081: Was named CEO of MIPS Technologies. Vij studied under John Hennessy as a Stanford University graduate student. Prior to taking over at MIPS, Vij was an executive at Cavium Networks , Xilinx and Altera . EE Times reported that MIPS had 150 employees as of November 1, 2010. If the August 14, 2008 EDN article was accurate about MIPS having over 500 employees at the time, then MIPS reduced their total workforce by 70% between 2008 and 2010. In addition to its main R&;D center in Sunnyvale, California , MIPS has engineering facilities in Shanghai , China , Beaverton, Oregon , Bristol and Kings Langley , both in England . It also has offices in Hsin-chu, Taiwan ; Tokyo, Japan ; Remscheid, Germany and Haifa, Israel . During

3024-575: Was popular in its intended market, it was largely replaced with the cheaper and generally better performing R10000 introduced January 1996. Users of the R8000 were SGI, who used it in their Power Indigo2 workstation , Power Challenge server, Power ChallengeArray cluster and Power Onyx visualization system. In the November 1994 TOP500 list, 50 systems out of 500 used the R8000. The highest ranked R8000-based systems were four Power Challenges at positions 154 to 157. Each had 18 R8000s. SGI claimed

3080-459: Was replaced by Bob Miller, a former senior IBM and Data General executive. Miller ran the company through its IPO and subsequent sale to Silicon Graphics. In 1986, MIPS Computer Systems designs were noticed by companies such as Cadnetix, Prime Computer and Silicon Graphics (SGI), these adopting the R2000 for new products, with SGI adopting the MIPS architecture for its computers having noted that

3136-542: Was used in the decoders and combined sense amplifier and comparator portions of the chip to reduce cycle time. Each Tag RAM is 14.8 mm by 14.8 mm large, packaged in a 155-pin CPGA, and dissipates 3 W at 75 MHz. In addition to providing the cache tags, the Tag RAMs are responsible for the streaming cache being four-way set associative. To avoid high a pin count, the cache tags are four-way set associative and logic selects which set to access after lookup instead of

#333666