Misplaced Pages

#590409

61-762: A DIP is usually referred to as a DIP n , where n is the total number of pins, and sometimes appended with the row-to-row package width "N" for narrow (0.3") or "W" for wide (0.6"). For example, a microcircuit package with two rows of seven vertical leads would be a DIP14 or DIP14N. The photograph at the upper right shows three DIP14 ICs. Common packages have as few as three and as many as 64 leads. Many analog and digital integrated circuit types are available in DIP packages, as are arrays of transistors, switches, light emitting diodes, and resistors. DIP plugs for ribbon cables can be used with standard IC sockets. DIP packages are usually made from an opaque molded epoxy plastic pressed around

122-598: A QIL package , has the same dimensions as a DIL package, but the leads on each side are bent into an alternating zigzag configuration so as to fit four lines of solder pads (instead of two with a DIL). The QIL design increased the spacing between solder pads without increasing package size, for two reasons: Commonly found DIP packages that conform to JEDEC standards use an inter-lead spacing (lead pitch) of 0.1 inches (2.54 mm) (JEDEC MS-001BA). Row spacing varies depending on lead counts, with 0.3 in. (7.62 mm) (JEDEC MS-001) or 0.6 inch (15.24 mm) (JEDEC MS-011)

183-461: A mercury-vapor lamp ). EPROMs are easily recognizable by the transparent fused quartz (or on later models' resin) window on the top of the package, through which the silicon chip is visible, and which permits exposure to ultraviolet light during erasing. It was invented by Dov Frohman in 1971. Development of the EPROM memory cell started with investigation of faulty integrated circuits where

244-456: A quad flat no-leads package (QFN), a quad flat package (QFP), or a dual in-line package (DIP). Advances in lead frame technology have allowed better packing techniques like routable lead frame technology that allow improved thermal and electrical performance. This electronics-related article is a stub . You can help Misplaced Pages by expanding it . EPROM An EPROM (rarely EROM ), or erasable programmable read-only memory ,

305-481: A +25 V pulse in Programming mode. The n-MOS technology evolution introduced single-rail V CC = +5 V power supply and single V PP = +25 V programming voltage without pulse in the third generation. The unneeded V BB and V DD pins were reused for additional address bits allowing larger capacities (2716/2732) in the same 24-pin package, and even larger capacities with larger packages. Later

366-399: A circular window of clear quartz over the chip die to allow the part to be erased by ultraviolet light . Often, the same chips were also sold in less expensive windowless PDIP or CERDIP packages as one-time programmable (OTP) versions. Windowed and windowless packages were also used for microcontrollers, and other devices, containing EPROM memory. Windowed CERDIP-packaged EPROMs were used for

427-420: A complex memory array before the package is finally sealed. Once the package is sealed, information can still be erased by exposing it to X radiation in excess of 5*10 rads , a dose which is easily attained with commercial X-ray generators. In other words, to erase your EPROM, you would first have to X-ray it and then put it in an oven at about 600 degrees Celsius (to anneal semiconductor alterations caused by

488-429: A die paddle, where the die sits in the leadframe, and the leads. The leadframe is made of an alloy the molding compound can adhere to, a thermal expansion coefficient that is as close as possible to that of the die and compound, has good thermal and electrical conductivity, is strong enough and has high formability. The die is glued or soldered to the die pad inside the lead frame, and then bond wires are attached between

549-548: A hollow plastic box with the bottom/back open, filled (around the contained electronic components) with a hard translucent epoxy material from which the leads emerge. Others, such as DIP switches, are composed of two (or more) plastic housing parts snapped, welded, or glued together around a set of contacts and tiny mechanical parts, with the leads emerging through molded-in holes or notches in the plastic. Several DIP variants for ICs exist, mostly distinguished by packaging material: EPROMs were sold in ceramic DIPs manufactured with

610-467: A minimum of ten to twenty years, with many still retaining data after 35 or more years, and can be read an unlimited number of times without affecting the lifetime. The erasing window must be kept covered with an opaque label to prevent accidental erasure by the UV found in sunlight or camera flashes. Old PC BIOS chips were often EPROMs, and the erasing window was often covered with an adhesive label containing

671-551: A non-replaceable 10-year lithium battery. DIP header blocks on to which discrete components could be soldered were used where groups of components needed to be easily removed, for configuration changes, optional features or calibration. The original dual-in-line package was invented by Bryant "Buck" Rogers in 1964 while working for Fairchild Semiconductor. The first devices had 14 pins and looked much like they do today. The rectangular shape allowed integrated circuits to be packaged more densely than previous round packages. The package

SECTION 10

#1732793874591

732-521: A second bend in the leads to flatten them parallel to the bottom plane of the plastic housing. The SOJ (Small Outline J-lead) and other SMT packages with "SOP" (for "Small Outline Package") in their names can be considered further relatives of the DIP, their original ancestor. SOIC packages tend to have half the pitch of DIP, and SOP are half that, a fourth of DIP. (0.1"/2.54 mm, 0.05"/1.27 mm, and 0.025"/0.635 mm, respectively) Pin grid array (PGA) packages may be considered to have evolved from

793-422: A tin-, silver-, or gold-plated lead frame that supports the device die and provides connection pins. Some types of IC are made in ceramic DIP packages, where high temperature or high reliability is required, or where the device has an optical window to the interior of the package. Most DIP packages are secured to a PCB by inserting the pins through holes in the board and soldering them in place. Where replacement of

854-562: A windowed part used for development to a non-windowed part for production. The first generation 1702 devices were fabricated with the p-MOS technology. They were powered with V CC = V BB = +5 V and V DD = V GG = -9 V in Read mode, and with V DD = V GG = -47 V in Programming mode. The second generation 2704/2708 devices switched to n-MOS technology and to three-rail V CC = +5 V, V BB = -5 V, V DD = +12 V power supply with V PP = 12 V and

915-421: A year and a week number), sometimes where it was made, and other proprietary information (perhaps revision numbers, manufacturing plant codes, or stepping ID codes.) The necessity of laying out all of the leads in a basically radial pattern in a single plane from the die perimeter to two rows on the periphery of the package is the main reason that DIP packages with higher lead counts must have wider spacing between

976-527: Is a type of programmable read-only memory (PROM) chip that retains its data when its power supply is switched off. Computer memory that can retrieve stored data after a power supply has been turned off and back on is called non-volatile . It is an array of floating-gate transistors individually programmed by an electronic device that supplies higher voltages than those normally used in digital circuits. Once programmed, an EPROM can be erased by exposing it to strong ultraviolet (UV) light source (such as from

1037-433: Is always even. For 0.3 inch spacing, typical lead counts are 8, 14, 16, and 20; less common are 4, 6, 18, 24, and 28 lead counts. To have an even number of leads some DIPs have unused not connected (NC) leads to the internal chip, or are duplicated, e.g. two ground pins. For 0.6 inch spacing, typical lead counts are 24, 28, 32, and 40; less common are 36, 42, 48, 52, and 64 lead counts. Some microprocessors, such as

1098-416: Is directed onto the die . Photons of the UV light cause ionization within the silicon oxide, which allows the stored charge on the floating gate to dissipate. Since the whole memory array is exposed, all the memory is erased at the same time. The process takes several minutes for UV lamps of convenient sizes; sunlight would erase a chip in weeks, and indoor fluorescent lighting over several years. Generally,

1159-414: Is grown over the channel, then a conductive (silicon or aluminum) gate electrode is deposited, and a further thick layer of oxide is deposited over the gate electrode. The floating-gate electrode has no connections to other parts of the integrated circuit and is completely insulated by the surrounding layers of oxide. A control gate electrode is deposited and further oxide covers it. To retrieve data from

1220-472: Is not as popular as the DIP, but has been used for packaging RAM chips and multiple resistors with a common pin. As compared to DIPs with a typical maximum pin count of 64, SIPs have a typical maximum pin count of 24 with lower package costs. One variant of the single in-line package uses part of the lead frame for a heat sink tab. This multi-leaded power package is useful for such applications as audio power amplifiers, for example. The QIP, sometimes called

1281-468: The BIOS ROM of many early IBM PC clones with an adhesive label covering the window to prevent inadvertent erasure through exposure to ambient light. Molded plastic DIPs are much lower in cost than ceramic packages; one 1979 study showed that a plastic 14 pin DIP cost around US$ 0.063 and a ceramic package cost US$ 0.82. A single in-line package ( SIP or SIL package ) has one row of connecting pins. It

SECTION 20

#1732793874591

1342-566: The Intel 8048 , the Freescale 68HC11 , and the "C" versions of the PIC microcontroller . Like EPROM chips, such microcontrollers came in windowed (expensive) versions that were used for debugging and program development. The same chip came in (somewhat cheaper) opaque OTP packages for production. Leaving the die of such a chip exposed to light can also change behavior in unexpected ways when moving from

1403-466: The Motorola 68000 and Zilog Z180 , used lead counts as high as 64; this is typically the maximum number of leads for a DIP package. As shown in the diagram, leads are numbered consecutively from Pin 1. When the identifying notch in the package is at the top, Pin 1 is the top left corner of the device. Sometimes Pin 1 is identified with an indent or paint dot mark. For example, for a 14-lead DIP, with

1464-447: The 1990s, and still continue to be used today. Because some modern chips are available only in surface-mount package types, a number of companies sell various prototyping adapters to allow those surface-mount devices (SMD) to be used like DIP devices with through-hole breadboards and soldered prototyping boards (such as stripboard and perfboard ). (SMT can pose quite a problem, at least an inconvenience, for prototyping in general; most of

1525-557: The BIOS publisher's name, the BIOS revision, and a copyright notice. Often this label was foil-backed to ensure its opacity to UV. Erasure of the EPROM begins to occur with wavelengths shorter than 400 nm . Exposure time for sunlight of one week or three years for room fluorescent lighting may cause erasure. The recommended erasure procedure is exposure to UV light at 253.7 nm of at least 15 Ws/cm , usually achieved in 20 to 30 minutes with

1586-456: The DIP. PGAs with the same 0.1 inches (2.54 mm) pin centers as most DIPs were popular for microprocessors from the early to mid-1980s through the 1990s. Owners of personal computers containing Intel 80286 through P5 Pentium processors may be most familiar with these PGA packages, which were often inserted into ZIF sockets on motherboards . The similarity is such that a PGA socket may be physically compatible with some DIP devices, though

1647-461: The DIP64 used for the Motorola 68000 CPU) has long leads inside the package between pins and the die, making such a package unsuitable for high speed devices. Some other types of DIP devices are built very differently. Most of these have molded plastic housings and straight leads or leads that extend directly out of the bottom of the package. For some, LED displays particularly, the housing is usually

1708-404: The EPROM, the address represented by the values at the address pins of the EPROM is decoded and used to connect one word (usually an 8-bit byte) of storage to the output buffer amplifiers . Each bit of the word is a 1 or 0, depending on the storage transistor being switched on or off, conducting or non-conducting. The switching state of the field-effect transistor is controlled by the voltage on

1769-463: The EPROMs must be removed from equipment to be erased, since it is not usually practical to build in a UV lamp to erase parts in-circuit. Electrically Erasable Programmable Read-Only Memory (EEPROM) was developed to provide an electrical erase function and has now mostly displaced ultraviolet-erased parts. As the quartz window is expensive to make, OTP (one-time programmable) chips were introduced; here,

1830-482: The IC die inside. Plastic DIP (PDIP) packages are usually sealed by fusing or cementing the plastic halves around the leads, but a high degree of hermeticity is not achieved because the plastic itself is usually somewhat porous to moisture and the process cannot ensure a good microscopic seal between the leads and the plastic at all points around the perimeter. However, contaminants are usually still kept out well enough that

1891-529: The ROMs. Initially, it was thought that the EPROM would be too expensive for mass production use and that it would be confined to development only. It was soon found that small-volume production was economical with EPROM parts, particularly when the advantage of rapid upgrades of firmware was considered. Some microcontrollers , from before the era of EEPROMs and flash memory , use an on-chip EPROM to store their program. Such microcontrollers include some versions of

Dual in-line package - Misplaced Pages Continue

1952-457: The SMT package that most resembles a typical DIP, appears essentially the same, notwithstanding size scale, except that after being bent down the leads are bent upward again by an equal angle to become parallel with the bottom plane of the package.) In ceramic (CERDIP) packages, an epoxy or grout is used to hermetically seal the two halves together, providing an air and moisture tight seal to protect

2013-514: The X-rays). The effects of this process on the reliability of the part would have required extensive testing so they decided on the window instead. EPROMs have a limited but large number of erase cycles; the silicon dioxide around the gates accumulates damage from each cycle, making the chip unreliable after several thousand cycles. EPROM programming is slow compared to other forms of memory. Because higher-density parts have little exposed oxide between

2074-531: The art, this advantage of DIPs is rapidly losing importance as well. Through the 1990s, devices with fewer than 20 leads were manufactured in a DIP format in addition to the newer formats. Since about 2000, newer devices are often unavailable in the DIP format. DIPs can be mounted either by through-hole soldering or in sockets. Sockets allow easy replacement of a device and eliminates the risk of damage from overheating during soldering. Generally sockets were used for high-value or large ICs, which cost much more than

2135-411: The characteristics of SMT that are advantages for mass production are difficulties for prototyping.) For programmable devices like EPROMs and GALs , DIPs remained popular for many years due to their easy handling with external programming circuitry (i.e., the DIP devices could be simply plugged into a socket on the programming device.) However, with In-System Programming (ISP) technology now state of

2196-456: The control gate of the transistor. Presence of a voltage on this gate creates a conductive channel in the transistor, switching it on. In effect, the stored charge on the floating gate allows the threshold voltage of the transistor to be programmed. Storing data in the memory requires selecting a given address and applying a higher voltage to the transistors. This creates an avalanche discharge of electrons, which have enough energy to pass through

2257-424: The converse is rarely true. Lead frame A lead frame (pronounced / l i d / LEED ) is a metal structure inside a chip package that carries signals from the die to the outside, used in DIP, QFP and other packages where connections to the chip are made on its edges. The lead frame consists of a central die pad, where the die is placed, surrounded by leads, metal conductors leading away from

2318-511: The decreased cost of the CMOS technology allowed the same devices to be fabricated using it, adding the letter "C" to the device numbers (27xx(x) are n-MOS and 27Cxx(x) are CMOS). While parts of the same size from different manufacturers are compatible in read mode, different manufacturers added different and sometimes multiple programming modes leading to subtle differences in the programming process. This prompted larger capacity devices to introduce

2379-431: The device can operate reliably for decades with reasonable care in a controlled environment. Inside the package, the lower half has the leads embedded, and at the center of the package is a rectangular space, chamber, or void into which the IC die is cemented. The leads of the package extend diagonally inside the package from their positions of emergence along the periphery to points along a rectangular perimeter surrounding

2440-406: The device. Typical cure cycles for the resins are less than 2 minutes and a single cycle may produce hundreds of devices. The leads emerge from the longer sides of the package along the seam, parallel to the top and bottom planes of the package, and are bent downward approximately 90 degrees (or slightly less, leaving them angled slightly outward from the centerline of the package body). (The SOIC ,

2501-416: The die and the bond pads to connect the die to the leads in a process called wire bonding. In a process called encapsulation, a plastic case is moulded around the lead frame and die, exposing only the leads. The leads are cut off outside the plastic body and any exposed supporting structures are cut away. The external leads are then bent to the desired shape. Amongst others, lead frames are used to manufacture

Dual in-line package - Misplaced Pages Continue

2562-478: The die is mounted in an opaque package so it cannot be erased after programming – this also eliminates the need to test the erase function, further reducing cost. OTP versions of both EPROMs and EPROM-based microcontrollers are manufactured. However, OTP EPROM (whether separate or part of a larger chip) is being increasingly replaced by EEPROM for small sizes, where the cell cost isn't too important, and flash for larger sizes. A programmed EPROM retains its data for

2623-632: The die to the outside world. The end of each lead closest to the die ends in a bond pad. Small bond wires connect the die to each bond pad. Mechanical connections fix all these parts into a rigid structure, which makes the whole lead frame easy to handle automatically. Lead frames are manufactured by removing material from a flat plate of copper, copper-alloy, or iron-nickel alloy like alloy 42. Two processes used for this are etching (suitable for high density of leads), or stamping (suitable for low density of leads). The mechanical bending process can be applied after both techniques. A lead frame has two sections:

2684-450: The die, tapering as they go to become fine contacts at the die. Ultra-fine bond wires (barely visible to the naked human eye) are welded between these die periphery contacts and bond pads on the die itself, connecting one lead to each bond pad, and making the final connection between the microcircuits and the external DIP leads. The bond wires are not usually taut but loop upward slightly to allow slack for thermal expansion and contraction of

2745-485: The early 1960s. In 1963, he noted the movement of charge through oxide onto a gate . While he did not pursue it, this idea would later become the basis for EPROM technology. In 1967, Dawon Kahng and Simon Min Sze at Bell Labs proposed that the floating gate of a MOSFET could be used for the cell of a reprogrammable ROM (read-only memory). Building on this concept, Dov Frohman of Intel invented EPROM in 1971, and

2806-475: The gate connections of transistors had broken. Stored charge on these isolated gates changes their threshold voltage . In 1957, Frosch and Derick were able to manufacture the first silicon dioxide field effect transistors at Bell Labs , the first transistors in which drain and source were adjacent at the surface. Following the invention of the MOSFET at Bell Labs, Frank Wanlass studied MOSFET structures in

2867-416: The informal term "dead bug style" for the method. The body (housing) of a DIP containing an IC chip is usually made from molded plastic or ceramic. The hermetic nature of a ceramic housing is preferred for extremely high reliability devices. However, the vast majority of DIPs are manufactured via a thermoset molding process in which an epoxy mold compound is heated and transferred under pressure to encapsulate

2928-438: The insulating oxide layer and accumulate on the gate electrode. When the high voltage is removed, the electrons are trapped on the electrode. Because of the high insulation value of the silicon oxide surrounding the gate, the stored charge cannot readily leak away and the data can be retained for decades. The programming process is not electrically reversible. To erase the data stored in the array of transistors, ultraviolet light

2989-525: The lamp at a distance of about 2.5 cm. Erasure can also be accomplished with X-rays : Erasure, however, has to be accomplished by non-electrical methods, since the gate electrode is not accessible electrically. Shining ultraviolet light on any part of an unpackaged device causes a photocurrent to flow from the floating gate back to the silicon substrate, thereby discharging the gate to its initial, uncharged condition ( photoelectric effect ). This method of erasure allows complete testing and correction of

3050-448: The layers of interconnects and gate, ultraviolet erasing becomes less practical for very large memories. Even dust inside the package can prevent some cells from being erased. For large volumes of parts (thousands of pieces or more), mask-programmed ROMs are the lowest cost devices to produce. However, these require many weeks lead time to make, since the artwork or design in an IC mask layer or photomask must be altered to store data on

3111-443: The lead rows, and it effectively limits the number of leads which a practical DIP package may have. Even for a very small die with many bond pads (e.g. a chip with 15 inverters, requiring 32 leads), a wider DIP would still be required to accommodate the radiating leads internally. This is one of the reasons that four-sided and multiple rowed packages, such as PGAs , were introduced (around the early 1980s). A large DIP package (such as

SECTION 50

#1732793874591

3172-408: The materials; if a single bond wire breaks or detaches, the entire IC may become useless. The top of the package covers all of this delicate assemblage without crushing the bond wires, protecting it from contamination by foreign materials. Usually, a company logo, alphanumeric codes and sometimes words are printed on top of the package to identify its manufacturer and type, when it was made (usually as

3233-456: The most common. Less common standardized row spacings include 0.4 inch (10.16 mm) (JEDEC MS-010) and 0.9 inch (22.86 mm), as well as a row spacing of 0.3 inch, 0.6 inch or 0.75 inch with a 0.07 inch (1.778 mm) lead pitch. The former Soviet Union and Eastern bloc countries used similar packages, but with a metric pin-to-pin spacing of 2.5 mm rather than 0.1 inches (2.54 mm). The number of leads

3294-401: The notch at the top, the left leads are numbered from 1 to 7 (top to bottom) and the right row of leads are numbered 8 to 14 (bottom to top). Leads are skipped on some DIP devices (e.g. segmented LED displays , relays, or devices that replace leads with a heat sink fin). The remaining leads are numbered as if all positions had leads. In addition to providing for human visual identification of

3355-419: The orientation of the package, the notch allows automated chip-insertion machinery to confirm correct orientation of the chip by mechanical sensing. The SOIC (Small Outline IC), a surface-mount package which is currently very popular, particularly in consumer electronics and personal computers, is essentially a shrunk version of the standard IC PDIP, the fundamental difference which makes it an SMT device being

3416-602: The package. DIP packages have been mostly displaced by surface-mount package types, which avoid the expense of drilling holes in a PCB and which allow higher density of interconnections. DIPs are commonly used for integrated circuits (ICs). Other devices in DIP packages include resistor networks, DIP switches , LED segmented and bar graph displays, and electromechanical relays . DIP connector plugs for ribbon cables are common in computers and other electronic equipment. Dallas Semiconductor manufactured integrated DIP real-time clock (RTC) modules which contained an IC chip and

3477-437: The parts is necessary, such as in test fixtures or where programmable devices must be removed for changes, a DIP socket is used. Some sockets include a zero insertion force (ZIF) mechanism. Variations of the DIP package include those with only a single row of pins, e.g. a resistor array , possibly including a heat sink tab in place of the second row of pins, and types with four rows of pins, two rows, staggered, on each side of

3538-512: The size and weight of systems. DIP chips are still popular for circuit prototyping on a breadboard because of how easily they can be inserted and used there. DIPs were the mainstream of the microelectronics industry in the 1970s and 1980s. Their use has declined in the first decade of the 21st century due to the emerging new surface-mount technology (SMT) packages such as plastic leaded chip carrier (PLCC) and small-outline integrated circuit (SOIC), though DIPs continued in extensive use through

3599-471: The socket. Where devices would be frequently inserted and removed, such as in test equipment or EPROM programmers, a zero insertion force socket would be used. DIPs are also used with breadboards, a temporary mounting arrangement for education, design development or device testing. Some hobbyists, for one-off construction or permanent prototyping, use point-to-point wiring with DIPs, and their appearance when physically inverted as part of this method inspires

3660-468: Was awarded U.S. patent 3,660,819 in 1972. Frohman designed the Intel 1702, a 2048-bit EPROM, which was announced by Intel in 1971. Each storage location of an EPROM consists of a single field-effect transistor . Each field-effect transistor consists of a channel in the semiconductor body of the device. Source and drain contacts are made to regions at the end of the channel. An insulating layer of oxide

3721-463: Was well-suited to automated assembly equipment; a PCB could be populated with scores or hundreds of ICs, then all the components on the circuit board could be soldered at one time on a wave soldering machine and passed on to automated testing machines, with very little human labor required. DIP packages were still large with respect to the integrated circuits within them. By the end of the 20th century, surface-mount packages allowed further reduction in

SECTION 60

#1732793874591
#590409