A multidrop bus ( MDB ) is a computer bus in which all components are connected to the electrical circuit. A process of arbitration determines which device sends information at any point. The other devices listen for the data they are intended to receive.
61-468: The media-independent interface ( MII ) was originally defined as a standard interface to connect a Fast Ethernet (i.e., 100 Mbit/s ) medium access control (MAC) block to a PHY chip . The MII is standardized by IEEE 802.3u and connects different types of PHYs to MACs. Being media independent means that different types of PHY devices for connecting to different media (i.e. twisted pair , fiber optic , etc.) can be used without redesigning or replacing
122-470: A 50 MHz clock where MII requires a 25 MHz clock and data is clocked out two bits at a time vs 4 bits at a time for MII or 1 bit at a time for SNI ( 10 Mbit/s only). Data is sampled on the rising edge only (i.e. it is not double-pumped ). The REF_CLK operates at 50 MHz in both 100 Mbit/s mode and 10 Mbit/s mode. The transmitting side (PHY or MAC) must keep all signals valid for 10 clock cycles in 10 Mbit/s mode. The receiver (PHY or MAC) samples
183-527: A media access controller (MAC), which deals with the higher-level issues of medium availability, and a physical layer interface ( PHY ). The MAC is typically linked to the PHY by a four-bit 25 MHz synchronous parallel interface known as a media-independent interface (MII), or by a two-bit 50 MHz variant called reduced media independent interface (RMII). In rare cases, the MII may be an external connection but
244-432: A star network . Alternatively, it is possible to connect two devices directly using a crossover cable . With today's equipment, crossover cables are generally not needed as most equipment supports auto-negotiation along with auto MDI-X to select and match speed, duplex and pairing. With 100BASE-TX hardware, the raw bits, presented 4 bits wide clocked at 25 MHz at the MII, go through 4B5B binary encoding to generate
305-433: A 100BASE-T cable is limited to 100 metres (328 ft) (the same limit as 10BASE-T and gigabit Ethernet ). All are or were standards under IEEE 802.3 (approved 1995). Almost all 100BASE-T installations are 100BASE-TX. 100BASE-TX is the predominant form of Fast Ethernet, and runs over two pairs of wire inside a Category 5 or above cable. Cable distance between nodes can be up to 100 metres (328 ft). One pair
366-449: A frame when some problem is detected after transmission has already started. The MAC may omit the signal if it has no use for this functionality, in which case the signal should be tied low for the PHY. More recently, raising transmit error outside frame transmission is used to indicate the transmit data lines are being used for special-purpose signalling. Specifically, the data value 0b0001 (held continuously with TX_EN low and TX_ER high)
427-561: A lower-performing cable compared to Category 5 cable used by 100BASE-TX. Maximum distance was limited to 100 meters. One pair was reserved for transmit and one for receive, and the remaining two switched direction. The fact that three pairs were used to transmit in each direction made 100BASE-T4 inherently half-duplex. Using three cable pairs allowed it to reach 100 mbps while running at lower carrier frequencies, which allowed it to run on older cabling that many companies had recently installed for 10BASE-T networks. A very unusual 8B6T code
488-484: A maximum fundamental frequency of 31.25 MHz. The procedure is borrowed from the ANSI X3.263 FDDI specifications, with minor changes. In 100BASE-T1 the data is transmitted over a single copper pair, 3 bits per symbol, each transmitted as code pair using PAM3. It supports full-duplex transmission. The twisted-pair cable is required to support 66 MHz, with a maximum length of 15 m. No specific connector
549-403: A packet, and return to control mode. This concept was intended to solve two problems. The first was that it eliminated the need for collision detection and thereby reduced contention on busy networks. While any particular node may find itself throttled due to heavy traffic, the network as a whole would not end up losing efficiency due to collisions and the resulting rebroadcasts. Under heavy use,
610-455: A piece of 10BASE-T equipment and setting the port to 10BASE-T half duplex if the 10BASE-T equipment cannot perform autonegotiation itself. The standard specifies the use of CSMA/CD for media access control. A full-duplex mode is also specified and in practice, all modern networks use Ethernet switches and operate in full-duplex mode, even as legacy devices that use half duplex still exist. A Fast Ethernet adapter can be logically divided into
671-482: A preamble, start frame delimiter, Ethernet headers, protocol-specific data and a cyclic redundancy check (CRC). The original MII transfers network data using 4-bit nibbles in each direction (4 transmit data bits, 4 receive data bits). The data is clocked at 25 MHz to achieve 100 Mbit/s throughput. The original MII design has been extended to support reduced signals and increased speeds. Current variants include: The Management Data Input/Output (MDIO) serial bus
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#1732791811022732-579: A problem, especially for multiport devices; for example, an eight-port switch using MII would need 8 × 16 + 2 = 130 signals. Reduced media-independent interface (RMII) is a standard which was developed to reduce the number of signals required to connect a PHY to a MAC. Reducing pin count reduces cost and complexity for network hardware especially in the context of microcontrollers with built-in MAC, FPGAs , multiport switches or repeaters, and PC motherboard chipsets. Four things were changed compared to
793-647: A repeater; this is possible, however, with the National DP83848 which supplies the decoded RX_DV as a supplemental signal in RMII mode. TTL logic levels are used for 5 V or 3.3 V logic. Input high threshold is 2.0 V and low is 0.8 V . The specification states that inputs should be 5 V tolerant, however, some popular chips with RMII interfaces are not 5 V tolerant. Newer devices may support 2.5 V and 1.8 V logic. The RMII signals are treated as lumped signals rather than transmission lines . However,
854-426: A series of 0 and 1 symbols clocked at a 125 MHz symbol rate . The 4B5B encoding provides DC equalization and spectrum shaping. Just as in the 100BASE-FX case, the bits are then transferred to the physical medium attachment layer using NRZI encoding. However, 100BASE-TX introduces an additional, medium-dependent sublayer, which employs MLT-3 as a final encoding of the data stream before transmission, resulting in
915-411: A simple wiring adaptor on each end. Cabling is conventionally wired to one of ANSI/TIA-568 's termination standards, T568A or T568B. 100BASE-TX uses pairs 2 and 3 (orange and green). The configuration of 100BASE-TX networks is very similar to 10BASE-T. When used to build a local area network , the devices on the network (computers, printers etc.) are typically connected to a hub or switch , creating
976-723: A single clock signal recovered from the incoming data. The management interface controls the behavior of the PHY. It has the same set of registers as the MII, except that register #15 is the Extended Status register. The reduced gigabit media-independent interface (RGMII) uses half the number of data pins as are used in the GMII interface. This reduction is achieved by running half as many data lines at double speed, time multiplexing signals and by eliminating non-essential carrier-sense and collision-indication signals. Thus RGMII consists only of 14 pins, as opposed to GMII's 24 to 27. Data
1037-667: Is a placeholder for the FX and TX variants. Fast Ethernet is an extension of the 10-megabit Ethernet standard. It runs on twisted pair or optical fiber cable in a star wired bus topology , similar to the IEEE standard 802.3i called 10BASE-T , itself an evolution of 10BASE5 (802.3) and 10BASE2 (802.3a). Fast Ethernet devices are generally backward compatible with existing 10BASE-T systems, enabling plug-and-play upgrades from 10BASE-T. Most switches and other networking devices with ports capable of Fast Ethernet can perform autonegotiation , sensing
1098-603: Is a standard defined in IEEE 802.3 designed for connecting full duplex 10 Gigabit Ethernet (10GbE) ports to each other and to other electronic devices on a printed circuit board (PCB). It is now typically used for on-chip connections. PCB connections are now mostly accomplished with XAUI . XGMII features two 32-bit datapaths (Rx & Tx) and two four-bit control flows (Rxc and Txc), operating at 156.25 MHz DDR (312.5 MT/s ). Fast Ethernet In computer networking , Fast Ethernet physical layers carry traffic at
1159-451: Is a subset of the MII that is used to transfer management information between MAC and PHY. At power up, using autonegotiation , the PHY usually adapts to whatever it is connected to unless settings are altered via the MDIO interface. The standard MII features a small set of registers: Register #15 is reserved; registers #16 through #31 are vendor-specific. The registers are used to configure
1220-439: Is a version of Fast Ethernet over optical fiber standardized in 802.3ah-2004 clause 58. It has a 10 km reach over a pair of single-mode fibers. 100BASE-BX10 is a version of Fast Ethernet over optical fiber standardized in 802.3ah-2004 clause 58. It uses an optical multiplexer to split TX and RX signals into different wavelengths on the same fiber. It has a 10 km reach over a single strand of single-mode fiber. 100BASE-EX
1281-705: Is a version of Fast Ethernet over optical fiber standardized in TIA/EIA-785-1-2002. It is a lower-cost, shorter-distance alternative to 100BASE-FX. Because of the shorter wavelength used (850 nm) and the shorter distance supported, 100BASE-SX uses less expensive optical components (LEDs instead of lasers). Because it uses the same wavelength as 10BASE-FL , the 10 Mbit/s version of Ethernet over optical fiber, 100BASE-SX can be backward-compatible with 10BASE-FL. Cost and compatibility makes 100BASE-SX an attractive option for those upgrading from 10BASE-FL and those who do not require long distances. 100BASE-LX10
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#17327918110221342-424: Is ambiguous between vendors. 100BASE-ZX is a non-standard but multi-vendor term to refer to Fast Ethernet transmission using 1,550 nm wavelength to achieve distances of at least 70 km over single-mode fiber. Some vendors specify distances up to 160 km over single-mode fiber, sometimes called 100BASE-EZX. Ranges beyond 80 km are highly dependent upon the path loss of the fiber in use, specifically
1403-502: Is carried by duplicating data words 100/10 times each, so the clock is always at 625 MHz. The high serial gigabit media-independent interface (HSGMII) is functionally similar to the SGMII but supports link speeds of up to 2.5 Gbit/s . The quad serial gigabit media-independent interface (QSGMII) is a method of combining four SGMII lines into a 5 Gbit/s interface. QSGMII, like SGMII, uses low-voltage differential signaling (LVDS) for
1464-415: Is clocked on rising and falling edges for 1000 Mbit/s , and on rising edges only for 10/100 Mbit/s . The RX_CTL signal carries RXDV (data valid) on the rising edge, and (RXDV xor RXER) on the falling edge. The TX_CTL signal likewise carries TXEN on rising edge and (TXEN xor TXER) on the falling edge. This is the case for both 1000 Mbit/s and 10/100 Mbit/s . The transmit clock signal is always provided by
1525-476: Is defined. The standard is intended for automotive applications or when Fast Ethernet is to be integrated into another application. It was developed as Open Alliance BroadR-Reach (OABR) before IEEE standardization. In 100BASE-T2 , standardized in IEEE 802.3y, the data is transmitted over two copper pairs, but these pairs are only required to be Category 3 rather than the Category 5 required by 100BASE-TX. Data
1586-541: Is less than the theoretical maximum, due to the necessary header and trailer (addressing and error-detection bits) on every Ethernet frame , and the required interpacket gap between transmissions. 100BASE-T is any of several Fast Ethernet standards for twisted pair cables , including: 100BASE-TX (100 Mbit/s over two-pair Cat5 or better cable), 100BASE-T4 (100 Mbit/s over four-pair Cat3 or better cable, defunct), 100BASE-T2 (100 Mbit/s over two-pair Cat3 or better cable, also defunct). The segment length for
1647-431: Is not backward compatible with 10BASE-F and is not forward compatible with 1000BASE-X . 100BASE-FX is a version of Fast Ethernet over optical fiber . The 100BASE-FX physical medium dependent (PMD) sublayer is defined by FDDI 's PMD, so 100BASE-FX is not compatible with 10BASE-FL , the 10 Mbit/s version over optical fiber. 100BASE-FX is still used for existing installation of multimode fiber where more speed
1708-431: Is not required, like industrial automation plants. 100BASE-LFX is a non-standard term to refer to Fast Ethernet transmission. It is very similar to 100BASE-FX but achieves longer distances up to 4–5 km over a pair of multi-mode fibers through the use of Fabry–Pérot laser transmitter running on 1310 nm wavelength. The signal attenuation per km at 1300 nm is about half the loss of 850 nm. 100BASE-SX
1769-414: Is transmitted and received on both pairs simultaneously thus allowing full-duplex operation. Transmission uses 4 bits per symbol. The 4-bit symbol is expanded into two 3-bit symbols through a non-trivial scrambling procedure based on a linear-feedback shift register . This is needed to flatten the bandwidth and emission spectrum of the signal, as well as to match transmission line properties. The mapping of
1830-418: Is used for each direction, providing full-duplex operation at 100 Mbit/s in each direction. Like 10BASE-T , the active pairs in a standard connection are terminated on pins 1, 2, 3 and 6. Since a typical Category 5 cable contains four pairs and the performance requirements of 100BASE-TX do not exceed the capabilities of even the worst-performing pair, one typical cable can carry two 100BASE-TX links with
1891-401: Is used to request an EEE -capable PHY to enter low power mode. The first seven receiver signals are entirely analogous to the transmitter signals, except RX_ER is not optional and used to indicate the received signal could not be decoded to valid data. The receive clock is recovered from the incoming signal during frame reception. When no clock can be recovered (i.e. when the medium is silent),
Media-independent interface - Misplaced Pages Continue
1952-500: Is usually a connection between ICs in a network adapter or even two sections within a single IC. The specs are written based on the assumption that the interface between MAC and PHY will be an MII but they do not require it. Fast Ethernet or Ethernet hubs may use the MII to connect to multiple PHYs for their different interfaces. The MII fixes the theoretical maximum data bit rate for all versions of Fast Ethernet to 100 Mbit/s. The information rate actually observed on real networks
2013-418: Is very similar to 100BASE-LX10 but achieves longer distances up to 40 km over a pair of single-mode fibers due to higher quality optics than a LX10, running on 1310 nm wavelength lasers. 100BASE-EX is not a formal standard but industry-accepted term. It is sometimes referred to as 100BASE-LH (long haul), and is easily confused with 100BASE-LX10 or 100BASE-ZX because the use of -LX(10), -LH, -EX, and -ZX
2074-527: The 3com 3C250-T4 Superstack II HUB 100, IBM 8225 Fast Ethernet Stackable Hub and Intel LinkBuilder FMS 100 T4. The same applies to network interface controllers . Bridging 100BASE-T4 with 100BASE-TX required additional network equipment. Proposed and marketed by Hewlett-Packard , 100BaseVG was an alternative design using category 3 cabling and a token concept instead of CSMA/CD. It was slated for standardization as IEEE 802.12 but it quickly vanished when switched 100BASE-TX became popular. The IEEE standard
2135-578: The medium access control (MAC) device and the physical layer ( PHY ). The interface operates at speeds up to 1000 Mbit/s , implemented using a data interface clocked at 125 MHz with separate eight-bit data paths for receive and transmit, and is backwards compatible with the MII specification and can operate on fall-back speeds of 10 or 100 Mbit/s . The GMII interface was first defined for 1000BASE-X in IEEE 802.3z-1998 as clause 35, and subsequently incorporated into IEEE 802.3-2000 onwards. There are two transmitter clocks. The clock used depends on whether
2196-503: The COL signal, allowing the combination of COL high with CRS low (which a PHY will never produce) to serve as indication of an absent/disconnected PHY. MDC and MDIO constitute a synchronous serial data interface similar to I²C . As with I²C, the interface is a multidrop bus so MDC and MDIO can be shared among multiple PHYs. The interface requires 18 signals, out of which only two (MDIO and MDC) can be shared among multiple PHYs. This presents
2257-406: The IEEE version of the related MII standard specifies 68 Ω trace impedance. National recommends running 50 Ω traces with 33 Ω series termination resistors for either MII or RMII mode to reduce reflections. National also suggests that traces be kept under 0.15 m long and matched within 0.05 m on length to minimize skew. The gigabit media-independent interface (GMII) is an interface between
2318-518: The MAC hardware. Thus any MAC may be used with any PHY, independent of the network signal transmission medium. The MII can be used to connect a MAC to an external PHY using a pluggable connector, or directly to a PHY chip on the same PCB . On older PCs the CNR connector Type B carried MII signals. Network data on the interface is framed using the IEEE Ethernet standard. As such it consists of
2379-623: The MAC on the TXC line. The receive clock signal is always provided by the PHY on the RXC line. Source-synchronous clocking is used: the clock signal that is output (by either the PHY or the MAC) is synchronous with the data signals. This requires the PCB to be designed to add a 1.5–2 ns delay to the clock signal to meet the setup and hold times on the sink. RGMII v2.0 specifies an optional internal delay, obviating
2440-478: The MAC synchronously on the rising edge of TX_CLK. This arrangement allows the MAC to operate without having to be aware of the link speed. The transmit enable signal is held high during frame transmission and low when the transmitter is idle. Transmit error may be raised for one or more clock periods during frame transmission to request the PHY to deliberately corrupt the frame in some visible way that precludes it from being received as valid. This may be used to abort
2501-480: The MII standard to achieve this. These changes mean that RMII uses about half the number of signals compared to MII. MDC and MDIO can be shared among multiple PHYs. The receiver signals are referenced to the REF_CLK, same as the transmitter signals. This interface requires 9 signals, versus MII's 18. Of those 9, on multiport devices, MDIO, MDC, and REF_CLK may be shared leaving 6 or 7 pins per port. RMII requires
Media-independent interface - Misplaced Pages Continue
2562-568: The PHY is operating at gigabit or 10/100 Mbit/s speeds. For gigabit operation, the GTXCLK is supplied to the PHY and the TXD, TXEN, TXER signals are synchronized to this. For 10 or 100 Mbit/s operation, the TXCLK is supplied by the PHY and is used for synchronizing those signals. This operates at either 25 MHz for 100 Mbit/s or 2.5 MHz for 10 Mbit/s connections. In contrast, the receiver uses
2623-451: The PHY must present a free-running clock as a substitute. The receive data valid signal (RX_DV) is not required to go high immediately when the frame starts, but must do so in time to ensure the "start of frame delimiter" byte is included in the received data. Some of the preamble nibbles may be lost. Similar to transmit, raising RX_ER outside a frame is used for special signalling. For receive, two data values are defined: 0b0001 to indicate
2684-515: The RMII Consortium specification states that its MDIO/MDC interface is identical to that specified for MII in IEEE 802.3u. Current revisions of IEEE 802.3 specify a standard MDIO/MDC mechanism for negotiating and configuring the link's speed and duplex mode, but it is possible that older PHY devices might have been designed against obsolete versions of the standard, and may therefore use proprietary methods to set speed and duplex. The lack of
2745-640: The RX_ER signal which is not connected on some MACs (such as multiport switches) is dealt with by data replacement on some PHYs to invalidate the CRC . The missing COL signal is derived from AND-ing together the TX_EN and the decoded CRS signal from the CRS_DV line in half duplex mode. This means a slight modification of the definition of CRS: On MII, CRS is asserted for both Rx and Tx frames; on RMII only for Rx frames. This has
2806-527: The TX and RX data, and a single LVDS clock signal. QSGMII uses significantly fewer signal lines than four separate SGMII connections. QSGMII predates NBASE-T and is used to connect multi-port PHYs to MACs, for example in network routers. The PSGMII (penta serial gigabit media-independent interface) uses the same signal lines as QSGMII, but operates at 6.25 Gbit/s , which supports five 1 gigabit/s ports through one MII. 10 gigabit media-independent interface (XGMII)
2867-545: The attenuation figure in dB per km, the number and quality of connectors/patch panels and splices located between transceivers. Multidrop bus Multidrop buses have the advantage of simplicity and extensibility, but their differing electrical characteristics make them relatively unsuitable for high frequency or high bandwidth applications. Since 2000, multidrop standards such as PCI and Parallel ATA are increasingly being replaced by point-to-point systems such as PCI Express and SATA . Modern SDRAM chips exemplify
2928-403: The consequence that on RMII the two error conditions no carrier and lost carrier cannot be detected, and it is difficult or impossible to support shared media such as 10BASE2 or 10BASE5 . Since the RMII standard neglected to stipulate that TX_EN should only be sampled on alternate clock cycles, it is not symmetric with CRS_DV and two RMII PHY devices cannot be connected back to back to form
2989-438: The device and to query the current operating mode. The MII Status Word is the most useful datum, since it may be used to detect whether an Ethernet NIC is connected to a network. It contains a bit field with the following information: The transmit clock is a free-running clock generated by the PHY based on the link speed (25 MHz for 100 Mbit/s , 2.5 MHz for 10 Mbit/s ). The remaining transmit signals are driven by
3050-484: The input signals only every ten cycles in 10 Mbit/s mode. There is no signal which defines whether the interface is in full or half duplex mode, but both the MAC and the PHY need to agree. This must instead be communicated over the serial MDIO/MDC interface. There is also no signal which defines whether the interface is in 10 or 100 Mbit/s mode, so this must also be handled using the MDIO/MDC interface. Version 1.2 of
3111-468: The link partner is in EEE low power mode, and 0b1110 for a false carrier indication. The CRS and COL signals are asynchronous to the receive clock, and are only meaningful in half-duplex mode. Carrier sense is high when transmitting, receiving, or the medium is otherwise sensed as being in use. If a collision is detected, COL also goes high while the collision persists. In addition, the MAC may weakly pull-up
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#17327918110223172-459: The media type designation refers to the transmission speed of 100 Mbit/s, while the BASE refers to baseband signaling. The letter following the dash ( T or F ) refers to the physical medium that carries the signal (twisted pair or fiber, respectively), while the last character ( X , 4 , etc.) refers to the line code method used. Fast Ethernet is sometimes referred to as 100BASE-X , where X
3233-750: The need for the PCB designer to add delay; this is known as RGMII-ID. RGMII version 1.3 uses 2.5V CMOS, whereas RGMII version 2 uses 1.5V HSTL . The serial gigabit media-independent interface (SGMII) is a variant of MII used for Gigabit Ethernet but can also carry 10/100 Mbit/s Ethernet. It uses differential pairs at 625 MHz clock frequency DDR for TX and RX data and TX and RX clocks. It differs from GMII by its low-power and low pin-count 8b/10b -coded SerDes . Transmit and receive path each use one differential pair for data and another differential pair for clock. The TX/RX clocks must be generated on device output but are optional on device input ( clock recovery may be used alternatively). 10/100 Mbit/s Ethernet
3294-496: The nominal rate of 100 Mbit/s. The prior Ethernet speed was 10 Mbit/s. Of the Fast Ethernet physical layers, 100BASE-TX is by far the most common. Fast Ethernet was introduced in 1995 as the IEEE 802.3u standard and remained the fastest version of Ethernet for three years before the introduction of Gigabit Ethernet . The acronym GE/FE is sometimes used for devices supporting both standards. The 100 in
3355-451: The original bits to the symbol codes is not constant in time and has a fairly large period (appearing as a pseudo-random sequence). The final mapping from symbols to PAM-5 line modulation levels obeys the table on the right. 100BASE-T2 was not widely adopted but the technology developed for it is used in 1000BASE-T. 100BASE-T4 was an early implementation of Fast Ethernet. It required four twisted copper pairs of voice grade twisted pair ,
3416-429: The other two pairs are used for flow control . In the second mode, transmission, all four are used to transfer data in a single direction. The hubs implemented a token passing scheme to choose which of the attached nodes were allowed to communicate at any given time, based on signals sent to it from the nodes using control mode. When one node was selected to become active, it would switch to transfer mode, send or receive
3477-651: The problem of electrical impedance discontinuity . Fully Buffered DIMM is an alternative approach to connecting multiple DRAM modules to a memory controller. MDB/ICP (formerly known as MDB) is a multidrop bus computer networking protocol used within the vending machine industry, currently published by the American National Automatic Merchandising Association . The ccTalk multidrop bus protocol uses an 8 bit TTL-level asynchronous serial protocol . It uses address randomization to allow multiple similar devices on
3538-402: The total throughput was increased compared to the other standards. The other was that the hubs could examine the payload types and schedule the nodes based on their bandwidth requirements. For instance, a node sending a video signal may not require much bandwidth but will require it to be predictable in terms of when it is delivered. A VG hub could schedule access on that node to ensure it received
3599-603: The transmission timeslots it needed while opening up the network at all other times to the other nodes. This style of access was known as demand priority . Fiber variants use fiber-optic cable with the listed interface types. Interfaces may be fixed or modular, often as small form-factor pluggable (SFP). Fast Ethernet speed is not available on all SFP ports, but supported by some devices. An SFP port for Gigabit Ethernet should not be assumed to be backwards compatible with Fast Ethernet. To have interoperability there are some criteria that have to be met: 100BASE-X Ethernet
3660-474: Was later withdrawn. VG was similar to T4 in that it used more cable pairs combined with a lower carrier frequency to allow it to reach 100 mbps on voice-grade cables. It differed in the way those cables were assigned. Whereas T4 would use the two extra pairs in different directions depending on the direction of data exchange, VG instead used two transmission modes. In one, control, two pairs are used for transmission and reception as in classic Ethernet, while
3721-498: Was used to convert 8 data bits into 6 base-3 digits (the signal shaping is possible as there are nearly three times as many 6-digit base-3 numbers as there are 8-digit base-2 numbers). The two resulting 3-digit base-3 symbols were sent in parallel over three pairs using 3-level pulse-amplitude modulation (PAM-3). 100BASE-T4 was not widely adopted but some of the technology developed for it is used in 1000BASE-T . Very few hubs were released with 100BASE-T4 support. Some examples include
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