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83-554: SATA ( Serial AT Attachment ) is a computer bus interface that connects host bus adapters to mass storage devices such as hard disk drives , optical drives , and solid-state drives . Serial ATA succeeded the earlier Parallel ATA (PATA) standard to become the predominant interface for storage devices. Serial ATA industry compatibility specifications originate from the Serial ATA International Organization (SATA-IO) which are then released by

166-418: A processor or DMA -enabled device needs to read or write to a memory location, it specifies that memory location on the address bus (the value to be read or written is sent on the data bus). The width of the address bus determines the amount of memory a system can address. For example, a system with a 32-bit address bus can address 2 (4,294,967,296) memory locations. If each memory location holds one byte,

249-730: A bidirectional data bus, re-using the same wires for input and output at different times. Some processors use a dedicated wire for each bit of the address bus, data bus, and the control bus. For example, the 64-pin STEbus is composed of 8 physical wires dedicated to the 8-bit data bus, 20 physical wires dedicated to the 20-bit address bus, 21 physical wires dedicated to the control bus, and 15 physical wires dedicated to various power buses. Bus multiplexing requires fewer wires, which reduces costs in many early microprocessors and DRAM chips. One common multiplexing scheme, address multiplexing , has already been mentioned. Another multiplexing scheme re-uses

332-726: A card plugged into the bus, which is why computers have so many slots on the bus. But through the 1980s and 1990s, new systems like SCSI and IDE were introduced to serve this need, leaving most slots in modern systems empty. Today there are likely to be about five different buses in the typical machine, supporting various devices. "Third generation" buses have been emerging into the market since about 2001, including HyperTransport and InfiniBand . They also tend to be very flexible in terms of their physical connections, allowing them to be used both as internal buses, as well as connecting different machines together. This can lead to complex problems when trying to service different requests, so much of

415-563: A different power connector than the four-pin Molex connector used on Parallel ATA (PATA) devices (and earlier small storage devices, going back to ST-506 hard disk drives and even to floppy disk drives that predated the IBM PC). It is a wafer-type connector, like the SATA data connector, but much wider (fifteen pins versus seven) to avoid confusion between the two. Some early SATA drives included

498-427: A mode provided by a proprietary driver and command set that allowed access to SATA's advanced features before AHCI became popular. Modern versions of Microsoft Windows , Mac OS X , FreeBSD , Linux with version 2.6.19 onward, as well as Solaris and OpenSolaris , include support for AHCI, but earlier operating systems such as Windows XP do not. Even in those instances, a proprietary driver may have been created for

581-510: A multiplexed address scheme, the address is sent in two equal parts on alternate bus cycles. This halves the number of address bus signals required to connect to the memory. For example, a 32-bit address bus can be implemented by using 16 lines and sending the first half of the memory address, immediately followed by the second half memory address. Typically two additional pins in the control bus – row-address strobe (RAS) and column-address strobe (CAS) – are used to tell

664-403: A multitasking environment. During the initial period after SATA 1.5 Gbit/s finalization, adapter and drive manufacturers used a "bridge chip" to convert existing PATA designs for use with the SATA interface. Bridged drives have a SATA connector, may include either or both kinds of power connectors, and, in general, perform identically to their native-SATA equivalents. As of April 2010,

747-561: A native transfer rate of 3.0 Gbit/s that, when accounted for the 8b/10b encoding scheme, equals to the maximum uncoded transfer rate of 2.4 Gbit/s (300 MB/s). The theoretical burst throughput of the SATA revision 2.0, which is also known as the SATA 3 Gbit/s, doubles the throughput of SATA revision 1.0. All SATA data cables meeting the SATA spec are rated for 3.0 Gbit/s and handle modern mechanical drives without any loss of sustained and burst data transfer performance. However, high-performance flash-based drives can exceed

830-470: A number of techniques to reduce the undesirable effects of such unintentional coupling. One such technique used in SATA links is differential signaling . This is an enhancement over PATA, which uses single-ended signaling . The use of fully shielded, dual coax conductors, with multiple ground connections, for each differential pair improves isolation between the channels and reduces the chances of lost data in difficult electrical environments. SATA specifies

913-515: A passive backplane connected directly or through buffer amplifiers to the pins of the CPU . Memory and other devices would be added to the bus using the same address and data pins as the CPU itself used, connected in parallel. Communication was controlled by the CPU, which read and wrote data from the devices as if they are blocks of memory, using the same instructions, all timed by a central clock controlling

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996-506: A serial bus inherently has no timing skew or crosstalk. USB , FireWire , and Serial ATA are examples of this. Multidrop connections do not work well for fast serial buses, so most modern serial buses use daisy-chain or hub designs. The transition from parallel to serial buses was allowed by Moore's law which allowed for the incorporation of SerDes in integrated circuits which are used in computers. Network connections such as Ethernet are not generally regarded as buses, although

1079-449: A single source LRI/LRU or, as with ARINC 629, MIL-STD-1553B, and STANAG 3910, be duplex , allow all the connected LRI/LRUs to act, at different times ( half duplex ), as transmitters and receivers of data. The frequency or the speed of a bus is measured in Hz such as MHz and determines how many clock cycles there are per second; there can be one or more data transfers per clock cycle. If there

1162-563: A specific chipset, such as Intel 's. SATA revisions are typically designated with a dash followed by Roman numerals , e.g. "SATA-III", to avoid confusion with the speed, which is always displayed in Arabic numerals , e.g. "SATA 6 Gbit / s ". The speeds given are the raw interface rate in Gbit/s including line code overhead, and the usable data rate in MB /s without overhead. Revision 1.0a

1245-614: A subgroup of T10 responsible for Serial Attached SCSI (SAS). The remainder of this article strives to use the SATA-IO terminology and specifications. Before SATA's introduction in 2000, PATA was simply known as ATA. The "AT Attachment" (ATA) name originated after the 1984 release of the IBM Personal Computer AT , more commonly known as the IBM AT. The IBM AT's controller interface became a de facto industry interface for

1328-501: A system memory structure for computer hardware vendors to exchange data between host system memory and attached storage devices . AHCI gives software developers and hardware designers a standard method for detecting, configuring, and programming SATA/AHCI adapters. AHCI is separate from the SATA 3 Gbit/s standard, although it exposes SATA's advanced capabilities (such as hot swapping and native command queuing ) such that host systems can utilize them. For modern solid state drives ,

1411-433: A unified system bus . In this case, a single mechanical and electrical system can be used to connect together many of the system components, or in some cases, all of them. Later computer programs began to share memory common to several CPUs. Access to this memory bus had to be prioritized, as well. The simple way to prioritize interrupts or bus access was with a daisy chain . In this case signals will naturally flow through

1494-406: Is a communication system that transfers data between components inside a computer , or between computers. This expression covers all related hardware components (wire, optical fiber , etc.) and software , including communication protocols . In most traditional computer architectures , the CPU and main memory tend to be tightly coupled, with the internal bus connecting the two being known as

1577-412: Is a single transfer per clock cycle it is known as Single Data Rate (SDR), and if there are two transfers per clock cycle it is known as Double Data Rate (DDR) although the use of signalling other than SDR is uncommon outside of RAM. An example of this is PCIe which uses SDR. Within each data transfer there can be multiple bits of data. This is described as the width of a bus which is the number of bits

1660-510: Is a software backward-compatibility mechanism intended to allow the SATA controller to run in legacy operating systems which are not SATA-aware or where a driver does not exist to make the operating system SATA-aware. When a SATA controller is configured to operate in IDE Mode, the number of storage devices per controller is usually limited to four (two IDE channels, master device and slave device with up to two devices per channel), compared to

1743-561: Is an open standard interconnect for high-speed CPU -to-device and CPU-to-memory, designed to accelerate next-generation data center performance. Many field buses are serial data buses (not to be confused with the parallel "data bus" section of a system bus or expansion card ), several of which use the RS-485 electrical characteristics and then specify their own protocol and connector: Other serial buses include: Advanced Host Controller Interface The specification describes

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1826-732: Is an open host controller interface published and used by Intel, which has become a de facto standard. It allows the use of advanced features of SATA such as hotplug and native command queuing (NCQ). If AHCI is not enabled by the motherboard and chipset, SATA controllers typically operate in "IDE emulation" mode, which does not allow access to device features not supported by the ATA (also called IDE) standard. Windows device drivers that are labeled as SATA are often running in IDE emulation mode unless they explicitly state that they are AHCI mode, in RAID mode, or

1909-475: Is provided by the bus‍—‌is not the case in many avionic systems , where data connections such as ARINC 429 , ARINC 629 , MIL-STD-1553B (STANAG 3838), and EFABus ( STANAG 3910 ) are commonly referred to as “data buses” or, sometimes, "databuses". Such avionic data buses are usually characterized by having several equipments or Line Replaceable Items/Units (LRI/LRUs) connected to a common, shared media . They may, as with ARINC 429, be simplex , i.e. have

1992-507: Is removed. Unlike PATA, both SATA and eSATA support hot plugging by design. However, this feature requires proper support at the host, device (drive), and operating-system levels. In general, SATA devices fulfill the device-side hot-plugging requirements, and most SATA host adapters support this function. For eSATA, hot plugging is supported in AHCI mode only. IDE mode does not support hot plugging. Advanced Host Controller Interface (AHCI)

2075-404: Is required to mate a SATA connector. A smaller mini-SATA or mSATA connector is used by smaller devices such as 1.8-inch SATA drives, some DVD and Blu-ray drives, and mini SSDs. A special eSATA connector is specified for external devices, and an optionally implemented provision for clips to hold internal connectors firmly in place. SATA drives may be plugged into SAS controllers and communicate on

2158-501: Is that the system drive typically fails to boot, with an ensuing error message, if the SATA controller (in BIOS) is inadvertently switched to AHCI mode after OS installation. In Microsoft Windows the symptom is a boot loop which begins with a Blue Screen error, if not rectified. Technically speaking, this is an implementation bug with AHCI that can be avoided, but it has not been fixed yet. As an interim resolution, Intel recommends changing

2241-436: Is the case with PCI . While the term " peripheral bus " is sometimes used to refer to all other buses apart from the system bus, the "expansion bus" has also been used to describe a third category of buses separate from the peripheral bus, which includes bus systems like PCI. Early computer buses were parallel electrical wires with multiple hardware connections, but the term is now used for any physical arrangement that provides

2324-509: The BIOS will allow the user to boot into Windows, and thereby the required registry change can be performed. Consequently, the user then has the option of continuing to use the system in Combined mode or switching to AHCI mode. Inter alia with Windows 10 and 8, this can be fixed by forcing the correct drivers to reload during Safe Mode . In Windows 8, Windows 8.1 and Windows Server 2012 ,

2407-473: The IBM PC , although similar physical architecture can be employed, instructions to access peripherals ( in and out ) and memory ( mov and others) have not been made uniform at all, and still generate distinct CPU signals, that could be used to implement a separate I/O bus. These simple bus systems had a serious drawback when used for general-purpose computers. All the equipment on the bus had to talk at

2490-495: The INCITS Technical Committee T13, AT Attachment (INCITS T13). SATA was announced in 2000 in order to provide several advantages over the earlier PATA interface such as reduced cable size and cost (seven conductors instead of 40 or 80), native hot swapping , faster data transfer through higher signaling rates, and more efficient transfer through an (optional) I/O queuing protocol. Revision 1.0 of

2573-889: The S-100 bus were used, but to reduce latency , modern memory buses are designed to connect directly to DRAM chips, and thus are designed by chip standards bodies such as JEDEC . Examples are the various generations of SDRAM , and serial point-to-point buses like SLDRAM and RDRAM . An exception is the Fully Buffered DIMM which, despite being carefully designed to minimize the effect, has been criticized for its higher latency. Buses can be parallel buses , which carry data words in parallel on multiple wires, or serial buses , which carry data in bit-serial form. The addition of extra power and control connections, differential drivers , and data connections in each direction usually means that most serial buses have more conductors than

SATA - Misplaced Pages Continue

2656-488: The SATA ports in modern computers support multiple peripherals, allowing multiple hard drives to be connected without an expansion card . In systems that have a similar architecture to multicomputers , but which communicate by buses instead of networks, the system bus is known as a front-side bus . In such systems, the expansion bus may not share any architecture with their host CPUs, instead supporting many different CPUs, as

2739-446: The system bus . In systems that include a cache , CPUs use high-performance system buses that operate at speeds greater than memory to communicate with memory. The internal bus (also known as the internal data bus, memory bus or system bus ) connects internal components of a computer to the mother board. Local buses connect the CPU and memory to the expansion bus , which in turn connects the computer to peripherals. Bus systems such as

2822-405: The 3.3 V power supply. However, most drives do not require the 3.3 V power line. Just like SATA data connectors, SATA power connectors may be straight, upward-angled, or downward-angled. The power connector is reduced to six pins so it supplies only +5 V (red wire), and not +12 V or +3.3 V. Pin 1 of the slimline power connector, denoting device presence, is shorter than

2905-469: The DRAM whether the address bus is currently sending the first half of the memory address or the second half. Accessing an individual byte frequently requires reading or writing the full bus width (a word ) at once. In these instances the least significant bits of the address bus may not even be implemented - it is instead the responsibility of the controlling device to isolate the individual byte required from

2988-472: The IEEE "Superbus" study group, the open microprocessor initiative (OMI), the open microsystems initiative (OMI), the "Gang of Nine" that developed EISA , etc. Early computer buses were bundles of wire that attached computer memory and peripherals. Anecdotally termed the " digit trunk " in the early Australian CSIRAC computer, they were named after electrical power buses, or busbars . Almost always, there

3071-558: The PATA specification; however, cables up to 90 centimeters (35 in) are readily available. Thus, SATA connectors and cables are easier to fit in closed spaces and reduce obstructions to air cooling . Some cables even include a locking feature, whereby a small (usually metal) spring holds the plug in the socket. SATA connectors may be straight, upward-angled, downward-angled, leftward-angled, or rightward-angled. Angled connectors allow lower-profile connections. Downward-angled connectors lead

3154-677: The SATA 3 Gbit/s transfer rate; this is addressed with the SATA 6 Gbit/s interoperability standard. Announced in August 2005, SATA revision 2.5 consolidated the specification to a single document. Announced in February 2007, SATA revision 2.6 introduced the following features: Serial ATA International Organization (SATA-IO) presented the draft specification of SATA 6 Gbit/s physical layer in July 2008, and ratified its physical layer specification on August 18, 2008. The full 3.0 standard

3237-805: The SATA power connector. Some legacy power supplies that provide 3.3 V power on Pin 3 would force drives with Power Disable feature to get stuck in a hard reset condition preventing them from spinning up. The problem can usually be eliminated by using a simple “ Molex to SATA” power adaptor to supply power to these drives. Released in June 2018, SATA revision 3.4 introduced the following features that enable monitoring of device conditions and execution of housekeeping tasks, both with minimal impact on performance: Released in July 2020, SATA revision 3.5 introduces features that enable increased performance benefits and promote greater integration of SATA devices and products with other industry I/O standards: SATA revision 3.5a

3320-549: The address bus pins as the data bus pins, an approach used by conventional PCI and the 8086 . The various "serial buses" can be seen as the ultimate limit of multiplexing, sending each of the address bits and each of the data bits, one at a time, through a single pin (or a single differential pair). Over time, several groups of people worked on various computer bus standards, including the IEEE Bus Architecture Standards Committee (BASC),

3403-473: The addressable memory space is 4 GB. Early processors used a wire for each bit of the address width. For example, a 16-bit address bus had 16 physical wires making up the bus. As the buses became wider and lengthier, this approach became expensive in terms of the number of chip pins and board traces. Beginning with the Mostek 4096 DRAM , address multiplexing implemented with multiplexers became common. In

SATA - Misplaced Pages Continue

3486-411: The associated eSATA are one example of a system that would formerly be described as internal, while certain automotive applications use the primarily external IEEE 1394 in a fashion more similar to a system bus. Other examples, like InfiniBand and I²C were designed from the start to be used both internally and externally. An address bus is a bus that is used to specify a physical address . When

3569-489: The bits themselves, and allows for an increase in data transfer speed without increasing the frequency of the bus. The effective or real data transfer speed/rate may be lower due to the use of encoding that also allows for error correction such as 128/130b (b for bit) encoding. The data transfer speed is also known as the bandwidth. The simplest system bus has completely separate input data lines, output data lines, and address lines. To reduce cost, most microcomputers have

3652-600: The box. Some operating systems, notably Windows Vista , Windows 7 , Windows 8 , Windows 8.1 and Windows 10 , do not configure themselves to load the AHCI driver upon boot if the SATA controller was not in AHCI mode at the time the operating system was installed. Although this is an easily rectifiable condition, it remains an ongoing issue with the AHCI standard. The most prevalent symptom for an operating system (or systems) that are installed in IDE mode (in some BIOS firmware implementations otherwise called 'Combined IDE mode'),

3735-493: The bus can transfer per clock cycle and can be synonymous with the number of physical electrical conductors the bus has if each conductor transfers one bit at a time. The data rate in bits per second can be obtained by multiplying the number of bits per clock cycle times the frequency times the number of transfers per clock cycle. Alternatively a bus such as PCIe can use modulation or encoding such as PAM4 which groups 2 bits into symbols which are then transferred instead of

3818-409: The bus had to talk at the same speed. While the CPU was now isolated and could increase speed, CPUs and memory continued to increase in speed much faster than the buses they talked to. The result was that the bus speeds were now much slower than what a modern system needed, and the machines were left starved for data. A particularly common example of this problem was that video cards quickly outran even

3901-519: The bus in physical or logical order, eliminating the need for complex scheduling. Digital Equipment Corporation (DEC) further reduced cost for mass-produced minicomputers , and mapped peripherals into the memory bus, so that the input and output devices appeared to be memory locations. This was implemented in the Unibus of the PDP-11 around 1969. Early microcomputer bus systems were essentially

3984-626: The bus supplied power, but often use a separate power source. This distinction is exemplified by a telephone system with a connected modem , where the RJ11 connection and associated modulated signalling scheme is not considered a bus, and is analogous to an Ethernet connection. A phone line connection scheme is not considered to be a bus with respect to signals, but the Central Office uses buses with cross-bar switches for connections between phones. However, this distinction‍—‌that power

4067-452: The cable immediately away from the drive, on the circuit-board side. Upward-angled connectors lead the cable across the drive towards its top. One of the problems associated with the transmission of data at high speed over electrical connections is described as noise , which is due to electrical coupling between data circuits and other circuits. As a result, the data circuits can both affect other circuits and be affected by them. Designers use

4150-431: The cards to be much more complex. These buses also often addressed speed issues by being "bigger" in terms of the size of the data path, moving from 8-bit parallel buses in the first generation, to 16 or 32-bit in the second, as well as adding software setup (now standardised as Plug-n-play ) to supplant or replace the jumpers. However, these newer systems shared one quality with their earlier cousins, in that everyone on

4233-527: The complete word transmitted. This is the case, for instance, with the VESA Local Bus which lacks the two least significant bits, limiting this bus to aligned 32-bit transfers. Historically, there were also some examples of computers which were only able to address words -- word machines . The memory bus is the bus which connects the main memory to the memory controller in computer systems . Originally, general-purpose buses like VMEbus and

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4316-491: The computer into two "worlds", the CPU and memory on one side, and the various devices on the other. A bus controller accepted data from the CPU side to be moved to the peripherals side, thus shifting the communications protocol burden from the CPU itself. This allowed the CPU and memory side to evolve separately from the device bus, or just "bus". Devices on the bus could talk to each other with no CPU intervention. This led to much better "real world" performance, but also required

4399-421: The controller driver has changed from msahci to storahci , and the procedures to upgrade to the AHCI controller is similar to that of Windows 7. On Windows 8, 8.1 and Windows Server 2012, changing from IDE mode to AHCI mode without first updating the registry will make the boot drive inaccessible (i.e. resulting in a recurring boot loop, which begins with a Blue Screen error). In Windows 10, after changing

4482-557: The controller to AHCI mode, if the OS is allowed to reboot a couple of times after the start of the boot loop, which starts with an INACCESSIBLE_BOOT_DEVICE BSOD, Windows presents recovery options. Out of the Advanced options, if Startup Repair option is selected, Windows attempts to fix the issue and the PC begins to function normally. A similar problem can occur on Linux systems if the AHCI driver

4565-557: The data directly in memory, a concept known as direct memory access . Low-performance bus systems have also been developed, such as the Universal Serial Bus (USB). Given technological changes, the classical terms "system", "expansion" and "peripheral" no longer have the same connotations. Other common categorization systems are based on the bus's primary role, connecting devices internally or externally. However, many common modern bus systems can be used for both. SATA and

4648-415: The desktop PC market was 99% in 2008. PATA has mostly been replaced by SATA for any use; with PATA in declining use in industrial and embedded applications that use CompactFlash (CF) storage, which was designed around the legacy PATA standard. A 2008 standard, CFast , to replace CompactFlash is based on SATA. The Serial ATA spec requires SATA devices be capable of hot plugging ; that is, devices that meet

4731-489: The difference is largely conceptual rather than practical. An attribute generally used to characterize a bus is that power is provided by the bus for the connected hardware. This emphasizes the busbar origins of bus architecture as supplying switched or distributed power. This excludes, as buses, schemes such as serial RS-232 , parallel Centronics , IEEE 1284 interfaces and Ethernet, since these devices also needed separate power supplies. Universal Serial Bus devices may use

4814-403: The drive controller to AHCI or RAID before installing an operating system. (It may also be necessary to load chipset-specific AHCI or RAID drivers at installation time, for example from a USB flash drive). On Windows Vista and Windows 7, this can be fixed by configuring the msahci device driver to start at boot time (rather than on-demand). Setting non-AHCI mode (i.e. IDE or Combined mode) in

4897-496: The fastest 10,000 rpm SATA hard disk drives could transfer data at maximum (not average) rates of up to 157 MB/s, which is beyond the capabilities of the older PATA/133 specification and also exceeds the capabilities of SATA 1.5 Gbit/s. SATA revision 2.0 was released in April 2004, introducing Native Command Queuing (NCQ). It is backward compatible with SATA 1.5 Gbit/s. Second-generation SATA interfaces run with

4980-464: The following changes: In general, the enhancements are aimed at improving quality of service for video streaming and high-priority interrupts. In addition, the standard continues to support distances up to one meter. The newer speeds may require higher power consumption for supporting chips, though improved process technologies and power management techniques may mitigate this. The later specification can use existing SATA cables and connectors, though it

5063-618: The four-pin Molex power connector together with the new fifteen-pin connector, but most SATA drives now have only the latter. The new SATA power connector contains many more pins for several reasons: Passive adapters are available that convert a four-pin Molex connector to a SATA power connector, providing the 5 V and 12 V lines available on the Molex connector, but not 3.3 V. There are also four-pin Molex-to-SATA power adapters that include electronics to additionally provide

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5146-471: The inclusion of hard disks. "AT" was IBM's abbreviation for "Advanced Technology"; thus, many companies and organizations indicate SATA is an abbreviation of "Serial Advanced Technology Attachment". However, the ATA specifications simply use the name "AT Attachment", to avoid possible trademark issues with IBM. SATA host adapters and devices communicate via a high-speed serial cable over two pairs of conductors. In contrast, parallel ATA (the redesignation for

5229-635: The input and output of a given bus. IBM introduced these on the IBM 709 in 1958, and they became a common feature of their platforms. Other high-performance vendors like Control Data Corporation implemented similar designs. Generally, the channel controllers would do their best to run all of the bus operations internally, moving data when the CPU was known to be busy elsewhere if possible, and only using interrupts when necessary. This greatly reduced CPU load, and provided better overall system performance. To provide modularity, memory and I/O buses can be combined into

5312-528: The interface has been superseded by NVMe . The current version of the specification is 1.3.1. Many SATA controllers offer selectable modes of operation: legacy Parallel ATA emulation (more commonly called IDE Mode), standard AHCI mode (also known as Native Mode), or vendor-specific RAID (which generally enables AHCI in order to take advantage of its capabilities). Intel recommends choosing RAID mode on their motherboards (which also enables AHCI) rather than AHCI/SATA mode for maximum flexibility. Legacy mode

5395-632: The legacy ATA specifications) uses a 16-bit wide data bus with many additional support and control signals, all operating at a much lower frequency. To ensure backward compatibility with legacy ATA software and applications, SATA uses the same basic ATA and ATAPI command sets as legacy ATA devices. The world's first SATA hard disk drive is the Seagate Barracuda SATA V, which was released in Jan 2003. SATA has replaced parallel ATA in consumer desktop and laptop computers ; SATA's market share in

5478-779: The maximum of 32 devices/ports when configured in AHCI mode. But the chipset SATA interfaces may emulate more than one "IDE controller" when configured in IDE Mode. AHCI is supported out of the box on Windows Vista and later, Linux -based operating systems (since version 2.6.19 of the kernel ), OpenBSD (since version 4.1), NetBSD (since version 4.0), FreeBSD (since version 8.0), macOS , GNU Mach , ArcaOS , eComStation (since version 2.1), and Solaris 10 (since version 8/07). DragonFlyBSD based its AHCI implementation on OpenBSD's and added extended features such as port multiplier support. Older versions of operating systems require hardware-specific drivers in order to support AHCI. Windows XP and older do not provide AHCI support out of

5561-446: The minimum of one used in 1-Wire and UNI/O . As data rates increase, the problems of timing skew , power consumption, electromagnetic interference and crosstalk across parallel buses become more and more difficult to circumvent. One partial solution to this problem has been to double pump the bus. Often, a serial bus can be operated at higher overall data rates than a parallel bus, despite having fewer electrical connections, because

5644-401: The newer bus systems like PCI , and computers began to include AGP just to drive the video card. By 2004 AGP was outgrown again by high-end video cards and other peripherals and has been replaced by the new PCI Express bus. An increasing number of external devices started employing their own bus systems as well. When disk drives were first introduced, they would be added to the machine with

5727-456: The others to allow hot-swapping. Note: The data connector used is the same as the non-slimline version. Low-cost adapters exist to convert from standard SATA to slimline SATA. SATA 2.6 is the first revision that defined the slimline power connector targeted for smaller form-factors drives, such as laptop optical drives. Computer bus In computer architecture , a bus (historically also called data highway or databus )

5810-484: The program attempted to perform those other tasks, it might take too long for the program to check again, resulting in loss of data. Engineers thus arranged for the peripherals to interrupt the CPU. The interrupts had to be prioritized, because the CPU can only execute code for one peripheral at a time, and some devices are more time-critical than others. High-end systems introduced the idea of channel controllers , which were essentially small computers dedicated to handling

5893-529: The same logical function as a parallel electrical busbar . Modern computer buses can use both parallel and bit serial connections, and can be wired in either a multidrop (electrical parallel) or daisy chain topology, or connected by switched hubs. Many modern CPUs also feature a second set of pins similar to those for communicating with memory—but able to operate with different speeds and protocols—to ensure that peripherals do not slow overall system performance. CPUs can also feature smart controllers to place

5976-790: The same physical cable as native SAS disks, but SATA controllers cannot handle SAS disks. Female SATA ports (on motherboards for example) are for use with SATA data cables that have locks or clips to prevent accidental unplugging. Some SATA cables have right- or left-angled connectors to ease connection to circuit boards. The SATA standard defines a data cable with seven conductors (three grounds and four active data lines in two pairs) and 8 mm wide wafer connectors on each end. SATA cables can have lengths up to 1 meter (3.3 ft), and connect one motherboard socket to one hard drive. PATA ribbon cables , in comparison, connect one motherboard socket to one or two hard drives, carry either 40 or 80 wires, and are limited to 45 centimeters (18 in) in length by

6059-420: The same speed, as it shared a single clock. Increasing the speed of the CPU becomes harder, because the speed of all the devices must increase as well. When it is not practical or economical to have all devices as fast as the CPU, the CPU must either enter a wait state , or work at a slower clock frequency temporarily, to talk to other devices in the computer. While acceptable in embedded systems , this problem

6142-451: The specification are capable of insertion or removal of a device into or from a backplane connector (combined signal and power) that has power on. After insertion, the device initializes and then operates normally. Depending upon the operating system, the host may also initialize, resulting in a hot swap . The powered host and device do not need to be in an idle state for safe insertion and removal, although unwritten data may be lost when power

6225-553: The specification was released in January 2003. Serial ATA industry compatibility specifications originate from the Serial ATA International Organization (SATA-IO). The SATA-IO group collaboratively creates, reviews, ratifies, and publishes the interoperability specifications, the test cases and plugfests . As with many other industry compatibility standards, the SATA content ownership is transferred to other industry bodies: primarily INCITS T13 and an INCITS T10 subcommittee ( SCSI ),

6308-522: The speed of the CPU. Still, devices interrupted the CPU by signaling on separate CPU pins. For instance, a disk drive controller would signal the CPU that new data was ready to be read, at which point the CPU would move the data by reading the "memory location" that corresponded to the disk drive. Almost all early microcomputers were built in this fashion, starting with the S-100 bus in the Altair 8800 computer system. In some instances, most notably in

6391-522: The work on these systems concerns software design, as opposed to the hardware itself. In general, these third generation buses tend to look more like a network than the original concept of a bus, with a higher protocol overhead needed than early systems, while also allowing multiple devices to use the bus at once. Buses such as Wishbone have been developed by the open source hardware movement in an attempt to further remove legal and patent constraints from computer design. The Compute Express Link (CXL)

6474-441: Was not tolerated for long in general-purpose, user-expandable computers. Such bus systems are also difficult to configure when constructed from common off-the-shelf equipment. Typically each added expansion card requires many jumpers in order to set memory addresses, I/O addresses, interrupt priorities, and interrupt numbers. "Second generation" bus systems like NuBus addressed some of these problems. They typically separated

6557-402: Was one bus for memory, and one or more separate buses for peripherals. These were accessed by separate instructions, with completely different timings and protocols. One of the first complications was the use of interrupts . Early computer programs performed I/O by waiting in a loop for the peripheral to become ready. This was a waste of time for programs that had other tasks to do. Also, if

6640-463: Was released in March 2021. Connectors and cables present the most visible differences between SATA and parallel ATA drives. Unlike PATA, the same connectors are used on 3.5-inch SATA hard disks (for desktop and server computers) and 2.5-inch disks (for portable or small computers). Standard SATA connectors for both data and power have a conductor pitch of 1.27 mm (0.050 inches). Low insertion force

6723-497: Was released on January 7, 2003. First-generation SATA interfaces, now known as SATA 1.5 Gbit/s, communicate at a rate of 1.5 Gbit/s, and do not support Native Command Queuing (NCQ). Taking 8b/10b encoding overhead into account, they have an actual uncoded transfer rate of 1.2 Gbit/s (150 MB/s). The theoretical burst throughput of SATA 1.5 Gbit/s is similar to that of PATA /133, but newer SATA devices offer enhancements such as NCQ, which improve performance in

6806-423: Was released on May 27, 2009. Third-generation SATA interfaces run with a native transfer rate of 6.0 Gbit/s; taking 8b/10b encoding into account, the maximum uncoded transfer rate is 4.8 Gbit/s (600 MB/s). The theoretical burst throughput of SATA 6.0 Gbit/s is double that of SATA revision 2.0. It is backward compatible with earlier SATA implementations. The SATA 3.0 specification contains

6889-509: Was reported in 2008 that some OEMs were expected to upgrade host connectors for the higher speeds. Released in July 2011, SATA revision 3.1 introduced or changed the following features: Released in August 2013, SATA revision 3.2 introduced the following features: Released in February 2016, SATA revision 3.3 introduced the following features: The new Power Disable feature (similar to the SAS Power Disable feature) uses Pin 3 of

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