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29-495: The LVDC was capable of executing 12190 instructions per second . For comparison, as of 2022, researchers at the University of California created a chip capable of running at 1.78 trillion instructions per second, 146 million times faster. Its master clock ran at 2.048 MHz, but operations were performed bit-serially, with 4 cycles required to process each bit, 14 bits per instruction phase, and 3 phases per instruction, for

58-467: A 3 x 5 matrix of cells separated by walls through which coolant was circulated to remove the 138 watts of power dissipated by the computer. Slots in the cell walls held "pages" of electronics. The decision to cool the LVDC by circulating coolant through the walls of the computer was unique at the time and allowed the LVDC and LVDA (part-cooled using this technique) to be placed in one cold plate location due to

87-410: A 4-bit opcode field (least-significant bits) and a 9-bit operand address field (most-significant bits). This left it with sixteen possible opcode values when there were eighteen different instructions: consequently, three of the instructions used the same opcode value, and used two bits of the address value to determine which instruction was executed. Memory was broken into 256-word "sectors". 8 bits of

116-412: A Saturn IB these interrupts were: For a Saturn V these interrupts were: The LVDC was approximately 30 inches (760 mm) wide, 12.5 inches (320 mm) high, and 10.5 inches (270 mm) deep and weighed 72.5 pounds (32.9 kg). The chassis was made of magnesium-lithium alloy LA 141, chosen for its high stiffness, low weight, and good vibration damping characteristics. The chassis was divided into

145-415: A basic instruction cycle time of 82 μs (168 clock cycles) for a simple add. A few instructions (such as multiply or divide) took several multiples of the basic instruction cycle to execute. Memory was in the form of 13-bit syllables , each with a 14th parity bit. Instructions were one syllable in size, while data words were two syllables (26 bits). Main memory was random access magnetic core , in

174-453: A majority vote on the results, with the most popular result being passed on to the next stage in all pipelines. This meant that, for each of the seven stages, one module in any one of the three pipelines could fail, and the LVDC would still produce the correct results. The result was an estimated reliability of 99.6% over 250 hours of operation, which was far more than the few hours required for an Apollo mission. With four memory modules, giving

203-410: A metal lid. Several of these SLT modules (20 in the image on the right) were then mounted on a small multi-layer printed circuit board to make an SLT card. Each SLT card had a socket on one edge that plugged into pins on the computer's backplane (the exact reverse of how most other companies' modules were mounted). IBM considered monolithic integrated circuit technology too immature at the time. SLT

232-552: A modern C / C++ compiler. For the most early 8-bit and 16-bit microprocessors , performance was measured in thousand instructions per second (1000 kIPS = 1 MIPS). zMIPS refers to the MIPS measure used internally by IBM to rate its mainframe servers ( zSeries , IBM System z9 , and IBM System z10 ). Weighted million operations per second (WMOPS) is a similar measurement, used for audio codecs. Solid Logic Technology Solid Logic Technology ( SLT )

261-443: A total capacity of 16,384 words, the computer weighed 72.5 lb (32.9 kg), was 29.5 by 12.5 by 10.5 inches (750 mm × 320 mm × 270 mm) in size and consumed 137W. The LVDC communicated digitally with a Launch Vehicle Data adapter (LVDA). The LVDA converted analog-to-digital and digital-to-analog with a Flight Control Computer (FCC). The FCC was an analog computer. LVDC instruction words were split into

290-890: Is a measure of a computer 's processor speed. For complex instruction set computers (CISCs), different instructions take different amounts of time, so the value measured depends on the instruction mix; even for comparing processors in the same family the IPS measurement can be problematic. Many reported IPS values have represented "peak" execution rates on artificial instruction sequences with few branches and no cache contention , whereas realistic workloads typically lead to significantly lower IPS values. Memory hierarchy also greatly affects processor performance, an issue barely considered in IPS calculations. Because of these problems, synthetic benchmarks such as Dhrystone are now generally used to estimate computer performance in commonly used applications, and raw IPS has fallen into disuse. The term

319-404: Is commonly used in association with a metric prefix (k, M, G, T, P, or E) to form kilo instructions per second ( kIPS ), mega instructions per second ( MIPS ), giga instructions per second ( GIPS ) and so on. Formerly TIPS was used occasionally for "thousand IPS". IPS can be calculated using this equation: However, the instructions/cycle measurement depends on the instruction sequence,

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348-460: Is rarely used today, as most current microprocessors can execute at least a million instructions per second. Gibson divided computer instructions into 12 classes, based on the IBM 704 architecture, adding a 13th class to account for indexing time. Weights were primarily based on analysis of seven scientific programs run on the 704, with a small contribution from some IBM 650 programs. The overall score

377-567: The Apollo Guidance Computer software, the software which ran on the LVDC seems to have vanished. While the hardware would be fairly simple to emulate, the only remaining copies of the software are probably in the core rope memory of the Instrument Unit LVDCs of the remaining Saturn V rockets on display at NASA sites. The LVDC could also respond to a number of interrupts triggered by external events. For

406-516: The System/360 in 1970. SLT used silicon planar glass-encapsulated transistors and diodes. SLT uses dual diode chips and individual transistor chips each approximately 0.025 inches (0.64 mm) square. The chips are mounted on a 0.5 inches (13 mm) square substrate with silk-screened resistors and printed connections. The whole is encapsulated to form a 0.5 inches (13 mm) square module. Up to 36 modules are mounted on each card, though

435-465: The address specified a word within a sector, and the 9th bit selected between the software-selectable "current sector" or a global sector called "residual memory". The eighteen possible LVDC instructions were: In flight the LVDC ran a major computation loop every 2 seconds for vehicle guidance, and a minor loop 25 times a second for attitude control. The minor loop is triggered by a dedicated interrupt every 40 ms and takes 18 ms to run. Unlike

464-625: The data and external factors. Before standard benchmarks were available, average speed rating of computers was based on calculations for a mix of instructions with the results given in kilo instructions per second (kIPS). The most famous was the Gibson Mix , produced by Jack Clark Gibson of IBM for scientific applications in 1959. Other ratings, such as the ADP mix which does not include floating point operations, were produced for commercial applications. The thousand instructions per second (kIPS) unit

493-574: The first volume uses of hybrid thick-film technology . SLT replaced the earlier Standard Modular System , although some later SMS cards held SLT modules. SLT had several updates during its life, the last being the Monolithic System Technology ( MST ) which replaced the single transistors of SLT with small-scale integrated circuits that held four or five transistors. MST was used in the System/370 , which began to replace

522-404: The form of 4,096-word memory modules. Up to 8 modules provided a maximum of 32,768 words of memory. Ultrasonic delay lines provided temporary storage. For reliability, the LVDC used triple-redundant logic and a voting system. The computer included three identical logic systems. Each logic system was split into a seven-stage pipeline . At each stage in the pipeline, a voting system would take

551-399: The frame. A page consisted of two 2.5–3-inch (64–76 mm) boards back to back and a magnesium-lithium frame to conduct heat to the chassis on low power pages and magnesium-aluminun-zinc on higher power pages. The 12-layer boards contained signal, power, and ground layers and connections between layers were made by plated-through holes. The plated-through holes were deliberately placed below

580-548: The mid-1980s. For this reason, MIPS has become not a measure of instruction execution speed, but task performance speed compared to a reference. In the late 1970s, minicomputer performance was compared using VAX MIPS , where computers were measured on a task and their performance rated against the VAX-11/780 that was marketed as a 1 MIPS machine. (The measure was also known as the VAX Unit of Performance or VUP .) This

609-470: The processor may be capable of executing multiple independent instructions simultaneously. MIPS can be useful when comparing performance between processors made with similar architecture (e.g. Microchip branded microcontrollers), but they are difficult to compare between differing CPU architectures . This led to the term "Meaningless Indicator of Processor Speed," or less commonly, "Meaningless Indices of Performance," being popular amongst technical people by

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638-491: The programming language used. The Whetstone Report has a table showing MWIPS speeds of PCs via early interpreters and compilers up to modern languages. The first PC compiler was for BASIC (1982) when a 4.8 MHz 8088/87 CPU obtained 0.01 MWIPS. Results on a 2.4 GHz Intel Core 2 Duo (1 CPU 2007) vary from 9.7 MWIPS using BASIC Interpreter, 59 MWIPS via BASIC Compiler, 347 MWIPS using 1987 Fortran, 1,534 MWIPS through HTML/Java to 2,403 MWIPS using

667-553: The three dimensional packaging. The cold plates used to cool most equipment in the Instrument Unit were inefficient from a space view although versatile for the variety of equipment used. The alloy LA 141 had been used by IBM on the Gemini keyboard, read out units, and computer in small quantities and the larger frame of the LVDC was produced from the largest billets of LA 141 cast at the time and subsequently CNC machined into

696-423: The top side. The complete module was called a unit logic device. The unit logic device (ULD) was a smaller version of IBM's Solid Logic Technology (SLT) module, but with clip connections. Copper balls were used for contacts between the chips and the conductive patterns. The hierarchy of the electronic structure is shown in the following table. Instructions per second Instructions per second ( IPS )

725-532: The unit logic devices (ULD) to help conduct heat from the devices to the metal frames and thus the coolant walls. Up to 35 alumina squares of 0.3 by 0.3 by 0.07 inches (7.6 mm × 7.6 mm × 1.8 mm) could be reflow soldered to a board. These alumina squares had conductors silk screened to the top side and resistors silk-screened to the bottom side. Semiconductor chips of 0.025 by 0.025 inches (0.64 mm × 0.64 mm), each containing either one transistor or two diodes, were reflow soldered to

754-518: Was IBM 's method for hybrid packaging of electronic circuitry introduced in 1964 with the IBM System/360 series of computers. It was also used in the 1130, announced in 1965. IBM chose to design custom hybrid circuits using discrete, flip chip -mounted, glass -encapsulated transistors and diodes , with silk-screened resistors on a ceramic substrate, forming an SLT module. The circuits were either encapsulated in plastic or covered with

783-551: Was a revolutionary technology for 1964, with much higher circuit densities and improved reliability over earlier packaging techniques such as the Standard Modular System . It helped propel the IBM System/360 mainframe family to overwhelming success during the 1960s. SLT research produced ball chip assembly, wafer bumping , trimmed thick-film resistors, printed discrete functions, chip capacitors and one of

812-569: Was chosen because the 11/780 was roughly equivalent in performance to an IBM System/370 model 158–3, which was commonly accepted in the computing industry as running at 1 MIPS. Many minicomputer performance claims were based on the Fortran version of the Whetstone benchmark , giving Millions of Whetstone Instructions Per Second (MWIPS). The VAX 11/780 with FPA (1977) runs at 1.02 MWIPS. Effective MIPS speeds are highly dependent on

841-532: Was then the weighted sum of the average execution speed for instructions in each class. The speed of a given CPU depends on many factors, such as the type of instructions being executed, the execution order and the presence of branch instructions (problematic in CPU pipelines). CPU instruction rates are different from clock frequencies, usually reported in Hz , as each instruction may require several clock cycles to complete or

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