The PDP–11 is a series of 16-bit minicomputers sold by Digital Equipment Corporation (DEC) from 1970 into the late 1990s, one of a set of products in the Programmed Data Processor (PDP) series. In total, around 600,000 PDP-11s of all models were sold, making it one of DEC's most successful product lines. The PDP-11 is considered by some experts to be the most popular minicomputer.
125-451: The PDP–11 included a number of innovative features in its instruction set and additional general-purpose registers that made it easier to program than earlier models in the PDP series. Further, the innovative Unibus system allowed external devices to be more easily interfaced to the system using direct memory access , opening the system to a wide variety of peripherals . The PDP–11 replaced
250-538: A VT100 terminal enclosure. The /150 was housed in a table-top unit which included two 8-inch floppy drives, three asynchronous serial ports, one printer port, one modem port and one synchronous serial port and required an external terminal. All three employed the same chipset as used on the LSI-11/03 and LSI-11/2 in four "microm"s. There is an option which combines two of the microms into one dual carrier, freeing one socket for an EIS/FIS chip. The /150 in combination with
375-471: A VT105 terminal was also sold as MiniMINC , a budget version of the MINC-11 . The DEC Professional series are desktop PCs intended to compete with IBM's earlier 8088 and 80286 based personal computers. The models are equipped with 5 1 ⁄ 4 inch floppy disk drives and hard disks, except the 325 which has no hard disk. The original operating system was P/OS, which was essentially RSX-11 M+ with
500-462: A "low" and between 2.4 V and V CC for a "high", providing at least 0.4 V of noise immunity . Standardization of the TTL levels is so ubiquitous that complex circuit boards often contain TTL chips made by many different manufacturers selected for availability and cost, compatibility being assured. Two circuit board units off the same assembly line on different successive days or weeks might have
625-408: A 16-bit design as well. The team decided that the best approach to a new architecture would be to minimize the memory bandwidth needed to execute the instructions. Larry McGowan coded a series of assembly language programs using the instruction sets of various existing platforms and examined how much memory would be exchanged to execute them. Harold McFarland joined the effort and had already written
750-505: A basic ALU operation, such as "add", with the access of one or more operands in memory (using addressing modes such as direct, indirect, indexed, etc.). Certain architectures may allow two or three operands (including the result) directly in memory or may be able to perform functions such as automatic pointer increment, etc. Software-implemented instruction sets may have even more complex and powerful instructions. Reduced instruction-set computers , RISC , were first widely implemented during
875-401: A cache line or virtual memory page boundary, for instance), and are therefore somewhat easier to optimize for speed. In early 1960s computers, main memory was expensive and very limited, even on mainframes. Minimizing the size of a program to make sure it would fit in the limited memory was often central. Thus the size of the instructions needed to perform a particular task, the code density ,
1000-415: A conditional branch instruction will transfer control if the condition is true, so that execution proceeds to a different part of the program, and not transfer control if the condition is false, so that execution continues sequentially. Some instruction sets also have conditional moves, so that the move will be executed, and the data stored in the target location, if the condition is true, and not executed, and
1125-432: A different mix of brands of chips in the same positions on the board; repair is possible with chips manufactured years later than original components. Within usefully broad limits, logic gates can be treated as ideal Boolean devices without concern for electrical limitations. The 0.4 V noise margins are adequate because of the low output impedance of the driver stage, that is, a large amount of noise power superimposed on
1250-406: A few hundred transistors each. Functions within a single package generally range from a few logic gates to a microprocessor bit-slice . TTL also became important because its low cost made digital techniques economically practical for tasks previously done by analog methods. The Kenbak-1 , ancestor of the first personal computers , used TTL for its CPU instead of a microprocessor chip, which
1375-517: A fifth chip can be added to extend the instruction set). It uses a bus which is a close variant of the Unibus called the LSI Bus or Q-Bus ; it differs from the Unibus primarily in that addresses and data are multiplexed onto a shared set of wires rather than having separate sets of wires. It also differs slightly in how it addresses I/O devices and it eventually allowed a 22-bit physical address (whereas
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#17327809583031500-420: A form of surface-mount package, with leads suitable for welding or soldering to printed circuit boards. Today , many TTL-compatible devices are available in surface-mount packages, which are available in a wider array of types than through-hole packages. TTL is particularly well suited to bipolar integrated circuits because additional inputs to a gate merely required additional emitters on a shared base region of
1625-572: A given instruction may specify: More complex operations are built up by combining these simple instructions, which are executed sequentially, or as otherwise directed by control flow instructions. Examples of operations common to many instruction sets include: Processors may include "complex" instructions in their instruction set. A single "complex" instruction does something that may take many instructions on other computers. Such instructions are typified by instructions that take multiple steps, control multiple functional units, or otherwise appear on
1750-601: A larger scale than the bulk of simple instructions implemented by the given processor. Some examples of "complex" instructions include: Complex instructions are more common in CISC instruction sets than in RISC instruction sets, but RISC instruction sets may include them as well. RISC instruction sets generally do not include ALU operations with memory operands, or instructions to move large blocks of memory, but most RISC instruction sets include SIMD or vector instructions that perform
1875-554: A menu system on top. As the design was intended to avoid software exchange with existing PDP–11 models, the poor market response was unsurprising. The RT-11 operating system was eventually ported to the PRO series. A port of the RSTS/E operating system to the PRO series was also done internal to DEC, but it was not released. The PRO-325 and -350 units are based on the DCF-11 ("Fonz") chipset,
2000-419: A period of rapidly growing memory subsystems. They sacrifice code density to simplify implementation circuitry, and try to increase performance via higher clock frequencies and more registers. A single RISC instruction typically performs only a single operation, such as an "add" of registers or a "load" from a memory location into a register. A RISC instruction set normally has a fixed instruction length , whereas
2125-617: A register by one (byte instructions) or two (word instructions). Use of relative addressing lets a machine-language program be position-independent . Early models of the PDP–11 had no dedicated bus for input/output , but only a system bus called the Unibus , as input and output devices were mapped to memory addresses. An input/output device determined the memory addresses to which it would respond, and specified its own interrupt vector and interrupt priority . This flexible framework provided by
2250-543: A single architecture for a series of five processors spanning a wide range of cost and performance. None of the five engineering design teams could count on being able to bring about adjustments in architectural specifications as a way of easing difficulties in achieving cost and performance objectives. Some virtual machines that support bytecode as their ISA such as Smalltalk , the Java virtual machine , and Microsoft 's Common Language Runtime , implement this by translating
2375-545: A single instruction. Some exotic instruction sets do not have an opcode field, such as transport triggered architectures (TTA), only operand(s). Most stack machines have " 0-operand " instruction sets in which arithmetic and logical operations lack any operand specifier fields; only instructions that push operands onto the evaluation stack or that pop operands from the stack into variables have operand specifiers. The instruction set carries out most ALU actions with postfix ( reverse Polish notation ) operations that work only on
2500-420: A standard TTL input while not allowing the voltage to rise to more than 0.4 volts. The output stage of the most common TTL gates is specified to function correctly when driving up to 10 standard input stages (a fanout of 10). TTL inputs are sometimes simply left floating to provide a logical "1", though this usage is not recommended. Standard TTL circuits operate with a 5- volt power supply. A TTL input signal
2625-408: A standard and compatible application binary interface (ABI) for a particular ISA, machine code will run on future implementations of that ISA and operating system. However, if an ISA supports running multiple operating systems, it does not guarantee that machine code for one operating system will run on another operating system, unless the first operating system supports running machine code built for
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#17327809583032750-463: A typical CISC instruction set has instructions of widely varying length. However, as RISC computers normally require more and often longer instructions to implement a given task, they inherently make less optimal use of bus bandwidth and cache memories. Certain embedded RISC ISAs like Thumb and AVR32 typically exhibit very high density owing to a technique called code compression. This technique packs two 16-bit instructions into one 32-bit word, which
2875-421: A very complex instruction set that the team rejected, but a second one was simpler and would ultimately form the basis for the PDP–11. When they first presented the new architecture, the managers were dismayed. It lacked single instruction-word immediate data and short addresses, both of which were considered essential to improving memory performance. McGowan and McFarland were eventually able to convince them that
3000-697: A wide range of logic gates , flip-flops , counters, and other circuits. Variations of the original TTL circuit design offered higher speed or lower power dissipation to allow design optimization. TTL devices were originally made in ceramic and plastic dual in-line package (s) and in flat-pack form. Some TTL chips are now also made in surface-mount technology packages. TTL became the foundation of computers and other digital electronics. Even after Very-Large-Scale Integration (VLSI) CMOS integrated circuit microprocessors made multiple-chip processors obsolete, TTL devices still found extensive use as glue logic interfacing between more densely integrated components. TTL
3125-540: A writable control store use it to allow the instruction set to be changed (for example, the Rekursiv processor and the Imsys Cjip ). CPUs designed for reconfigurable computing may use field-programmable gate arrays (FPGAs). An ISA can also be emulated in software by an interpreter . Naturally, due to the interpretation overhead, this is slower than directly running programs on the emulated hardware, unless
3250-415: Is 15 bytes (120 bits). Within an instruction set, different instructions may have different lengths. In some architectures, notably most reduced instruction set computers (RISC), instructions are a fixed length , typically corresponding with that architecture's word size . In other architectures, instructions have variable length , typically integral multiples of a byte or a halfword . Some, such as
3375-501: Is a common debug interface for embedded devices. Handheld devices such as graphing calculators and NMEA 0183 -compliant GPS receivers and fishfinders also commonly use UART with TTL. TTL serial is only a de facto standard: there are no strict electrical guidelines. Driver–receiver modules interface between TTL and longer-range serial standards: one example is the MAX232 , which converts from and to RS-232 . Differential TTL
3500-444: Is a complex issue. There were two stages in history for the microprocessor. The first was the CISC (Complex Instruction Set Computer), which had many different instructions. In the 1970s, however, places like IBM did research and found that many instructions in the set could be eliminated. The result was the RISC (Reduced Instruction Set Computer), an architecture that uses a smaller set of instructions. A simpler instruction set may offer
3625-504: Is applied to many successive generations of bipolar logic, with gradual improvements in speed and power consumption over about two decades. The most recently introduced family 74Fxx is still sold today (as of 2019), and was widely used into the late 90s. 74AS/ALS Advanced Schottky was introduced in 1985. As of 2008, Texas Instruments continues to supply the more general-purpose chips in numerous obsolete technology families, albeit at increased prices. Typically, TTL chips integrate no more than
3750-406: Is buffered by a common emitter amplifier. Inputs both logical ones. When all the inputs are held at high voltage, the base–emitter junctions of the multiple-emitter transistor are reverse-biased. Unlike DTL, a small “collector” current (approximately 10 μA) is drawn by each of the inputs. This is because the transistor is in reverse-active mode . An approximately constant current flows from
3875-515: Is defined as "low" when between 0 V and 0.8 V with respect to the ground terminal, and "high" when between 2 V and V CC (5 V), and if a voltage signal ranging between 0.8 V and 2.0 V is sent into the input of a TTL gate, there is no certain response from the gate and therefore it is considered "uncertain" (precise logic levels vary slightly between sub-types and by temperature). TTL outputs are typically restricted to narrower limits of between 0.0 V and 0.4 V for
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4000-602: Is due to the many addressing modes and optimizations (such as sub-register addressing, memory operands in ALU instructions, absolute addressing, PC-relative addressing, and register-to-register spills) that CISC ISAs offer. The size or length of an instruction varies widely, from as little as four bits in some microcontrollers to many hundreds of bits in some VLIW systems. Processors used in personal computers , mainframes , and supercomputers have minimum instruction sizes between 8 and 64 bits. The longest possible instruction on x86
4125-553: Is similar to the code density of RISC; the increased instruction density is offset by requiring more of the primitive instructions to do a task. There has been research into executable compression as a mechanism for improving code density. The mathematics of Kolmogorov complexity describes the challenges and limits of this. In practice, code density is also dependent on the compiler . Most optimizing compilers have options that control whether to optimize code generation for execution speed or for code density. For instance GCC has
4250-481: Is substantially slower. Designers can combine ECL and TTL devices in the same system to achieve best overall performance and economy, but level-shifting devices are required between the two logic families. TTL is less sensitive to damage from electrostatic discharge than early CMOS devices. Due to the output structure of TTL devices, the output impedance is asymmetrical between the high and low state, making them unsuitable for driving transmission lines. This drawback
4375-432: Is then unpacked at the decode stage and executed as two instructions. Minimal instruction set computers (MISC) are commonly a form of stack machine , where there are few separate instructions (8–32), so that multiple instructions can be fit into a single machine word. These types of cores often take little silicon to implement, so they can be easily realized in an FPGA or in a multi-core form. The code density of MISC
4500-400: Is usually overcome by buffering the outputs with special line-driver devices where signals need to be sent through cables. ECL, by virtue of its symmetric low-impedance output structure, does not have this drawback. The TTL "totem-pole" output structure often has a momentary overlap when both the upper and lower transistors are conducting, resulting in a substantial pulse of current drawn from
4625-504: The ARM with Thumb-extension have mixed variable encoding, that is two fixed, usually 32-bit and 16-bit encodings, where instructions cannot be mixed freely but must be switched between on a branch (or exception boundary in ARMv8). Fixed-length instructions are less complicated to handle than variable-length instructions for several reasons (not having to check whether an instruction straddles
4750-489: The CPU in a computer or a family of computers. A device or program that executes instructions described by that ISA, such as a central processing unit (CPU), is called an implementation of that ISA. In general, an ISA defines the supported instructions , data types , registers , the hardware support for managing main memory , fundamental features (such as the memory consistency , addressing modes , virtual memory ), and
4875-769: The CPU , connecting semiconductor memory to the processor, with core memory and I/O devices connected via the Unibus. In the PDP–11/70, this was taken a step further, with the addition of a dedicated interface between disks and tapes and memory, via the Massbus . Although input/output devices continued to be mapped into memory addresses, some additional programming was necessary to set up the added bus interfaces. The PDP–11 supports hardware interrupts at four priority levels. Interrupts are serviced by software service routines, which could specify whether they themselves could be interrupted (achieving interrupt nesting ). The event that causes
5000-514: The DEC VAX and Data General Eclipse ; however some computer families were based on proprietary components (e.g. Fairchild CTL) while supercomputers and high-end mainframes used emitter-coupled logic . They were also used for equipment such as machine tool numerical controls, printers and video display terminals, and as microprocessors became more functional for "glue logic" applications, such as address decoders and bus drivers, which tie together
5125-608: The PDP–8 in many real-time computing applications, although both product lines lived in parallel for more than 10 years. The ease of programming of the PDP–11 made it popular for general-purpose computing. The design of the PDP–11 inspired the design of late-1970s microprocessors including the Intel x86 and the Motorola 68000 . The design features of PDP–11 operating systems, and other operating systems from Digital Equipment, influenced
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5250-411: The compiler responsible for instruction issue and scheduling. Architectures with even less complexity have been studied, such as the minimal instruction set computer (MISC) and one-instruction set computer (OISC). These are theoretically important types, but have not been commercialized. Machine language is built up from discrete statements or instructions . On the processing architecture,
5375-521: The input/output model of implementations of the ISA. An ISA specifies the behavior of machine code running on implementations of that ISA in a fashion that does not depend on the characteristics of that implementation, providing binary compatibility between implementations. This enables multiple implementations of an ISA that differ in characteristics such as performance , physical size, and monetary cost (among other things), but that are capable of running
5500-438: The instruction pipeline only allow a single memory load or memory store per instruction, leading to a load–store architecture (RISC). For another example, some early ways of implementing the instruction pipeline led to a delay slot . Transistor%E2%80%93transistor logic Transistor–transistor logic ( TTL ) is a logic family built from bipolar junction transistors . Its name signifies that transistors perform both
5625-529: The microarchitecture of a processor, engineers use blocks of "hard-wired" electronic circuitry (often designed separately) such as adders, multiplexers, counters, registers, ALUs, etc. Some kind of register transfer language is then often used to describe the decoding and sequencing of each instruction of an ISA using this physical microarchitecture. There are two basic ways to build a control unit to implement this description (although many designs use middle ways or compromises): Some microcoded CPU designs with
5750-457: The stack or in an implicit register. If some of the operands are given implicitly, fewer operands need be specified in the instruction. When a "destination operand" explicitly specifies the destination, an additional operand must be supplied. Consequently, the number of operands encoded in an instruction may differ from the mathematically necessary number of arguments for a logical or arithmetic operation (the arity ). Operands are either encoded in
5875-504: The x86 instruction set , but they have radically different internal designs. The concept of an architecture , distinct from the design of a specific machine, was developed by Fred Brooks at IBM during the design phase of System/360 . Prior to NPL [System/360], the company's computer designers had been free to honor cost objectives not only by selecting technologies but also by fashioning functional and architectural refinements. The SPREAD compatibility objective, in contrast, postulated
6000-431: The "opcode" representation of the instruction, or else are given as values or addresses following the opcode. Register pressure measures the availability of free registers at any point in time during the program execution. Register pressure is high when a large number of the available registers are in use; thus, the higher the register pressure, the more often the register contents must be spilled into memory. Increasing
6125-438: The "totem-pole" output stage is the decreased voltage level (no more than 3.5 V) of the output logical "1" (even if the output is unloaded). The reasons for this reduction are the voltage drops across the V 3 base–emitter and V 5 anode–cathode junctions. Like DTL, TTL is a current-sinking logic since a current must be drawn from inputs to bring them to a logic 0 voltage level. The driving stage must absorb up to 1.6 mA from
6250-533: The 1970s. Initially manufactured of small-scale transistor–transistor logic , a single-board large-scale integration version of the processor was developed in 1975. A two- or three-chip processor, the J-11 was developed in 1979. The last models of the PDP–11 line were the single board PDP–11/94 and PDP–11/93 introduced in 1990. The PDP–11 processor architecture has a mostly orthogonal instruction set . For example, instead of instructions such as load and store ,
6375-406: The 1990s. Until the advent of programmable logic , discrete bipolar logic was used to prototype and emulate microarchitectures under development. TTL inputs are the emitters of bipolar transistors. In the case of NAND inputs, the inputs are the emitters of multiple-emitter transistors , functionally equivalent to multiple transistors where the bases and collectors are tied together. The output
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#17327809583036500-404: The 7401 and 7403 series. Open-collector outputs of some gates have a higher maximum voltage, such as 15 V for the 7426, useful when driving non-TTL loads. To solve the problem with the high output resistance of the simple output stage the second schematic adds to this a "totem-pole" (" push–pull ") output. It consists of the two n-p-n transistors V 3 and V 4 , the "lifting" diode V 5 and
6625-656: The DEQNA Q-Bus card, were also available. Many of the earliest systems on the ARPANET were PDP–11's A wide range of peripherals were available; some of them were also used in other DEC systems like the PDP–8 or PDP–10 . The following are some of the more common PDP–11 peripherals. The PDP–11 family of computers was used for many purposes. It was used as a standard minicomputer for general-purpose computing, such as timesharing , scientific, educational, medical, government or business computing. Another common application
6750-764: The DN100 in 1981 running Domain/OS , which was proprietary but offered a degree of Unix compatibility; and the Silicon Graphics IRIS range, which developed into Unix-based workstations by 1985 (IRIS 2000). Personal computers based on the 68000 such as the Apple Lisa and Macintosh , the Atari ST , and the Commodore Amiga arguably constituted less of a threat to DEC's business, although technically these systems could also run Unix derivatives. In
6875-541: The Eastern Bloc (Soviet Union, GDR, Poland, Czechoslovakia, Hungary, Romania — for details see 7400 series ). Not only did others make compatible TTL parts, but compatible parts were made using many other circuit technologies as well. At least one manufacturer, IBM , produced non-compatible TTL circuits for its own use; IBM used the technology in the IBM System/38 , IBM 4300 , and IBM 3081 . The term "TTL"
7000-537: The LSI-11. This option allowed programming of the internal 8-bit micromachine to create application-specific extensions to the PDP–11 instruction set. The WCS is a quad Q-Bus board with a ribbon cable connecting to the third microcode ROM socket. The source code for EIS/FIS microcode was included so these instructions, normally located in the third MICROM, could be loaded in the WCS, if desired. Later Q-Bus based systems such as
7125-506: The LSI–11/23, /73, and /83 are based upon chip sets designed in house by Digital Equipment Corporation. Later PDP–11 Unibus systems were designed to use similar Q-Bus processor cards, using a Unibus adapter to support existing Unibus peripherals , sometimes with a special memory bus for improved speed. There were other significant innovations in the Q-Bus lineup. For example, a system variant of
7250-670: The PC based on BSD or Linux became available. By the late 1990s, not only DEC but most of the New England computer industry which had been built around minicomputers similar to the PDP–11 collapsed in the face of microcomputer-based workstations and servers. The PDP–11 processors tend to fall into several natural groups depending on the original design upon which they are based and which I/O bus they use. Within each group, most models were offered in two versions, one intended for OEMs and one intended for end-users. Although all models share
7375-556: The PDP–11 and could use its peripherals and system software. These include: Several operating systems were available for the PDP–11. The DECSA communications server was a communications platform developed by DEC based on a PDP–11/24, with the provision for user installable I/O cards including asynchronous and synchronous modules. This product was used as one of the earliest commercial platforms upon which networking products could be built, including X.25 gateways, SNA gateways, routers , and terminal servers . Ethernet adaptors, such as
7500-709: The PDP–11 has a move instruction for which either operand (source and destination) can be memory or register. There are no specific input or output instructions; the PDP–11 uses memory-mapped I/O and so the same move instruction is used; orthogonality even enables moving data directly from an input device to an output device. More complex instructions such as add likewise can have memory, register, input, or output as source or destination. Most operands can apply any of eight addressing modes to eight registers. The addressing modes provide register, immediate, absolute, relative, deferred (indirect), and indexed addressing, and can specify autoincrementation and autodecrementation of
7625-402: The PDP–11 system-software rights to Mentec Inc., an Irish producer of LSI-11 based boards for Q-Bus and ISA architecture personal computers, and in 1997 discontinued PDP–11 production. For several years, Mentec produced new PDP–11 processors. Other companies found a niche market for replacements for legacy PDP–11 processors, disk subsystems, etc. At the same time, free implementations of Unix for
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#17327809583037750-551: The PDP–11. In 1963, DEC introduced what is considered to be the first commercial minicomputer in the form of the PDP–5 . This was a 12-bit design adapted from the 1962 LINC machine that was intended to be used in a lab setting. DEC slightly simplified the LINC system and instruction set, aiming the PDP-5 at smaller settings that did not need the power of their larger 18-bit PDP-4 . The PDP-5
7875-479: The PDP–11/03 introduced full system power-on self-test (POST). The basic design of the PDP–11 was flexible, and was continually updated to use newer technologies. However, the limited throughput of the Unibus and Q-Bus started to become a system-performance bottleneck , and the 16-bit logical address limitation hampered the development of larger software applications. The article on PDP–11 architecture describes
8000-606: The PSW (priority level) on entry to the service routine. The PDP–11 was designed for ease of manufacture by semiskilled labor. The dimensions of its pieces were relatively non-critical. It used a wire-wrapped backplane . The LSI–11 (PDP–11/03), introduced in February 1975 is the first PDP–11 model produced using large-scale integration ; the entire CPU is contained on four LSI chips made by Western Digital (the MCP-1600 chip set;
8125-519: The TSD (Test System Director). As such, they were in use until their software was rendered inoperable by the Year 2000 problem . The US Navy used a PDP–11/34 to control its Multi-station Spatial Disorientation Device, a simulator used in pilot training, until 2007, when it was replaced by a PC-based emulator that could run the original PDP–11 software and interface with custom Unibus controller cards. A PDP–11/45
8250-418: The Unibus only allows an 18-bit physical address) and block-mode operations for significantly improved bandwidth (which the Unibus does not support). The CPU microcode includes a debugger : firmware with a direct serial interface ( RS-232 or current loop ) to a terminal . This lets the operator do debugging by typing commands and reading octal numbers, rather than operating switches and reading lights,
8375-452: The bottom of the resistor and ground. If one input voltage becomes zero, the corresponding base–emitter junction of the multiple-emitter transistor is in parallel with these two junctions. A phenomenon called current steering means that when two voltage-stable elements with different threshold voltages are connected in parallel, the current flows through the path with the smaller threshold voltage. That is, current flows out of this input and into
8500-595: The bytecode for commonly used code paths into native machine code. In addition, these virtual machines execute less frequently used code paths by interpretation (see: Just-in-time compilation ). Transmeta implemented the x86 instruction set atop VLIW processors in this fashion. An ISA may be classified in a number of different ways. A common classification is by architectural complexity . A complex instruction set computer (CISC) has many specialized instructions, some of which may only be rarely used in practical programs. A reduced instruction set computer (RISC) simplifies
8625-628: The controls of the Phoenix missile . TTL became popular with electronic systems designers after Texas Instruments introduced the 5400 series of ICs, with military temperature range, in 1964 and the later 7400 series , specified over a narrower range and with inexpensive plastic packages, in 1966. The Texas Instruments 7400 family became an industry standard. Compatible parts were made by Motorola , AMD , Fairchild , Intel , Intersil , Signetics , Mullard , Siemens , SGS-Thomson , Rifa , National Semiconductor , and many other companies, even in
8750-424: The current-limiting resistor R 3 (see the figure on the right). It is driven by applying the same current steering idea as above. When V 2 is "off", V 4 is "off" as well and V 3 operates in active region as a voltage follower producing high output voltage (logical "1"). When V 2 is "on", it activates V 4 , driving low voltage (logical "0") to the output. Again there is a current-steering effect:
8875-538: The design of operating systems such as CP/M and hence also MS-DOS . The first officially named version of Unix ran on the PDP–11/20 in 1970. It is commonly stated that the C programming language took advantage of several low-level PDP–11–dependent programming features, albeit not originally by design. An effort to expand the PDP–11 from 16- to 32-bit addressing led to the VAX-11 design, which took part of its name from
9000-436: The digital domain but would not ordinarily be used where analog amplification is the primary purpose. TTL inverters can also be used in crystal oscillators where their analog amplification ability is significant. A TTL gate may operate inadvertently as an analog amplifier if the input is connected to a slowly changing input signal that traverses the unspecified region from 0.8 V to 2 V. The output can be erratic when
9125-784: The diode. However, this technique actually converts the sophisticated "totem-pole" output into a simple output stage having significant output resistance when driving a high level (determined by the external resistor). Like most integrated circuits of the period 1963–1990, commercial TTL devices are usually packaged in dual in-line packages (DIPs), usually with 14 to 24 pins, for through-hole or socket mounting. Epoxy plastic (PDIP) packages were often used for commercial temperature range components, while ceramic packages (CDIP) were used for military temperature range parts. Beam-lead chip dies without packages were made for assembly into larger arrays as hybrid integrated circuits. Parts for military and aerospace applications were packaged in flatpacks ,
9250-651: The early years, in particular, Microsoft 's Xenix was ported to systems like the TRS-80 Model 16 (with up to 1 MB of memory) in 1983, and to the Apple Lisa, with up to 2 MB of installed RAM, in 1984. The mass-production of those chips eliminated any cost advantage for the 16-bit PDP–11. A line of personal computers based on the PDP–11, the DEC Professional series, failed commercially, along with other non-PDP–11 PC offerings from DEC. In 1994, DEC sold
9375-599: The emergence of a market of increasingly powerful scientific and technical workstations that would often run Unix variants. These included the HP 9000 series 200 (starting with the HP 9826A in 1981) and 300/400, with the HP-UX system being ported to the 68000 in 1984; Sun Microsystems workstations running SunOS , starting with the Sun-1 in 1982; Apollo/Domain workstations starting with
9500-414: The equivalent TTL component and with the same pinouts . For example, the 74HCT00 series provides many drop-in replacements for bipolar 7400 series parts, but uses CMOS technology. Successive generations of technology produced compatible parts with improved power consumption or switching speed, or both. Although vendors uniformly marketed these various product lines as TTL with Schottky diodes , some of
9625-406: The expression stack , not on data registers or arbitrary main memory cells. This can be very convenient for compiling high-level languages, because most arithmetic expressions can be easily translated into postfix notation. Conditional instructions often have a predicate field—a few bits that encode the specific condition to cause an operation to be performed rather than not performed. For example,
9750-501: The function blocks realized in VLSI elements. The Gigatron TTL is a more recent (2018) example of a processor built entirely with TTL integrated circuits. While originally designed to handle logic-level digital signals, a TTL inverter can be biased as an analog amplifier. Connecting a resistor between the output and the input biases the TTL element as a negative feedback amplifier . Such amplifiers may be useful to convert analog signals to
9875-515: The hardware and software techniques used to work around address-space limitations. DEC's 32-bit successor to the PDP–11, the VAX–11 (for "Virtual Address eXtension") overcame the 16-bit limitation, but was initially a superminicomputer aimed at the high-end time-sharing market. The early VAX CPUs provided a PDP–11 compatibility mode under which much existing software could be immediately used, in parallel with newer 32-bit software, but this capability
10000-414: The hardware running the emulator is an order of magnitude faster. Today, it is common practice for vendors of new ISAs or microarchitectures to make software emulators available to software developers before the hardware implementation is ready. Often the details of the implementation have a strong influence on the particular instructions selected for the instruction set. For example, many implementations of
10125-505: The input is in this range. A slowly changing input like this can also cause excess power dissipation in the output circuit. If such an analog input must be used, there are specialized TTL parts with Schmitt trigger inputs available that will reliably convert the analog input to a digital value, effectively operating as a one bit A to D converter. TTL serial refers to single-ended serial communication using raw transistor voltage levels: "low" for 0 and "high" for 1. UART over TTL serial
10250-685: The input transistor. If individually packaged transistors were used, the cost of all the transistors would discourage one from using such an input structure. But in an integrated circuit, the additional emitters for extra gate inputs add only a small area. At least one computer manufacturer, IBM, built its own flip chip integrated circuits with TTL; these chips were mounted on ceramic multi-chip modules. TTL devices consume substantially more power than equivalent CMOS devices at rest, but power consumption does not increase with clock speed as rapidly as for CMOS devices. Compared to contemporary ECL circuits, TTL uses less power and has easier design rules but
10375-546: The instruction set includes support for something such as " fetch-and-add ", " load-link/store-conditional " (LL/SC), or "atomic compare-and-swap ". A given instruction set can be implemented in a variety of ways. All ways of implementing a particular instruction set provide the same programming model , and all implementations of that instruction set are able to run the same executables. The various ways of implementing an instruction set give different tradeoffs between cost, performance, power consumption, size, etc. When designing
10500-412: The interrupt is indicated by the device itself, as it informs the processor of the address of its own interrupt vector. Interrupt vectors are blocks of two 16-bit words in low kernel address space (which normally corresponded to low physical memory) between 0 and 776. The first word of the interrupt vector contains the address of the interrupt service routine and the second word the value to be loaded into
10625-663: The large number of bits needed to encode the three registers of a 3-operand instruction, RISC architectures that have 16-bit instructions are invariably 2-operand designs, such as the Atmel AVR, TI MSP430 , and some versions of ARM Thumb . RISC architectures that have 32-bit instructions are usually 3-operand designs, such as the ARM , AVR32 , MIPS , Power ISA , and SPARC architectures. Each instruction specifies some number of operands (registers, memory locations, or immediate values) explicitly . Some instructions give one or both operands implicitly, such as by being stored on top of
10750-648: The logic function (the first "transistor") and the amplifying function (the second "transistor"), as opposed to earlier resistor–transistor logic (RTL) and diode–transistor logic (DTL). TTL integrated circuits (ICs) were widely used in applications such as computers , industrial controls, test equipment and instrumentation, consumer electronics, and synthesizers . After their introduction in integrated circuit form in 1963 by Sylvania Electric Products , TTL integrated circuits were manufactured by several semiconductor companies. The 7400 series by Texas Instruments became particularly popular. TTL manufacturers offered
10875-513: The military-specification temperature range of −55 to +125 °C. Special quality levels and high-reliability parts are available for military and aerospace applications. Radiation-hardened devices (for example from the SNJ54 series) are offered for space applications. Before the advent of VLSI devices, TTL integrated circuits were a standard method of construction for the processors of minicomputer and midrange mainframe computers, such as
11000-543: The most fundamental abstractions in computing . An instruction set architecture is distinguished from a microarchitecture , which is the set of processor design techniques used, in a particular processor, to implement the instruction set. Processors with different microarchitectures can share a common instruction set. For example, the Intel Pentium and the AMD Athlon implement nearly identical versions of
11125-401: The number of registers in an architecture decreases register pressure but increases the cost. While embedded instruction sets such as Thumb suffer from extremely high register pressure because they have small register sets, general-purpose RISC ISAs like MIPS and Alpha enjoy low register pressure. CISC ISAs like x86-64 offer low register pressure despite having smaller register sets. This
11250-439: The operation to perform, such as add contents of memory to register —and zero or more operand specifiers, which may specify registers , memory locations, or literal data. The operand specifiers may have addressing modes determining their meaning or may be in fixed fields. In very long instruction word (VLIW) architectures, which include many microcode architectures, multiple simultaneous opcodes and operands are specified in
11375-447: The option -Os to optimize for small machine code size, and -O3 to optimize for execution speed at the cost of larger machine code. The instructions constituting a program are rarely specified using their internal, numeric form ( machine code ); they may be specified by programmers using an assembly language or, more commonly, may be generated from high-level programming languages by compilers . The design of instruction sets
11500-451: The other operating system. An ISA can be extended by adding instructions or other capabilities, or adding support for larger addresses and data values; an implementation of the extended ISA will still be able to execute machine code for versions of the ISA without those extensions. Machine code using those extensions will only run on implementations that support those extensions. The binary compatibility that they provide makes ISAs one of
11625-464: The output is needed to drive an input into an undefined region. In some cases (e.g., when the output of a TTL logic gate needs to be used for driving the input of a CMOS gate), the voltage level of the "totem-pole" output stage at output logical "1" can be increased closer to V CC by connecting an external resistor between the V4 collector and the positive rail. It pulls up the V 5 cathode and cuts-off
11750-449: The output is not loaded. A common variation omits the collector resistor of the output transistor, making an open-collector output. This allows the designer to fabricate wired logic by connecting the open-collector outputs of several logic gates together and providing a single external pull-up resistor . If any of the logic gates becomes logic low (transistor conducting), the combined output will be low. Examples of this type of gate are
11875-423: The output stage. The main advantage of TTL with a "totem-pole" output stage is the low output resistance at output logical "1". It is determined by the upper output transistor V 3 operating in active region as an emitter follower . The resistor R 3 does not increase the output resistance since it is connected in the V 3 collector and its influence is compensated by the negative feedback. A disadvantage of
12000-425: The positive rail, through the resistor and into the base of the multiple emitter transistor. This current passes through the base–emitter junction of the output transistor, allowing it to conduct and pulling the output voltage low (logical zero). An input logical zero. Note that the base–collector junction of the multiple-emitter transistor and the base–emitter junction of the output transistor are in series between
12125-476: The potential for higher speeds, reduced processor size, and reduced power consumption. However, a more complex set may optimize common operations, improve memory and cache efficiency, or simplify programming. Some instruction set designers reserve one or more opcodes for some kind of system call or software interrupt . For example, MOS Technology 6502 uses 00 H , Zilog Z80 uses the eight codes C7,CF,D7,DF,E7,EF,F7,FF H while Motorola 68000 use codes in
12250-510: The power supply. These pulses can couple in unexpected ways between multiple integrated circuit packages, resulting in reduced noise margin and lower performance. TTL systems usually have a decoupling capacitor for every one or two IC packages, so that a current pulse from one TTL chip does not momentarily reduce the supply voltage to another. Since the mid 1980s, several manufacturers supply CMOS logic equivalents with TTL-compatible input and output levels, usually bearing part numbers similar to
12375-624: The predecessors of Alcatel-Lucent , the Bell Telephone Manufacturing Company , developed the BTMC DPS-1500 packet-switching ( X.25 ) network and used PDP–11s in the regional and national network management system, with the Unibus directly connected to the DPS-1500 hardware. Higher-performance members of the PDP–11 family departed from the single-bus approach. The PDP–11/45 had a dedicated data path within
12500-443: The processor architecture made it unusually easy to invent new bus devices, including devices to control hardware that had not been contemplated when the processor was originally designed. DEC openly published the basic Unibus specifications, even offering prototyping bus interface circuit boards, and encouraging customers to develop their own Unibus-compatible hardware. The Unibus made the PDP–11 suitable for custom peripherals. One of
12625-570: The processor by efficiently implementing only the instructions that are frequently used in programs, while the less common operations are implemented as subroutines, having their resulting additional processor execution time offset by infrequent use. Other types include very long instruction word (VLIW) architectures, and the closely related long instruction word (LIW) and explicitly parallel instruction computing (EPIC) architectures. These architectures seek to exploit instruction-level parallelism with less hardware than RISC and CISC by making
12750-504: The project as it did not appear to offer a significant advantage over their existing 12- and 18-bit platforms. This prompted several of the engineers from the PDP-X program to leave DEC and form Data General . The next year they introduced the 16-bit Data General Nova . The Nova sold tens of thousands of units and launched what would become one of DEC's major competitors through the 1970s and 1980s. Ken Olsen , president and founder of DEC,
12875-479: The range A000..AFFF H . Fast virtual machines are much easier to implement if an instruction set meets the Popek and Goldberg virtualization requirements . The NOP slide used in immunity-aware programming is much easier to implement if the "unprogrammed" state of the memory is interpreted as a NOP . On systems with multiple processors, non-blocking synchronization algorithms are much easier to implement if
13000-417: The resistor R 3 limits the current flowing directly through the series connected transistor V 3 , diode V 5 and transistor V 4 that are all conducting. It also limits the output current in the case of output logical "1" and short connection to the ground. The strength of the gate may be increased without proportionally affecting the power consumption by removing the pull-up and pull-down resistors from
13125-488: The same arithmetic operation on multiple pieces of data at the same time. SIMD instructions have the ability of manipulating large vectors and matrices in minimal time. SIMD instructions allow easy parallelization of algorithms commonly involved in sound, image, and video processing. Various SIMD implementations have been brought to market under trade names such as MMX , 3DNow! , and AltiVec . On traditional architectures, an instruction includes an opcode that specifies
13250-532: The same as found in the 11/23, 11/23+ and 11/24. The PRO-380 is based on the DCJ-11 ("Jaws") chipset, the same as found in the 11/53,73,83 and others, though running only at 10 MHz because of limitations in the support chipset. The PDP–11 was sufficiently popular that many unlicensed PDP–11-compatible minicomputers and microcomputers were produced in Eastern Bloc countries. Some were pin-compatible with
13375-516: The same instruction set, later models added new instructions and interpreted certain instructions slightly differently. As the architecture evolved, there were also variations in handling of some processor status and control registers. The following models use the Unibus as their principal bus: The following models use the Q-Bus as their principal bus: The PDT series were desktop systems marketed as "smart terminals". The /110 and /130 were housed in
13500-433: The same machine code, so that a lower-performance, lower-cost machine can be replaced with a higher-cost, higher-performance machine without having to replace software. It also enables the evolution of the microarchitectures of the implementations of that ISA, so that a newer, higher-performance implementation of an ISA can run software that runs on previous generations of implementations. If an operating system maintains
13625-405: The series combination of V 2 's C-E junction and V 4 's B-E junction is in parallel with the series of V 3 B-E, V 5 's anode-cathode junction, and V 4 C-E. The second series combination has the higher threshold voltage, so no current flows through it, i.e. V 3 base current is deprived. Transistor V 3 turns "off" and it does not impact on the output. In the middle of the transition,
13750-533: The system would work as expected, and suddenly "the Desk Calculator project got hot". Much of the system was developed using a PDP-10 where the SIM-11 simulated what would become the PDP–11/20 and Bob Bowers wrote an assembler for it. At a late stage, the marketing team wanted to ship the system with 2K of memory as the minimal configuration. When McGowan stated this would mean an assembler could not run on
13875-512: The system, the minimum was expanded to 4K. The marketing team also wanted to use the forward slash character for comments in the assembler code, as was the case in the PDP–8 assembler. McGowan stated that he would then have to use semicolon to indicate division, and the idea was dropped. The PDP–11 family was announced in January 1970 and shipments began early that year. DEC sold over 170,000 PDP–11s in
14000-524: The target location not modified, if the condition is false. Similarly, IBM z/Architecture has a conditional store instruction. A few instruction sets include a predicate field in every instruction; this is called branch predication . Instruction sets may be categorized by the maximum number of operands explicitly specified in instructions. (In the examples that follow, a , b , and c are (direct or calculated) addresses referring to memory cells, while reg1 and so on refer to machine registers.) Due to
14125-414: The transition over a diode input structure. The main disadvantage of TTL with a simple output stage is the relatively high output resistance at output logical "1" that is completely determined by the output collector resistor. It limits the number of inputs that can be connected (the fanout ). Some advantage of the simple output stage is the high voltage level (up to V CC ) of the output logical "1" when
14250-472: The typical debugging method at the time. The operator can thus examine and modify the computer's registers, memory, and input/output devices, diagnosing and perhaps correcting failures in software and peripherals (unless a failure disables the microcode itself). The operator can also specify which disk to boot from. Both innovations increased the reliability and decreased the cost of the LSI-11. A Writable Control Store (WCS) option (KUV11-AA) could be added to
14375-559: The underlying circuits, such as used in the LS family, could rather be considered DTL . Variations of and successors to the basic TTL family, which has a typical gate propagation delay of 10ns and a power dissipation of 10 mW per gate, for a power–delay product (PDP) or switching energy of about 100 pJ , include: Most manufacturers offer commercial and extended temperature ranges: for example Texas Instruments 7400 series parts are rated from 0 to 70 °C, and 5400 series devices over
14500-430: The zero (low) voltage source. As a result, no current flows through the base of the output transistor, causing it to stop conducting and the output voltage becomes high (logical one). During the transition the input transistor is briefly in its active region; so it draws a large current away from the base of the output transistor and thus quickly discharges its base. This is a critical advantage of TTL over DTL that speeds up
14625-469: Was real-time process control and factory automation . Some OEM models were also frequently used as embedded systems to control complex systems like traffic-light systems, medical systems, numerical controlled machining , or for network management. An example of such use of PDP–11s was the management of the packet switched network Datanet 1. In the 1980s, the UK's air traffic control radar processing
14750-480: Was a success, ultimately selling about 1,000 machines. This led to the PDP–8 , a further cost-reduced 12-bit model that sold about 50,000 units. During this period, the computer market was moving from computer word lengths based on units of 6 bits to units of 8 bits, following the introduction of the 7-bit ASCII standard. In 1967–1968, DEC engineers designed a 16-bit machine, the PDP–X, but management ultimately canceled
14875-753: Was an important characteristic of any instruction set. It remained important on the initially-tiny memories of minicomputers and then microprocessors. Density remains important today, for smartphone applications, applications downloaded into browsers over slow Internet connections, and in ROMs for embedded applications. A more general advantage of increased density is improved effectiveness of caches and instruction prefetch. Computers with high code density often have complex instructions for procedure entry, parameterized returns, loops, etc. (therefore retroactively named Complex Instruction Set Computers , CISC ). However, more typical, or frequent, "CISC" instructions merely combine
15000-470: Was conducted on a PDP 11/34 system known as PRDS – Processed Radar Display System at RAF West Drayton. The software for the Therac-25 medical linear particle accelerator also ran on a 32K PDP 11/23. In 2013, it was reported that PDP–11 programmers would be needed to control nuclear power plants through 2050. Another use was for storage of test programs for Teradyne ATE equipment, in a system known as
15125-585: Was dropped with the first MicroVAX . For a decade, the PDP–11 was the smallest system that could run Unix , but in the 1980s, the IBM PC and its clones largely took over the small computer market; BYTE in 1984 reported that the PC's Intel 8088 microprocessor could outperform the PDP–11/23 when running Unix. Newer microprocessors such as the Motorola 68000 (1979) and Intel 80386 (1985) also included 32-bit logical addressing. The 68000 in particular facilitated
15250-506: Was invented in 1961 by James L. Buie of TRW , which declared it "particularly suited to the newly developing integrated circuit design technology." The original name for TTL was transistor-coupled transistor logic (TCTL). The first commercial integrated-circuit TTL devices were manufactured by Sylvania in 1963, called the Sylvania Universal High-Level Logic family (SUHL). The Sylvania parts were used in
15375-405: Was more interested in a small 8-bit machine than the larger 16-bit system. This became the "Desk Calculator" project. Not long after, Datamation published a note about a desk calculator being developed at DEC, which caused concern at Wang Laboratories , who were heavily invested in that market. Before long, it became clear that the entire market was moving to 16-bit, and the Desk Calculator began
15500-451: Was not available in 1971. The Datapoint 2200 from 1970 used TTL components for its CPU and was the basis for the 8008 and later the x86 instruction set. The 1973 Xerox Alto and 1981 Star workstations, which introduced the graphical user interface , used TTL circuits integrated at the level of arithmetic logic units (ALUs) and bitslices, respectively. Most computers used TTL-compatible " glue logic " between larger chips well into
15625-747: Was used for the experiment that discovered the J/ψ meson at the Brookhaven National Laboratory . In 1976, Samuel C. C. Ting received the Nobel Prize for this discovery. Another PDP–11/45 was used to create the Death Star plans during the briefing sequence in Star Wars . Instruction set In computer science , an instruction set architecture ( ISA ) is an abstract model that generally defines how software controls
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