Misplaced Pages

#471528

52-470: The Xputer represents a move away from the traditional Von Neumann computer architecture, to a coarse-grained "soft Arithmetic logic unit (ALU)" architecture. Parallelism is achieved by configurable elements known as reconfigurable datapath arrays (rDPA), organized in a two-dimensional array of ALU's similar to the KressArray . The Xputer architecture is data-stream-based, and is the counterpart of

104-459: A computer architecture can specify for determining the address, usually called the addressing modes . Some common ways the effective address can be found are: The CPU sends the decoded instruction as a set of control signals to the corresponding computer components. If the instruction involves arithmetic or logic, the ALU is utilized. This is the only stage of the instruction cycle that is useful from

156-519: A data operation cannot occur at the same time (since they share a common bus ). This is referred to as the von Neumann bottleneck , which often limits the performance of the corresponding system. The von Neumann architecture is simpler than the Harvard architecture (which has one dedicated set of address and data buses for reading and writing to memory and another set of address and data buses to fetch instructions ). A stored-program computer uses

208-525: A description titled First Draft of a Report on the EDVAC based on the work of Eckert and Mauchly. It was unfinished when his colleague Herman Goldstine circulated it, and bore only von Neumann's name (to the consternation of Eckert and Mauchly). The paper was read by dozens of von Neumann's colleagues in America and Europe, and influenced the next round of computer designs. Jack Copeland considers that it

260-502: A design architecture for an electronic digital computer with these components: The attribution of the invention of the architecture to von Neumann is controversial, not least because Eckert and Mauchly had done a lot of the required design work and claim to have had the idea for stored programs long before discussing the ideas with von Neumann and Herman Goldstine The term "von Neumann architecture" has evolved to refer to any stored-program computer in which an instruction fetch and

312-506: A desk calculator (in principle) is a fixed program computer. It can do basic mathematics , but it cannot run a word processor or games. Changing the program of a fixed-program machine requires rewiring, restructuring, or redesigning the machine. The earliest computers were not so much "programmed" as "designed" for a particular task. "Reprogramming"—when possible at all—was a laborious process that started with flowcharts and paper notes, followed by detailed engineering designs, and then

364-405: A facility was the need for a program to increment or otherwise modify the address portion of instructions, which operators had to do manually in early designs. This became less important when index registers and indirect addressing became usual features of machine architecture. Another use was to embed frequently used data in the instruction stream using immediate addressing . On a large scale,

416-607: A machine he called the Automatic Computing Engine (ACE) . He presented this to the executive committee of the British National Physical Laboratory on February 19, 1946. Although Turing knew from his wartime experience at Bletchley Park that what he proposed was feasible, the secrecy surrounding Colossus , that was subsequently maintained for several decades, prevented him from saying so. Various successful implementations of

468-677: A machine was the development of suitable memory with instantaneously accessible contents. At first they suggested using a special vacuum tube —called the " Selectron "—which the Princeton Laboratories of RCA had invented. These tubes were expensive and difficult to make, so von Neumann subsequently decided to build a machine based on the Williams memory . This machine—completed in June, 1952 in Princeton—has become popularly known as

520-466: A major influence. Modern functional programming and object-oriented programming are much less geared towards "pushing vast numbers of words back and forth" than earlier languages like FORTRAN were, but internally, that is still what computers spend much of their time doing, even highly parallel supercomputers. As of 1996, a database benchmark study found that three out of four CPU cycles were spent waiting for memory. Researchers expect that increasing

572-406: A malfunctioning program can damage itself, other programs, or the operating system , possibly leading to a computer crash . However, this problem also applies to conventional programs that lack bounds checking . Memory protection and various access controls generally safeguard against both accidental and malicious program changes. Instruction fetch The instruction cycle (also known as

SECTION 10

#1732772050472

624-420: A modular system with lower cost . This is sometimes called a "streamlining" of the architecture. In subsequent decades, simple microcontrollers would sometimes omit features of the model to lower cost and size. Larger computers added features for higher performance. The use of the same bus to fetch instructions and data leads to the von Neumann bottleneck , the limited throughput (data transfer rate) between

676-436: A test program, some dates are the first time the computer was demonstrated or completed, and some dates are for the first delivery or installation. Through the decades of the 1960s and 1970s computers generally became both smaller and faster, which led to evolutions in their architecture. For example, memory-mapped I/O lets input and output devices be treated the same as memory. A single system bus could be used to provide

728-473: A two-way register that holds data fetched from memory or data waiting to be stored in memory (it is also known as the memory buffer register (MBR) because of this). Eventually, the instruction in the MDR is copied into the current instruction register (CIR) which acts as a temporary holding ground for the instruction that has just been fetched from memory. During the decode stage, the control unit (CU) will decode

780-455: Is "historically inappropriate to refer to electronic stored-program digital computers as 'von Neumann machines ' ". His Los Alamos colleague Stan Frankel said of von Neumann's regard for Turing's ideas I know that in or about 1943 or '44 von Neumann was well aware of the fundamental importance of Turing's paper of 1936.... Von Neumann introduced me to that paper and at his urging I studied it with care. Many people have acclaimed von Neumann as

832-449: Is reserved for performing floating-point operations . Each computer's CPU can have different cycles based on different instruction sets, but will be similar to the following cycle: In addition, on most processors interrupts can occur. This will cause the CPU to jump to an interrupt service routine, execute that and then return. In some cases an instruction can be interrupted in the middle,

884-690: The ENIAC at the Moore School of Electrical Engineering of the University of Pennsylvania , wrote about the stored-program concept in December 1943. In planning a new machine, EDVAC , Eckert wrote in January 1944 that they would store data and programs in a new addressable memory device, a mercury metal delay-line memory . This was the first time the construction of a practical stored-program machine

936-466: The Java virtual machine , or languages embedded in web browsers ). On a smaller scale, some repetitive operations such as BITBLT or pixel and vertex shaders can be accelerated on general purpose processors with just-in-time compilation techniques. This is one use of self-modifying code that has remained popular. The mathematician Alan Turing , who had been alerted to a problem of mathematical logic by

988-423: The University of Kaiserslautern . Instead of FPGAs ( field-programmable gate arrays ) having single bit configurable logic blocks (CLBs), rDPAs have multiple bits wide (for instance, 32 bit path width) reconfigurable datapath units (rDPUs). Each rDPU can be configured to perform an individual function. These rDPUs and interconnects can be programmed after the manufacturing process by the customer/designer (hence

1040-509: The central processing unit (CPU) and memory compared to the amount of memory. Because the single bus can only access one of the two classes of memory at a time, throughput is lower than the rate at which the CPU can work. This seriously limits the effective processing speed when the CPU is required to perform minimal processing on large amounts of data. The CPU is continually forced to wait for needed data to move to or from memory. Since CPU speed and memory size have increased much faster than

1092-417: The fetch–decode–execute cycle , or simply the fetch–execute cycle ) is the cycle that the central processing unit (CPU) follows from boot-up until the computer has shut down in order to process instructions. It is composed of three main stages: the fetch stage, the decode stage, and the execute stage. In simpler CPUs, the instruction cycle is executed sequentially, each instruction being processed before

SECTION 20

#1732772050472

1144-720: The instruction -based von Neumann computer architecture. The Xputer architecture was one of the first coarse-grained reconfigurable architectures, and consists of a reconfigurable datapath array (rDPA) organized as a two-dimensional array of ALUs (rDPU). The bus-width between ALU's were 32-bit in the first version of the Xputer. The ALUs (also known as rDPUs) are used for computing a single mathematical operation, such as addition, subtraction or multiplication, and can also be used purely for routing. ALUs are mesh-connected via three types of connections, and data-flow along these connections are managed by an address generation unit. Programs for

1196-487: The " reduction to practice " of these concepts but I would not regard these as comparable in importance with the introduction and explication of the concept of a computer able to store in its memory its program of activities and of modifying that program in the course of these activities. At the time that the "First Draft" report was circulated, Turing was producing a report entitled Proposed Electronic Calculator . It described in engineering and programming detail, his idea of

1248-404: The "father of the computer" (in a modern sense of the term) but I am sure that he would never have made that mistake himself. He might well be called the midwife, perhaps, but he firmly emphasized to me, and to others I am sure, that the fundamental conception is owing to Turing—in so far as not anticipated by Babbage.... Both Turing and von Neumann, of course, also made substantial contributions to

1300-514: The ACE design were produced. Both von Neumann's and Turing's papers described stored-program computers, but von Neumann's earlier paper achieved greater circulation and the computer architecture it outlined became known as the "von Neumann architecture". In the 1953 publication Faster than Thought: A Symposium on Digital Computing Machines (edited by B. V. Bowden), a section in the chapter on Computers in America reads as follows: The Machine of

1352-676: The Automatic Computing Engine, but although comparatively small in bulk and containing only about 800 thermionic valves, as can be judged from Plates XII, XIII and XIV, it is an extremely rapid and versatile calculating machine. The basic concepts and abstract principles of computation by a machine were formulated by Dr. A. M. Turing, F.R.S., in a paper . read before the London Mathematical Society in 1936, but work on such machines in Britain

1404-726: The Institute For Advanced Study, Princeton In 1945, Professor J. von Neumann, who was then working at the Moore School of Engineering in Philadelphia, where the E.N.I.A.C. had been built, issued on behalf of a group of his co-workers, a report on the logical design of digital computers. The report contained a detailed proposal for the design of the machine that has since become known as the E.D.V.A.C. (electronic discrete variable automatic computer). This machine has only recently been completed in America, but

1456-571: The Maniac. The design of this machine inspired at least half a dozen machines now being built in America, all known affectionately as "Johniacs". In the same book, the first two paragraphs of a chapter on ACE read as follows: Automatic Computation at the National Physical Laboratory One of the most modern digital computers which embodies developments and improvements in the technique of automatic electronic computing

1508-507: The Von Neumann performance bottleneck. For example, the following all can improve performance : The problem can also be sidestepped somewhat by using parallel computing , using for example the non-uniform memory access (NUMA) architecture—this approach is commonly employed by supercomputers . It is less clear whether the intellectual bottleneck that Backus criticized has changed much since 1977. Backus's proposed solution has not had

1560-550: The Xputer are written in the C language, and compiled for usage on the Xputer using the CoDeX compiler written by the author. The CoDeX compiler maps suitable portions of the C program onto the Xputer's rDPA fabric. The remainder of the program is executed on the host system, such as a personal computer . A reconfigurable datapath array (rDPA) is a semiconductor device containing reconfigurable data path units and programmable interconnects, first proposed by Rainer Kress in 1993, at

1612-588: The ability to treat instructions as data is what makes assemblers , compilers , linkers , loaders , and other automated programming tools possible. It makes "programs that write programs" possible. This has made a sophisticated self-hosting computing ecosystem flourish around von Neumann architecture machines. Some high-level languages leverage the von Neumann architecture by providing an abstract, machine-independent way to manipulate executable code at runtime (e.g., LISP ), or by using runtime information to tune just-in-time compilation (e.g. languages hosted on

Xputer - Misplaced Pages Continue

1664-476: The instruction in the CIR. The CU then sends signals to other components within the CPU, such as the arithmetic logic unit (ALU) and the floating point unit (FPU) . The ALU performs arithmetic operations such as addition and subtraction and also multiplication via repeated addition and division via repeated subtraction. It also performs logic operations such as AND , OR , NOT , and binary shifts as well. The FPU

1716-493: The instruction will have no effect, but will be re-executed after return from the interrupt. The first instruction cycle begins as soon as power is applied to the system, with an initial PC value that is predefined by the system's architecture (for instance, in Intel IA-32 CPUs, the predefined PC value is 0xfffffff0 ). Typically, this address points to a set of instructions in read-only memory (ROM), which begins

1768-573: The latter became the Electronics Section of the Laboratory, under the charge of Mr. F. M. Colebrook. The First Draft described a design that was used by many universities and corporations to construct their computers. Among these various computers, only ILLIAC and ORDVAC had compatible instruction sets. The date information in the following chronology is difficult to put into proper order. Some dates are for first running

1820-689: The lectures of Max Newman at the University of Cambridge , wrote a paper in 1936 entitled On Computable Numbers, with an Application to the Entscheidungsproblem , which was published in the Proceedings of the London Mathematical Society . In it he described a hypothetical machine he called a universal computing machine , now known as the " Universal Turing machine ". The hypothetical machine had an infinite store (memory in today's terminology) that contained both instructions and data. John von Neumann became acquainted with Turing while he

1872-449: The memory is decoded for the next steps and moved to the appropriate registers. The decoding is typically performed by binary decoders in the CPU 's control unit . This step evaluates which type of operation is to be performed, and if it is a memory operation, the computer determines the effective memory address to be used in the following Execute stage. There are various possible ways that

1924-502: The next instruction to be executed. During the fetch stage, the address stored in the PC is copied into the memory address register (MAR) and then the PC is incremented in order to "point" to the memory address of the next instruction to be executed. The CPU then takes the instruction at the memory address described by the MAR and copies it into the memory data register (MDR) . The MDR also acts as

1976-412: The next one is started. In most modern CPUs, the instruction cycles are instead executed concurrently , and often in parallel , through an instruction pipeline : the next instruction starts being processed before the previous instruction has finished, which is possible because the cycle is broken up into separate steps. The program counter (PC) is a special register that holds the memory address of

2028-445: The number of simultaneous instruction streams with multithreading or single-chip multiprocessing will make this bottleneck even worse. In the context of multi-core processors , additional overhead is required to maintain cache coherence between processors and threads. Aside from the von Neumann bottleneck, program modifications can be quite harmful, either by accident or design. In some simple stored-program computer designs,

2080-467: The often-arduous process of physically rewiring and rebuilding the machine. It could take three weeks to set up and debug a program on ENIAC . With the proposal of the stored-program computer, this changed. A stored-program computer includes, by design, an instruction set , and can store in memory a set of instructions (a program ) that details the computation . A stored-program design also allows for self-modifying code . One early motivation for such

2132-407: The process of loading (or booting ) the operating system . The fetch step is the same for each instruction: The control unit fetches the instruction's address from the memory unit . The decoding process allows the processor to determine what instruction is to be performed so that the CPU can tell how many operands it needs to fetch in order to perform the instruction. The opcode fetched from

Xputer - Misplaced Pages Continue

2184-615: The rDPA. rDPAs are not instruction-stream-driven and have no instruction fetch at run time. rDPUs do not have a program counter. Von Neumann architecture The von Neumann architecture —also known as the von Neumann model or Princeton architecture —is a computer architecture based on the First Draft of a Report on the EDVAC , written by John von Neumann in 1945, describing designs discussed with John Mauchly , J. Presper Eckert at University of Pennsylvania's Moore School of Electrical Engineering . The document describes

2236-471: The same hardware mechanism to encode and store both data and program instructions, but have caches between the CPU and memory, and, for the caches closest to the CPU, have separate caches for instructions and data, so that most instruction and data fetches use separate buses ( split-cache architecture ). The earliest computing machines had fixed programs. Some very simple computers still use this design, either for simplicity or training purposes. For example,

2288-615: The same underlying mechanism to encode both program instructions and data as opposed to designs which use a mechanism such as discrete plugboard wiring or fixed control circuitry for instruction implementation . Stored-program computers were an advancement over the manually reconfigured or fixed function computers of the 1940s, such as the Colossus and the ENIAC . These were programmed by setting switches and inserting patch cables to route data and control signals between various functional units. The vast majority of modern computers use

2340-428: The term "reconfigurable") so that the rDPA can perform whatever complex computation is needed. Because rDPUs are multiple bits wide (for instance, 32 bits), we talk about coarse-grained reconfigurability - in contrast to FPGAs with single-bit wide configurable logic blocks, called fine-gained reconfigurable. rDPAs are structurally programmed from "config-ware" source code , compiled into pipe-networks to be mapped onto

2392-406: The throughput between them, the bottleneck has become more of a problem, a problem whose severity increases with every new generation of CPU. The von Neumann bottleneck was described by John Backus in his 1977 ACM Turing Award lecture. According to Backus: Surely there must be a less primitive way of making big changes in the store than by pushing vast numbers of words back and forth through

2444-560: The von Neumann bottleneck. Not only is this tube a literal bottleneck for the data traffic of a problem, but, more importantly, it is an intellectual bottleneck that has kept us tied to word-at-a-time thinking instead of encouraging us to think in terms of the larger conceptual units of the task at hand. Thus programming is basically planning and detailing the enormous traffic of words through the von Neumann bottleneck, and much of that traffic concerns not significant data itself, but where to find it. There are several known methods for mitigating

2496-498: The von Neumann report inspired the construction of the E.D.S.A.C. (electronic delay-storage automatic calculator) in Cambridge (see p. 130). In 1947, Burks, Goldstine and von Neumann published another report that outlined the design of another type of machine (a parallel machine this time) that would be exceedingly fast, capable perhaps of 20,000 operations per second. They pointed out that the outstanding problem in constructing such

2548-570: Was a visiting professor at Cambridge in 1935, and also during Turing's PhD year at the Institute for Advanced Study in Princeton, New Jersey during 1936–1937. Whether he knew of Turing's paper of 1936 at that time is not clear. In 1936, Konrad Zuse also anticipated, in two patent applications, that machine instructions could be stored in the same storage used for data. Independently, J. Presper Eckert and John Mauchly , who were developing

2600-585: Was delayed by the war. In 1945, however, an examination of the problems was made at the National Physical Laboratory by Mr. J. R. Womersley, then superintendent of the Mathematics Division of the Laboratory. He was joined by Dr. Turing and a small staff of specialists, and, by 1947, the preliminary planning was sufficiently advanced to warrant the establishment of the special group already mentioned. In April, 1948,

2652-615: Was proposed. At that time, he and Mauchly were not aware of Turing's work. Von Neumann was involved in the Manhattan Project at the Los Alamos National Laboratory . It required huge amounts of calculation, and thus drew him to the ENIAC project, during the summer of 1944. There he joined the ongoing discussions on the design of this stored-program computer, the EDVAC. As part of that group, he wrote up

SECTION 50

#1732772050472

2704-502: Was recently demonstrated at the National Physical Laboratory, Teddington, where it has been designed and built by a small team of mathematicians and electronics research engineers on the staff of the Laboratory, assisted by a number of production engineers from the English Electric Company, Limited. The equipment so far erected at the Laboratory is only the pilot model of a much larger installation which will be known as

#471528