The TMS9900 was one of the first commercially available, single-chip 16-bit microprocessors . Introduced in June 1976, it implemented Texas Instruments ' TI-990 minicomputer architecture in a single-chip format, and was initially used for low-end models of that lineup.
112-525: Its 64-pin DIP format made it more expensive to implement in smaller machines than the more common 40-pin format, and it saw relatively few design wins outside TI's own use. Among those uses was their TI-99/4 and TI-99/4A home computers, which ultimately sold about 2.8 million units. Microcomputer-on-chip implementations of the 9900 in 40-pin packages included the TMS9940, TMS9980/81, and TMS9995. The SBP9900
224-598: A QIL package , has the same dimensions as a DIL package, but the leads on each side are bent into an alternating zigzag configuration so as to fit four lines of solder pads (instead of two with a DIL). The QIL design increased the spacing between solder pads without increasing package size, for two reasons: Commonly found DIP packages that conform to JEDEC standards use an inter-lead spacing (lead pitch) of 0.1 inches (2.54 mm) (JEDEC MS-001BA). Row spacing varies depending on lead counts, with 0.3 in. (7.62 mm) (JEDEC MS-001) or 0.6 inch (15.24 mm) (JEDEC MS-011)
336-521: A hex dump ), little-endian representation of integers has the significance increasing from right to left. In other words, it appears backwards when visualized, which can be counter-intuitive. This behavior arises, for example, in FourCC or similar techniques that involve packing characters into an integer, so that it becomes a sequence of specific characters in memory. For example, take the string "JOHN", stored in hexadecimal ASCII . On big-endian machines,
448-561: A printed circuit board (PCB) or inserted in a socket. The dual-inline format was invented by Don Forbes, Rex Rice and Bryant Rogers at Fairchild R&D in 1964, when the restricted number of leads available on circular transistor-style packages became a limitation in the use of integrated circuits . Increasingly complex circuits required more signal and power supply leads (as observed in Rent's rule ); eventually microprocessors and similar complex devices required more leads than could be put on
560-478: A subroutine is entered, only the single workspace register needs to be changed instead of requiring registers to be saved individually. Bits are numbered unconventionally with the most significant bit being 0. Addresses refer to bytes with big endian ordering convention. The TMS9900 is a classic 16 bit machine with an address space of 2 bytes (65,536 bytes or 32,768 words). There is no dedicated stack pointer register. Instead, branch instructions exist that save
672-481: A 32-bit base address of the segment stored in little-endian order, but in four nonconsecutive bytes, at relative positions 2, 3, 4 and 7 of the descriptor start. Hardware description languages (HDLs) used to express digital logic often support arbitrary endianness, with arbitrary granularity. For example, in SystemVerilog , a word can be defined as little-endian or big-endian. The recognition of endianness
784-478: A 4-bit interrupt priority input, which needed to be higher than the priority level stored in the status register (bits 12−15) in order for the interrupt request to be served. In addition, the /LOAD input provides a non-maskable interrupt facility with a dedicated vector. The TMS9900 CPU also contains a 16-bit shift register ("CRU") designed for interfacing with external shift registers, with dedicated instructions supporting access to fields of 1−16 bit width out of
896-458: A DIP package, leading to development of higher-density chip carriers . Furthermore, square and rectangular packages made it easier to route printed-circuit traces beneath the packages. A DIP is usually referred to as a DIP n , where n is the total number of pins, and sometimes appended with the row-to-row package width "N" for narrow (0.3") or "W" for wide (0.6"). For example, a microcircuit package with two rows of seven vertical leads would be
1008-493: A DIP14 or DIP14N. The photograph at the upper right shows three DIP14 ICs. Common packages have as few as three and as many as 64 leads. Many analog and digital integrated circuit types are available in DIP packages, as are arrays of transistors, switches, light emitting diodes, and resistors. DIP plugs for ribbon cables can be used with standard IC sockets. DIP packages are usually made from an opaque molded epoxy plastic pressed around
1120-526: A blank sheet. Notable among these was the TMS9900's use of processor registers that are mapped into main memory . This allows for fast context switching , which can be accomplished by changing a single register, the Workspace Pointer, to point to the first entry in a list of register values. More traditional designs would require the entire set of internal registers to be stored out to memory or
1232-470: A byte being part of a "field" is its "significance". These attributes of the parts of a field play an important role in the sequence the bytes are accessed by the computer hardware, more precisely: by the low-level algorithms contributing to the results of a computer instruction. Positional number systems (mostly base 2, or less often base 10) are the predominant way of representing and particularly of manipulating integer data by computers. In pure form this
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#17327810677821344-399: A circular window of clear quartz over the chip die to allow the part to be erased by ultraviolet light . Often, the same chips were also sold in less expensive windowless PDIP or CERDIP packages as one-time programmable (OTP) versions. Windowed and windowless packages were also used for microcontrollers, and other devices, containing EPROM memory. Windowed CERDIP-packaged EPROMs were used for
1456-548: A hollow plastic box with the bottom/back open, filled (around the contained electronic components) with a hard translucent epoxy material from which the leads emerge. Others, such as DIP switches, are composed of two (or more) plastic housing parts snapped, welded, or glued together around a set of contacts and tiny mechanical parts, with the leads emerging through molded-in holes or notches in the plastic. Several DIP variants for ICs exist, mostly distinguished by packaging material: EPROMs were sold in ceramic DIPs manufactured with
1568-472: A little-endian should start with FF FE 00 00 . Application binary data formats, such as MATLAB .mat files, or the .bil data format, used in topography, are usually endianness-independent. This is achieved by storing the data always in one fixed endianness or carrying with the data a switch to indicate the endianness. An example of the former is the binary XLS file format that is portable between Windows and Mac systems and always little-endian, requiring
1680-399: A new design is often arbitrary, but later technology revisions and updates perpetuate the existing endianness to maintain backward compatibility . A big-endian system stores the most significant byte of a word at the smallest memory address and the least significant byte at the largest. A little-endian system, in contrast, stores the least-significant byte at the smallest address. Of
1792-553: A non-replaceable 10-year lithium battery. DIP header blocks on to which discrete components could be soldered were used where groups of components needed to be easily removed, for configuration changes, optional features or calibration. The original dual-in-line package was invented by Bryant "Buck" Rogers in 1964 while working for Fairchild Semiconductor. The first devices had 14 pins and looked much like they do today. The rectangular shape allowed integrated circuits to be packaged more densely than previous round packages. The package
1904-547: A number of hardware architectures where floating-point numbers are represented in big-endian form while integers are represented in little-endian form. There are ARM processors that have mixed-endian floating-point representation for double-precision numbers: each of the two 32-bit words is stored as little-endian, but the most significant word is stored first. VAX floating point stores little-endian 16-bit words in big-endian order. Because there have been many floating-point formats with no network standard representation for them,
2016-483: A processor treats data accesses. Instruction accesses (fetches of instruction words) on a given processor may still assume a fixed endianness, even if data accesses are fully bi-endian, though this is not always the case, such as on Intel's IA-64 -based Itanium CPU, which allows both. Some nominally bi-endian CPUs require motherboard help to fully switch endianness. For instance, the 32-bit desktop-oriented PowerPC processors in little-endian mode act as little-endian from
2128-521: A second bend in the leads to flatten them parallel to the bottom plane of the plastic housing. The SOJ (Small Outline J-lead) and other SMT packages with "SOP" (for "Small Outline Package") in their names can be considered further relatives of the DIP, their original ancestor. SOIC packages tend to have half the pitch of DIP, and SOP are half that, a fourth of DIP. (0.1"/2.54 mm, 0.05"/1.27 mm, and 0.025"/0.635 mm, respectively) Pin grid array (PGA) packages may be considered to have evolved from
2240-436: A setting which allows for switchable endianness in data fetches and stores, instruction fetches, or both; those instruction set architectures are referred to as bi-endian . Architectures that support switchable endianness include PowerPC / Power ISA , SPARC V9, ARM versions 3 and above, DEC Alpha , MIPS , Intel i860 , PA-RISC , SuperH SH-4 , IA-64 , C-Sky , and RISC-V . This feature can improve performance or simplify
2352-406: A single byte, so the complexity of the hardware is not affected by the byte ordering. Addition, subtraction, and multiplication start at the least significant digit position and propagate the carry to the subsequent more significant position. On most systems, the address of a multi-byte value is the address of its first byte (the byte with the lowest address). The implementation of these operations
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#17327810677822464-522: A single positional element (character) also has a positional value. Lexicographical comparison means almost everywhere: first character ranks highest – as in the telephone book. Almost all machines which can do this using a single instruction are big-endian or at least mixed-endian. Integer numbers written as text are always represented most significant digit first in memory, which is similar to big-endian, independently of text direction . When memory bytes are printed sequentially from left to right (e.g. in
2576-407: A system call facility. In TI's DX10 operating system, XOP 15 invokes a system call. A programmer might define an assembler macro, for example SVC, which invokes XOP 15. Another use of XOP was to implement instructions in software which might be handled by dedicated hardware in future versions of the 990 minicomputer series. An example of such actions can be shown in the code below where a CALL function
2688-422: A tin-, silver-, or gold-plated lead frame that supports the device die and provides connection pins. Some types of IC are made in ceramic DIP packages, where high temperature or high reliability is required, or where the device has an optical window to the interior of the package. Most DIP packages are secured to a PCB by inserting the pins through holes in the board and soldering them in place. Where replacement of
2800-480: A total of 4096 addressable bits. Parallel peripherals can be attached in memory-mapped fashion to the regular address and data bus. The TMS9900 was used in the TI-99/4 and TI-99/4A home computers. Unfortunately, to reduce the production costs, TI chose to use in these systems just 128 16-bit words of the fast kind of RAM that the TMS9900 could access directly. The rest of the memory was 16KB of 8-bit DRAM that
2912-491: A word in a register to the opposite endianness, that is, they swap the order of the bytes in a 16-, 32- or 64-bit word. Recent Intel x86 and x86-64 architecture CPUs have a MOVBE instruction ( Intel Core since generation 4, after Atom ), which fetches a big-endian format word from memory or writes a word into memory in big-endian format. These processors are otherwise thoroughly little-endian. There are also devices which use different formats in different places. For instance,
3024-421: A year and a week number), sometimes where it was made, and other proprietary information (perhaps revision numbers, manufacturing plant codes, or stepping ID codes.) The necessity of laying out all of the leads in a basically radial pattern in a single plane from the die perimeter to two rows on the periphery of the package is the main reason that DIP packages with higher lead counts must have wider spacing between
3136-434: Is always even. For 0.3 inch spacing, typical lead counts are 8, 14, 16, and 20; less common are 4, 6, 18, 24, and 28 lead counts. To have an even number of leads some DIPs have unused not connected (NC) leads to the internal chip, or are duplicated, e.g. two ground pins. For 0.6 inch spacing, typical lead counts are 24, 28, 32, and 40; less common are 36, 42, 48, 52, and 64 lead counts. Some microprocessors, such as
3248-520: Is assigned a number, called its address , that the computer uses to access that data. On most modern computers, the smallest data group with an address is eight bits long and is called a byte. Larger groups comprise two or more bytes, for example, a 32-bit word contains four bytes. There are two possible ways a computer could number the individual bytes in a larger group, starting at either end. Both types of endianness are in widespread use in digital electronic engineering. The initial choice of endianness of
3360-690: Is fairly orthogonal , meaning that with few exceptions, instructions can use all methods of accessing operands (addressing modes). Addressing modes include Immediate (operand in instruction), Direct or "Symbolic" (operand address in instruction), Register (operand in workspace register), Register Indirect (operand address in workspace register) with or without auto-increment, Indexed (operand address in instruction indexed with workspace register content), and Program Counter Relative. The most important dual-operand instructions (add, subtract, compare, move etc.) contain 2-bit addressing mode and 4-bit register selector fields for both source and destination operands. In
3472-549: Is implemented using and XOP 6 Instruction. The beauty of this implementation of a CALL function using and XOP, is that it is straightforward to add checks to determine if the Stack has overflowed; for example C R10,@2*R9(R13), where R9 points to the address of the stack limit. In typical comparisons with the Intel 8086 , the TMS9900 had smaller programs. Some disadvantages were the small address space and need for fast RAM. The TMS9900
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3584-406: Is important when reading a file or filesystem created on a computer with different endianness. Fortran sequential unformatted files created with one endianness usually cannot be read on a system using the other endianness because Fortran usually implements a record (defined as the data written by a single Fortran statement) as data preceded and succeeded by count fields, which are integers equal to
3696-481: Is in principle a 16-bit little-endian system. The instructions to convert between floating-point and integer values in the optional floating-point processor of the PDP-11/45, PDP-11/70, and in some later processors, stored 32-bit "double precision integer long" values with the 16-bit halves swapped from the expected little-endian order. The UNIX C compiler used the same format for 32-bit long integers. This ordering
3808-539: Is known as PDP-endian . UNIX was one of the first systems to allow the same code to be compiled for platforms with different internal representations. One of the first programs converted was supposed to print out Unix , but on the Series/1 it printed nUxi instead. A way to interpret this endianness is that it stores a 32-bit integer as two little-endian 16-bit words, with a big-endian word ordering: Segment descriptors of IA-32 and compatible processors keep
3920-434: Is marginally simpler using little-endian machines where this first byte contains the least significant digit. Comparison and division start at the most significant digit and propagate a possible carry to the subsequent less significant digits. For fixed-length numerical values (typically of length 1,2,4,8,16), the implementation of these operations is marginally simpler on big-endian machines. Some big-endian processors (e.g.
4032-406: Is meant as the extremity where the big resp. little significance is written first , namely where the field starts . The integer data that are directly supported by the computer hardware have a fixed width of a low power of 2, e.g. 8 bits ≙ 1 byte, 16 bits ≙ 2 bytes, 32 bits ≙ 4 bytes, 64 bits ≙ 8 bytes, 128 bits ≙ 16 bytes. The low-level access sequence to the bytes of such a field depends on
4144-473: Is not as popular as the DIP, but has been used for packaging RAM chips and multiple resistors with a common pin. As compared to DIPs with a typical maximum pin count of 64, SIPs have a typical maximum pin count of 24 with lower package costs. One variant of the single in-line package uses part of the lead frame for a heat sink tab. This multi-leaded power package is useful for such applications as audio power amplifiers, for example. The QIP, sometimes called
4256-442: Is redirected to the corresponding address and unaligned access is not allowed. ARMv6 introduces BE-8 or byte-invariant mode, where access to a single byte works as in little-endian mode, but accessing a 16-bit, 32-bit or (starting with ARMv8) 64-bit word results in a byte swap of the data. This simplifies unaligned memory access as well as memory-mapped access to registers other than 32-bit. Many processors have instructions to convert
4368-515: Is used throughout the file. Computer memory consists of a sequence of storage cells (smallest addressable units); in machines that support byte addressing , those units are called bytes . Each byte is identified and accessed in hardware and software by its memory address . If the total number of bytes in memory is n , then addresses are enumerated from 0 to n − 1. Computer programs often use data structures or fields that may consist of more data than can be stored in one byte. In
4480-413: Is valid for moderate sized non-negative integers, e.g. of C data type unsigned . In such a number system, the value of a digit which it contributes to the whole number is determined not only by its value as a single digit, but also by the position it holds in the complete number, called its significance. These positions can be mapped to memory mainly in two ways: In these expressions, the term "end"
4592-527: The 6809 and the 68000 series of processors use the big-endian format. Solely big-endian architectures include the IBM z/Architecture and OpenRISC . The PDP-11 minicomputer, however, uses little-endian byte order, as does its VAX successor. The Datapoint 2200 used simple bit-serial logic with little-endian to facilitate carry propagation . When Intel developed the 8008 microprocessor for Datapoint, they used little-endian for compatibility. However, as Intel
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4704-682: The Altera Nios II , the Atmel AVR , the Andes Technology NDS32, the Qualcomm Hexagon , and many other processors and processor families are also little-endian. The Intel 8051 , unlike other Intel processors, expects 16-bit addresses for LJMP and LCALL in big-endian format; however, xCALL instructions store the return address onto the stack in little-endian format. Some instruction set architectures feature
4816-470: The BIOS ROM of many early IBM PC clones with an adhesive label covering the window to prevent inadvertent erasure through exposure to ambient light. Molded plastic DIPs are much lower in cost than ceramic packages; one 1979 study showed that a plastic 14 pin DIP cost around US$ 0.063 and a ceramic package cost US$ 0.82. A single in-line package ( SIP or SIL package ) has one row of connecting pins. It
4928-650: The Cray T3E ). IBM AIX and IBM i run in big-endian mode on bi-endian Power ISA; Linux originally ran in big-endian mode, but by 2019, IBM had transitioned to little-endian mode for Linux to ease the porting of Linux software from x86 to Power. SPARC has no relevant little-endian deployment, as both Oracle Solaris and Linux run in big-endian mode on bi-endian SPARC systems, and can be considered big-endian in practice. ARM, C-Sky, and RISC-V have no relevant big-endian deployments, and can be considered little-endian in practice. The term bi-endian refers primarily to how
5040-591: The Fairchild 9440 and Data General mN601 were both one-chip versions of Data General 's Nova . Unlike multi-chip 16-bit microprocessors such as the National Semiconductor IMP-16 or DEC LSI-11 , some of which predated the TMS9900, the 9900 was a single-chip, self-contained 16-bit microprocessor. The minicomputer roots of the TMS9900 give rise to a number of architectural features that are not commonly found on designs that started from
5152-463: The Intel Fortran compiler supports the non-standard CONVERT specifier when opening a file, e.g.: OPEN ( unit , CONVERT = 'BIG_ENDIAN' ,...) . Other compilers have options for generating code that globally enables the conversion for all file IO operations. This permits the reuse of code on a system with the opposite endianness without code modification. On most systems,
5264-465: The Intel 8088 for the IBM PC , he recalled. One factor was the lack of a roadmap for accessing more than 64K of logical memory. The 9900 family could expand its address space to 16MiB only by page-mapping; the 9900 could address 256K through segments. After dropping out of the personal computer market with products such as TI-99/4A , the company microprocessor division eventually switched focus to
5376-471: The Internet protocol suite , where it is referred to as network order , transmitting the most significant byte first. Conversely, little-endianness is the dominant ordering for processor architectures ( x86 , most ARM implementations, base RISC-V implementations) and their associated memory. File formats can use either ordering; some formats use a mixture of both or contain an indicator of which ordering
5488-467: The Motorola 68000 and Zilog Z180 , used lead counts as high as 64; this is typically the maximum number of leads for a DIP package. As shown in the diagram, leads are numbered consecutively from Pin 1. When the identifying notch in the package is at the top, Pin 1 is the top left corner of the device. Sometimes Pin 1 is identified with an indent or paint dot mark. For example, for a 14-lead DIP, with
5600-457: The TMS320 special-purpose processor series. The TMS9900 has three internal 16-bit registers — Program counter (PC), Status register (ST), and Workspace Pointer register (WP). The WP register points to a base address in external RAM where the processor's 16 general purpose user registers (each 16 bits wide) are kept. This architecture allows for quick context switching ; e.g. when
5712-784: The Texas Instruments TMS320 , introduced in 1983, and the Texas Instruments TMS340 graphics processor. The 9900 architecture lived on into the 1990s as the Communications Processor in TI's TMS380 chipset for Token Ring (later Ethernet). The TMS9900 was designed as a single chip version of the TI 990 minicomputer series, much like the Intersil 6100 was a single chip PDP-8 (12 bit), and
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#17327810677825824-454: The XDR standard uses big-endian IEEE 754 as its representation. It may therefore appear strange that the widespread IEEE 754 floating-point standard does not specify endianness. Theoretically, this means that even standard IEEE floating-point data written by one machine might not be readable by another. However, on modern standard computers (i.e., implementing IEEE 754), one may safely assume that
5936-447: The 1990s, and still continue to be used today. Because some modern chips are available only in surface-mount package types, a number of companies sell various prototyping adapters to allow those surface-mount devices (SMD) to be used like DIP devices with through-hole breadboards and soldered prototyping boards (such as stripboard and perfboard ). (SMT can pose quite a problem, at least an inconvenience, for prototyping in general; most of
6048-466: The 9900 included 128 or 256 bytes of fast onboard RAM for registers. TI used the same architecture across different divisions for corporate synergy: "one company, one computer architecture". In the late 1970s Walden C. Rhines gave a presentation of the TMS99110, then code-named “Alpha”, to an IBM group developing a personal computer. "We wouldn't know until 1981 just what we had lost" because IBM chose
6160-531: The Add instruction of the IBM 1401 addresses variable-length fields at their low-order (highest-addressed) position with their lengths being defined by a word mark set at their high-order (lowest-addressed) position. When an operation such as addition is performed, the processor begins at the low-order positions at the high addresses of the two fields and works its way down to the high-order. Another important attribute of
6272-675: The BQ27421 Texas Instruments battery gauge uses the little-endian format for its registers and the big-endian format for its random-access memory . SPARC historically used big-endian until version 9, which is bi-endian. Similarly early IBM POWER processors were big-endian, but the PowerPC and Power ISA descendants are now bi-endian. The ARM architecture was little-endian before version 3 when it became bi-endian. Although many processors use little-endian storage for all types of data (integer, floating point), there are
6384-534: The Branch and Load Workspace Pointer (BLWP) instruction loads new WP and PC values, then saves the values of WP, PC and ST to the (new) registers 13, 14 and 15 respectively. At the end of the subroutine, the Return Workspace Pointer (RTWP) restores these in reverse order. Using BLWP/RTWP, it is possible to nest subroutine calls despite the absence of a stack, however, the programmer needs to assign
6496-495: The C11 standard and commonly used in code interacting with hardware. Some operations in positional number systems have a natural or preferred order in which the elementary steps are to be executed. This order may affect their performance on small-scale byte-addressable processors and microcontrollers . However, high-performance processors usually fetch multi-byte operands from memory in the same amount of time they would have fetched
6608-647: The CPU in the 990/10A minicomputer as a cost reduction. Unfortunately, by the time the 990/10A made it to market, the end of the minicomputer era was already in sight. The TMS99000 family includes two microprocessors, the TMS99105A and the TMS99110A, which are identical except for the contents of on-chip macrostore ROM memory (macrostore memory contains added functions or instructions through emulation routines written in standard machine code). The on-chip ROM Macrostore in
6720-456: The DIP. PGAs with the same 0.1 inches (2.54 mm) pin centers as most DIPs were popular for microprocessors from the early to mid-1980s through the 1990s. Owners of personal computers containing Intel 80286 through P5 Pentium processors may be most familiar with these PGA packages, which were often inserted into ZIF sockets on motherboards . The similarity is such that a PGA socket may be physically compatible with some DIP devices, though
6832-461: The DIP64 used for the Motorola 68000 CPU) has long leads inside the package between pins and the die, making such a package unsuitable for high speed devices. Some other types of DIP devices are built very differently. Most of these have molded plastic housings and straight leads or leads that extend directly out of the bottom of the package. For some, LED displays particularly, the housing is usually
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#17327810677826944-720: The IBM System/360 and its successors) contain hardware instructions for lexicographically comparing varying length character strings . The normal data transport by an assignment statement is in principle independent of the endianness of the processor. Many historical and extant processors use a big-endian memory representation, either exclusively or as a design option. The IBM System/360 uses big-endian byte order, as do its successors System/370 , ESA/390 , and z/Architecture . The PDP-10 uses big-endian addressing for byte-oriented instructions. The IBM Series/1 minicomputer uses big-endian byte order. The Motorola 6800 / 6801,
7056-482: The IC die inside. Plastic DIP (PDIP) packages are usually sealed by fusing or cementing the plastic halves around the leads, but a high degree of hermeticity is not achieved because the plastic itself is usually somewhat porous to moisture and the process cannot ensure a good microscopic seal between the leads and the plastic at all points around the perimeter. However, contaminants are usually still kept out well enough that
7168-457: The SMT package that most resembles a typical DIP, appears essentially the same, notwithstanding size scale, except that after being bent down the leads are bent upward again by an equal angle to become parallel with the bottom plane of the package.) In ceramic (CERDIP) packages, an epoxy or grout is used to hermetically seal the two halves together, providing an air and moisture tight seal to protect
7280-489: The TMS9900 and a full software stack to go with it. They later went on to be co-founders of Autodesk , in part based on software first developed for these TMS9900 based systems. The second generation of the TMS9900 family of microprocessors was the TMS9995 which provided "functional performance at speeds 3 times faster than any previous 9900 family processor", largely due to the inclusion of instruction prefetch technology. In
7392-512: The TMS99110A microprocessor contains floating point instructions which are available as part of the machine language instruction set, while the baseline TMS99105A does not. Both chips can implement Macrostore instructions in an external ROM. A third member of the TMS99000 family, the TMS99120, was announced but may never have been commercially produced. The on-chip ROM Macrostore in the TMS99120
7504-421: The address of a multi-byte value is the address of its first byte (the byte with the lowest address); little-endian systems of that type have the property that, for sufficiently low data values, the same value can be read from memory at different lengths without using different addresses (even when alignment restrictions are imposed). For example, a 32-bit memory location with content 4A 00 00 00 can be read at
7616-474: The appropriate register workspace explicitly. The instruction set also contains a Branch and Link (BL) opcode that only saves PC to register 11 without changing WP. In this case, a branch instruction (B) using WR11 as the destination address can serve as the return opcode, but BL-type subroutines cannot be nested without the programmer taking actions to save the return address. The TMS9900 supports an execute instruction "X" (eXecute). This instruction executes
7728-531: The art, this advantage of DIPs is rapidly losing importance as well. Through the 1990s, devices with fewer than 20 leads were manufactured in a DIP format in addition to the newer formats. Since about 2000, newer devices are often unavailable in the DIP format. DIPs can be mounted either by through-hole soldering or in sockets. Sockets allow easy replacement of a device and eliminates the risk of damage from overheating during soldering. Generally sockets were used for high-value or large ICs, which cost much more than
7840-411: The characteristics of SMT that are advantages for mass production are difficulties for prototyping.) For programmable devices like EPROMs and GALs , DIPs remained popular for many years due to their easy handling with external programming circuitry (i.e., the DIP devices could be simply plugged into a socket on the programming device.) However, with In-System Programming (ISP) technology now state of
7952-439: The context of this article where its type cannot be arbitrarily complicated, a "field" consists of a consecutive sequence of bytes and represents a "simple data value" which – at least potentially – can be manipulated by one single hardware instruction . On most systems, the address of a multi-byte simple data value is the address of its first byte (the byte with the lowest address). There are exceptions to this rule – for example,
8064-516: The convention used by many other manufacturers, TI labeled the most significant address and data lines "A0" and "D0", respectively. All internal data paths and the ALU are 16 bits wide. The processor can be paused with the address bus tri-stated for external direct memory access (DMA). Memory accesses are always 16 bits wide, with the CPU automatically performing read-before-write operations for byte-wide accesses. The hardware interrupt system supports
8176-556: The converse is rarely true. Endianness In computing , endianness is the order in which bytes within a word of digital data are transmitted over a data communication medium or addressed (by rising addresses) in computer memory , counting only byte significance compared to earliness. Endianness is primarily expressed as big-endian (BE) or little-endian (LE), terms introduced by Danny Cohen into computer science for data ordering in an Internet Experiment Note published in 1980. The adjective endian has its origin in
8288-431: The device can operate reliably for decades with reasonable care in a controlled environment. Inside the package, the lower half has the leads embedded, and at the center of the package is a rectangular space, chamber, or void into which the IC die is cemented. The leads of the package extend diagonally inside the package from their positions of emergence along the periphery to points along a rectangular perimeter surrounding
8400-406: The device. Typical cure cycles for the resins are less than 2 minutes and a single cycle may produce hundreds of devices. The leads emerge from the longer sides of the package along the seam, parallel to the top and bottom planes of the package, and are bent downward approximately 90 degrees (or slightly less, leaving them angled slightly outward from the centerline of the package body). (The SOIC ,
8512-450: The die, tapering as they go to become fine contacts at the die. Ultra-fine bond wires (barely visible to the naked human eye) are welded between these die periphery contacts and bond pads on the die itself, connecting one lead to each bond pad, and making the final connection between the microcircuits and the external DIP leads. The bond wires are not usually taut but loop upward slightly to allow slack for thermal expansion and contraction of
8624-456: The effective address of the source operand in register 11 of the new workspace. The context saving feature of the XOP instruction can also be used as to implement inline debugging. XOP is less flexible than a BLWP, as the transfer vectors have to be at fixed locations, but allows one source operand to be directly addressed rather than passed in a register or otherwise. XOP can be used to implement
8736-446: The endianness is the same for floating-point numbers as for integers, making the conversion straightforward regardless of data type. Small embedded systems using special floating-point formats may be another matter, however. Most instructions considered so far contain the size (lengths) of their operands within the operation code . Frequently available operand lengths are 1, 2, 4, 8, or 16 bytes. But there are also architectures where
8848-526: The family can access 256KB of memory through code/data segmentation, and may use the TIM99610 memory mapper to address up to 16MiB. The architecture contains many other advances over the TMS9900 and TMS9995. Dual in-line package In microelectronics , a dual in-line package ( DIP or DIL ) is an electronic component package with a rectangular housing and two parallel rows of electrical connecting pins. The package may be through-hole mounted to
8960-707: The home computer arena, the TMS9995 only found use in the Tomy Tutor , an esoteric TI99-4/A upgrade called the Geneve 9640 , and a project printed in Electronics Today : the Powertran Cortex. It was planned to be used in the TI-99/2 & TI-99/8 computer systems, but neither advanced past the prototype stage. TI later developed the more powerful TMS99000 family of microprocessors, which was used as
9072-416: The informal term "dead bug style" for the method. The body (housing) of a DIP containing an IC chip is usually made from molded plastic or ceramic. The hermetic nature of a ceramic housing is preferred for extremely high reliability devices. However, the vast majority of DIPs are manufactured via a thermoset molding process in which an epoxy mold compound is heated and transferred under pressure to encapsulate
9184-454: The instruction in a register. It can be used for debugging (as a breakpoint instruction), for creating indexed-opcode tables as used in byte-code interpreters and can also be used to perform a time critical I/O instruction during an interrupt. An example of its utility is shown in the code below where an interrupt being serviced in a very encapsulated manner that would otherwise require many more instructions. this common piece of code during
9296-447: The interrupt that could be used by both I/O read and write commands. Similar methods could be employed in any debugging methods wanting to be used. The TMS9900 also supports the eXtended OPeration (XOP) instruction. XOP is given a number in the range 0-15 as well as a source address. When invoked, the instruction will perform a context switch through one of sixteen vectors at predefined locations in memory. The XOP instruction also places
9408-406: The late 1990s (SPARC v9 compliant processors) allow data endianness to be chosen with each individual instruction that loads from or stores to memory. The ARM architecture supports two big-endian modes, called BE-8 and BE-32 . CPUs up to ARMv5 only support BE-32 or word-invariant mode. Here any naturally aligned 32-bit access works like in little-endian mode, but access to a byte or 16-bit word
9520-443: The lead rows, and it effectively limits the number of leads which a practical DIP package may have. Even for a very small die with many bond pads (e.g. a chip with 15 inverters, requiring 32 leads), a wider DIP would still be required to accommodate the radiating leads internally. This is one of the reasons that four-sided and multiple rowed packages, such as PGAs , were introduced (around the early 1980s). A large DIP package (such as
9632-588: The length of an operand may be held in a separate field of the instruction or with the operand itself, e.g. by means of a word mark . Such an approach allows operand lengths up to 256 bytes or larger. The data types of such operands are character strings or BCD . Machines able to manipulate such data with one instruction (e.g. compare, add) include the IBM 1401 , 1410 , 1620 , System/360 , System/370 , ESA/390 , and z/Architecture , all of them of type big-endian. Numerous other orderings, generically called middle-endian or mixed-endian , are possible. The PDP-11
9744-497: The logic of networking devices and software. The word bi-endian , when said of hardware, denotes the capability of the machine to compute or pass data in either endian format. Many of these architectures can be switched via software to default to a specific endian format (usually done when the computer starts up); however, on some systems, the default endianness is selected by hardware on the motherboard and cannot be changed via software (e.g. Alpha, which runs only in big-endian mode on
9856-415: The longest-running instruction (DIV) can take up to 124 cycles (41.3 μs). The chip was packaged in a (then unusual) 64-pin, 0.9" wide DIP . The comparatively large number of pins allowed for the 15-bit (word) address bus and 16-bit data bus to be brought out on dedicated pins without the use of multiplexing (unlike e.g. the Intel 8086 CPU), keeping external memory connections simple. Contrary to
9968-408: The materials; if a single bond wire breaks or detaches, the entire IC may become useless. The top of the package covers all of this delicate assemblage without crushing the bond wires, protecting it from contamination by foreign materials. Usually, a company logo, alphanumeric codes and sometimes words are printed on top of the package to identify its manufacturer and type, when it was made (usually as
10080-456: The most common. Less common standardized row spacings include 0.4 inch (10.16 mm) (JEDEC MS-010) and 0.9 inch (22.86 mm), as well as a row spacing of 0.3 inch, 0.6 inch or 0.75 inch with a 0.07 inch (1.778 mm) lead pitch. The former Soviet Union and Eastern bloc countries used similar packages, but with a metric pin-to-pin spacing of 2.5 mm rather than 0.1 inches (2.54 mm). The number of leads
10192-401: The notch at the top, the left leads are numbered from 1 to 7 (top to bottom) and the right row of leads are numbered 8 to 14 (bottom to top). Leads are skipped on some DIP devices (e.g. segmented LED displays , relays, or devices that replace leads with a heat sink fin). The remaining leads are numbered as if all positions had leads. In addition to providing for human visual identification of
10304-403: The number of bytes in the data. An attempt to read such a file using Fortran on a system of the other endianness results in a run-time error, because the count fields are incorrect. Unicode text can optionally start with a byte order mark (BOM) to signal the endianness of the file or stream. Its code point is U+FEFF. In UTF-32 for example, a big-endian file should start with 00 00 FE FF ;
10416-621: The opcode, "Symbolic" mode is represented as Indexed mode with the register field set to 0, therefore workspace register 0 (WR0) cannot be used in Indexed mode. In less frequently used dual-operand instructions like XOR, the destination operand must be a workspace register (or workspace register pair in the case of multiply and divide instructions). Flow control is facilitated through a group of one unconditional and twelve conditional Jump instructions. Jump targets are relative to PC with an offset of -128 to +127 word addresses. For subroutine calls,
10528-416: The operation to be performed. The least-significant byte is accessed first for addition , subtraction and multiplication . The most-significant byte is accessed first for division and comparison . See § Calculation order . When character (text) strings are to be compared with one another, e.g. in order to support some mechanism like sorting , this is very frequently done lexicographically where
10640-421: The orientation of the package, the notch allows automated chip-insertion machinery to confirm correct orientation of the chip by mechanical sensing. The SOIC (Small Outline IC), a surface-mount package which is currently very popular, particularly in consumer electronics and personal computers, is essentially a shrunk version of the standard IC PDIP, the fundamental difference which makes it an SMT device being
10752-602: The package. DIP packages have been mostly displaced by surface-mount package types, which avoid the expense of drilling holes in a PCB and which allow higher density of interconnections. DIPs are commonly used for integrated circuits (ICs). Other devices in DIP packages include resistor networks, DIP switches , LED segmented and bar graph displays, and electromechanical relays . DIP connector plugs for ribbon cables are common in computers and other electronic equipment. Dallas Semiconductor manufactured integrated DIP real-time clock (RTC) modules which contained an IC chip and
10864-437: The parts is necessary, such as in test fixtures or where programmable devices must be removed for changes, a DIP socket is used. Some sockets include a zero insertion force (ZIF) mechanism. Variations of the DIP package include those with only a single row of pins, e.g. a resistor array , possibly including a heat sink tab in place of the second row of pins, and types with four rows of pins, two rows, staggered, on each side of
10976-560: The point of view of the executing programs, but they require the motherboard to perform a 64-bit swap across all 8 byte lanes to ensure that the little-endian view of things will apply to I/O devices. In the absence of this unusual motherboard hardware, device driver software must write to different addresses to undo the incomplete transformation and also must perform a normal byte swap. Some CPUs, such as many PowerPC processors intended for embedded use and almost all SPARC processors, allow per-page choice of endianness. SPARC processors since
11088-487: The program counter to a register (Branch and Link), or change the register context (Branch and Link Workspace, or XOP). The 16 hardware and 16 software interrupt vectors each consist of a pair of PC and WP values, so the register context switch is automatically performed by an interrupt as well. Stacks can be implemented atop either of these mechanisms. The TMS9900 has 69 instructions which are one, two or three words long and always word-aligned in memory. The instruction set
11200-427: The same address as either 8-bit (value = 4A), 16-bit (004A), 24-bit (00004A), or 32-bit (0000004A), all of which retain the same numeric value. Although this little-endian property is rarely used directly by high-level programmers, it is occasionally employed by code optimizers as well as by assembly language programmers. While not allowed by C++, such type punning code is allowed as "implementation-defined" by
11312-512: The size and weight of systems. DIP chips are still popular for circuit prototyping on a breadboard because of how easily they can be inserted and used there. DIPs were the mainstream of the microelectronics industry in the 1970s and 1980s. Their use has declined in the first decade of the 21st century due to the emerging new surface-mount technology (SMT) packages such as plastic leaded chip carrier (PLCC) and small-outline integrated circuit (SOIC), though DIPs continued in extensive use through
11424-471: The socket. Where devices would be frequently inserted and removed, such as in test equipment or EPROM programmers, a zero insertion force socket would be used. DIPs are also used with breadboards, a temporary mounting arrangement for education, design development or device testing. Some hobbyists, for one-off construction or permanent prototyping, use point-to-point wiring with DIPs, and their appearance when physically inverted as part of this method inspires
11536-404: The stack. The downside to this approach is that accessing these registers is more time-consuming. In a minicomputer implementation with fast memory, the effect is relatively small and the upside in a real-time or multi-tasking environment is significant as context switches are common. In other roles, like single-user microcomputers, this tradeoff may not be worthwhile. The 40-pin implementations of
11648-507: The two, big-endian is thus closer to the way the digits of numbers are written left-to-right in English, comparing digits to bytes. Bi-endianness is a feature supported by numerous computer architectures that feature switchable endianness in data fetches and stores or for instruction fetches. Other orderings are generically called middle-endian or mixed-endian . Big-endianness is the dominant ordering in networking protocols, such as in
11760-997: The value appears left-to-right, coinciding with the correct string order for reading the result ("J O H N"). But on a little-endian machine, one would see "N H O J". Middle-endian machines complicate this even further; for example, on the PDP-11 , the 32-bit value is stored as two 16-bit words "JO" "HN" in big-endian, with the characters in the 16-bit words being stored in little-endian, resulting in "O J N H". Byte-swapping consists of rearranging bytes to change endianness. Many compilers provide built-ins that are likely to be compiled into native processor instructions ( bswap / movbe ), such as __builtin_bswap32 . Software interfaces for swapping include: Some CPU instruction sets provide native support for endian byte swapping, such as bswap ( x86 — 486 and later, i960 — i960Jx and later ), and rev ( ARMv6 and later). Some compilers have built-in facilities for byte swapping. For example,
11872-420: The writings of 18th century Anglo-Irish writer Jonathan Swift . In the 1726 novel Gulliver's Travels , he portrays the conflict between sects of Lilliputians divided into those breaking the shell of a boiled egg from the big end or from the little end. By analogy, a CPU may read a digital word big end first, or little end first. Computers store information in various-sized groups of binary bits. Each group
11984-441: Was a ruggedized version. The last generation was the 99000 series, created to be the CPU of the 990/10A in 1981. The TMS99105 and 110 were sold as catalog parts. By the mid-1980s the microcomputer field was moving to 16-bit systems like the Intel 8086 and newer 16/32-bit designs like the Motorola 68000 . With no obvious future for the chip, TI's Semiconductor division turned its attention to special-purpose 32-bit processors:
12096-633: Was accessible only indirectly through the video display controller, which crippled the performance of the TI-99/4. TI developed the TM990 series of computer modules, including CPU, memory, I/O, which when plugged into a card frame could form a 16-bit minicomputer. These were typically used for process control. A microprocessor trainer was released in the form of the TM990/189. In the late 1970's John Walker and Dan Drake developed S100-bus cards based on
12208-495: Was implemented in an N-channel silicon gate MOS process, which required +5 V, −5 V and +12 V power supplies and a four-phase (non-overlapping) clock with a maximum frequency of 3 MHz (333 ns cycle), usually generated from a 48 MHz crystal using a TIM9904 (aka 74LS362) clock generator chip. The shortest instructions require eight clock cycles or 2.7 μs to complete (assuming 0 external wait cycles), many others run between 10 and 14 cycles (3.3...4.7 μs);
12320-553: Was to contain run-time support routines for the PASCAL high-level language. The instruction set for the TMS99000 family extends the 9900 instruction set while keeping compatibility. The additional instructions includes those for signed multiply and divide (first appearing in the TMS9995), long-word shift, add, and subtract; load status register, load workspace pointer, stack operations, multiprocessor support, bit manipulation. Members of
12432-513: Was unable to deliver the 8008 in time, Datapoint used a medium-scale integration equivalent, but the little-endianness was retained in most Intel designs, including the MCS-48 and the 8086 and its x86 successors, including IA-32 and x86-64 processors. The MOS Technology 6502 family (including Western Design Center 65802 and 65C816 ), the Zilog Z80 (including Z180 and eZ80 ),
12544-463: Was well-suited to automated assembly equipment; a PCB could be populated with scores or hundreds of ICs, then all the components on the circuit board could be soldered at one time on a wave soldering machine and passed on to automated testing machines, with very little human labor required. DIP packages were still large with respect to the integrated circuits within them. By the end of the 20th century, surface-mount packages allowed further reduction in
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