The task state segment ( TSS ) is a structure on x86 -based computers which holds information about a task . It is used by the operating system kernel for task management. Specifically, the following information is stored in the TSS:
66-603: All this information should be stored at specific locations within the TSS as specified in the IA-32 manuals. The TSS may reside anywhere in memory . A segment register called the task register (TR) holds a segment selector that points to a valid TSS segment descriptor which resides in the GDT (a TSS descriptor may not reside in the LDT ). Therefore, to use a TSS the following must be done by
132-405: A HPE EPYC -based supercomputer called Frontier is number one. The first ARM-based supercomputer appeared on the list in 2018 and, in recent years, non-CPU architecture co-processors ( GPGPU ) have also played a big role in performance. Intel's Xeon Phi "Knights Corner" coprocessors, which implement a subset of x86-64 with some vector extensions, are also used, along with x86-64 processors, in
198-650: A 64-bit OS. A CPU would no longer have legacy mode , and start directly in 64-bit long mode . There will be a way to switch to 5-level paging without going through the unpaged mode. Specific removed features include: Intel believes the change follows logically after the removal of the A20 gate in 2008 and the removal of 16-bit and 32-bit OS support in Intel firmware in 2020. Support for legacy operating systems would be accomplished via hardware-accelerated virtualization and/or ring 0 emulation. Advanced Performance Extensions
264-522: A TSS could be created for each task running on the computer, Linux kernel only creates one TSS for each CPU and uses them for all tasks. This approach was selected as it provides easier portability to other architectures (for example, the AMD64 architecture does not support hardware task switches), and improved performance and flexibility. Linux only uses the I/O port permission bitmap and inner stack features of
330-434: A bit more than 512 GiB of memory (about 0.195% of the 256 TiB virtual space). Intel has implemented a scheme with a 5-level page table , which allows Intel 64 processors to support a 57-bit virtual address space. Further extensions may allow full 64-bit virtual address space and physical memory with 12-bit page table descriptors and 16- or 21-bit memory offsets for 64 KiB and 2 MiB page allocation sizes;
396-774: A completely new design, the Isaiah architecture was built with support for features like the x86-64 instruction set and x86 virtualization which were unavailable on its predecessors, the VIA C7 line, while retaining their encryption extensions. In 2020, through a collaboration between AMD, Intel, Red Hat , and SUSE , three microarchitecture levels (or feature levels) on top of the x86-64 baseline were defined: x86-64-v2, x86-64-v3, and x86-64-v4. These levels define specific features that can be targeted by programmers to provide compile-time optimizations. The features exposed by each level are as follows: baseline for all x86-64 CPUs matches
462-467: A number of VIA-specific x86 extensions designed to boost efficiency in low-power appliances. It is expected that the Isaiah architecture will be twice as fast in integer performance and four times as fast in floating-point performance as the previous-generation VIA Esther at an equivalent clock speed . Power consumption is also expected to be on par with the previous-generation VIA CPUs, with thermal design power ranging from 5 W to 25 W. Being
528-406: A virtual processor running in the desired mode. Since the basic instruction set is the same, there is almost no performance penalty for executing protected mode x86 code. This is unlike Intel's IA-64 , where differences in the underlying instruction set mean that running 32-bit code must be done either in emulation of x86 (making the process slower) or with a dedicated x86 coprocessor. However, on
594-496: Is a 64-bit version of the x86 instruction set , first announced in 1999. It introduced two new modes of operation, 64-bit mode and compatibility mode, along with a new 4-level paging mode. With 64-bit mode and the new paging mode, it supports vastly larger amounts of virtual memory and physical memory than was possible on its 32-bit predecessors, allowing programs to store larger amounts of data in memory. x86-64 also expands general-purpose registers to 64-bit, and expands
660-479: Is a 2023 Intel proposal for new instructions and an additional 16 general-purpose registers. VIA Technologies introduced their first implementation of the x86-64 architecture in 2008 after five years of development by its CPU division, Centaur Technology . Codenamed "Isaiah", the 64-bit architecture was unveiled on January 24, 2008, and launched on May 29 under the VIA Nano brand name. The processor supports
726-476: Is in fact the very first one read out of the new TSS: since a hardware task switch can also switch to a completely different page table mapping, all the other fields (especially the LDTR ) are relative to the new mapping. The TSS contains a 16-bit pointer to I/O port permissions bitmap for the current task . This bitmap, usually set up by the operating system when a task is started, specifies individual ports to which
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#1732801062686792-467: Is made into a submode of legacy mode. It is the submode that 32-bit operating systems and 16-bit protected mode operating systems operate in when running on an x86-64 CPU. Real mode is the initial mode of operation when the processor is initialized, and is a submode of legacy mode. It is backwards compatible with the original Intel 8086 and Intel 8088 processors. Real mode is primarily used today by operating system bootloaders, which are required by
858-723: Is the Merom version of the Core 2 processor, which was released on July 27, 2006. None of Intel's earlier notebook CPUs ( Core Duo , Pentium M , Celeron M , Mobile Pentium 4 ) implement Intel 64. Intel's processors implementing the Intel64 architecture include the Pentium 4 F-series/5x1 series, 506, and 516, Celeron D models 3x1, 3x6, 355, 347, 352, 360, and 365 and all later Celerons , all models of Xeon since " Nocona ", all models of Pentium Dual-Core processors since " Merom-2M ",
924-518: Is the availability of 32-bit general-purpose processor registers (for example, EAX and EBX), 32-bit integer arithmetic and logical operations, 32-bit offsets within a segment in protected mode , and the translation of segmented addresses to 32-bit linear addresses. The designers took the opportunity to make other improvements as well. Some of the most significant changes (relative to the 16-bit 286 instruction set) are: X86-64 x86-64 (also known as x64 , x86_64 , AMD64 , and Intel 64 )
990-568: Is used by 64-bit operating systems. Under a 64-bit operating system, 64-bit programs run under 64-bit mode, and 32-bit and 16-bit protected mode applications (that do not need to use either real mode or virtual 8086 mode in order to execute at any time) run under compatibility mode. Real-mode programs and programs that use virtual 8086 mode at any time cannot be run in long mode unless those modes are emulated in software. However, such programs may be started from an operating system running in long mode on processors supporting VT-x or AMD-V by creating
1056-400: Is used. (Each register can store one or two double-precision numbers or one to four single-precision numbers, or various integer formats.) In 64-bit mode, instructions are modified to support 64-bit operands and 64-bit addressing mode . The compatibility mode defined in the architecture allows 16-bit and 32-bit user applications to run unmodified, coexisting with 64-bit applications if
1122-525: The 80386 microprocessor in 1985. IA-32 is the first incarnation of x86 that supports 32-bit computing; as a result, the "IA-32" term may be used as a metonym to refer to all x86 versions that support 32-bit computing. Within various programming language directives, IA-32 is still sometimes referred to as the "i386" architecture. In some other contexts, certain iterations of the IA-32 ISA are sometimes labelled i486 , i586 and i686 , referring to
1188-480: The 8086 , as x86 processors supporting protected mode have done since the 80286 . The original specification, created by AMD and released in 2000, has been implemented by AMD, Intel , and VIA . The AMD K8 microarchitecture , in the Opteron and Athlon 64 processors, was the first to implement it. This was the first significant addition to the x86 architecture designed by a company other than Intel. Intel
1254-673: The Atom 230, 330, D410, D425, D510, D525, N450, N455, N470, N475, N550, N570, N2600 and N2800, all versions of the Pentium D , Pentium Extreme Edition , Core 2 , Core i9 , Core i7 , Core i5 , and Core i3 processors, and the Xeon Phi 7200 series processors. X86S is a simplification of x86-64 proposed by Intel in May 2023 for their "Intel 64" products. The new architecture would remove support for 16-bit and 32-bit operating systems, while 32-bit programs will still run under
1320-514: The Tianhe-2 supercomputer. The following operating systems and releases support the x86-64 architecture in long mode . Preliminary infrastructure work was started in February 2004 for a x86-64 port. This development later stalled. Development started again during July 2007 and continued during Google Summer of Code 2008 and SoC 2009. The first official release to contain x86-64 support
1386-526: The Windows NT family) take the higher-addressed half of the address space (named kernel space ) for themselves and leave the lower-addressed half ( user space ) for application code, user mode stacks, heaps, and other data regions. The "canonical address" design ensures that every AMD64 compliant implementation has, in effect, two memory halves: the lower half starts at 00000000'00000000 and "grows upwards" as more virtual address bits become available, while
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#17328010626861452-571: The x86 CPU will look in the TSS for SS0 and ESP0 and load their values into SS and ESP respectively. This allows for the kernel to use a different stack than the user program, and also have this stack be unique for each user program. A new feature introduced in the AMD64 extensions is called the Interrupt Stack Table (IST), which also resides in the TSS and contains logical (segment+offset) stack pointers. If an interrupt descriptor table specifies an IST entry to use (there are 7),
1518-573: The "AMD64" nomenclature is used. These are used as synonyms with the x86-64-vX nomenclature and are thus functionally identical. E.g. the Go language documentation or the Fedora linux distribution. All levels include features found in the previous levels. Instruction set extensions not concerned with general-purpose computation, including AES-NI and RDRAND , are excluded from the level requirements. Although nearly identical, there are some differences between
1584-405: The 2013 Intel Haswell architecture, excluding Intel-specific instructions Intel Skylake and newer Intel "big" cores (AVX512 enabled models only) AMD Zen 4 and newer AMD cores features match the 2017 Intel Skylake-X architecture, excluding Intel-specific instructions The x86-64 microarchitecture feature levels can also be found as AMD64-v1, AMD64-v2 .. or AMD64_v1 .. in settings where
1650-474: The 64-bit operating system supports them. As the full x86 16-bit and 32-bit instruction sets remain implemented in hardware without any intervening emulation, these older executables can run with little or no performance penalty, while newer or modified applications can take advantage of new features of the processor design to achieve performance improvements. Also, a processor supporting x86-64 still powers on in real mode for full backward compatibility with
1716-405: The 64-bit registers. Legacy mode is the mode that the processor is in when it is not in long mode. In this mode, the processor acts like an older x86 processor, and only 16-bit and 32-bit code can be executed. Legacy mode allows for a maximum of 32 bit virtual addressing which limits the virtual address space to 4 GiB. 64-bit programs cannot be run from legacy mode. Protected mode
1782-452: The AMD64 architecture include Opteron , Athlon 64 , Athlon 64 X2 , Athlon 64 FX , Athlon II (followed by "X2", "X3", or "X4" to indicate the number of cores, and XLT models), Turion 64 , Turion 64 X2 , Sempron ("Palermo" E6 stepping and all "Manila" models), Phenom (followed by "X3" or "X4" to indicate the number of cores), Phenom II (followed by "X2", "X3", "X4" or "X6" to indicate
1848-483: The AMD64 architecture was positioned by AMD from the beginning as an evolutionary way to add 64-bit computing capabilities to the existing x86 architecture while supporting legacy 32-bit x86 code , as opposed to Intel's approach of creating an entirely new, completely x86-incompatible 64-bit architecture with IA-64. The first AMD64-based processor, the Opteron , was released in April 2003. AMD's processors implementing
1914-611: The OEM market as the Pentium 4, model F. The E0 revision also adds eXecute Disable (XD) (Intel's name for the NX bit ) to Intel 64, and has been included in then current Xeon code-named Irwindale . Intel's official launch of Intel 64 (under the name EM64T at that time) in mainstream desktop processors was the N0 stepping Prescott-2M. The first Intel mobile processor implementing Intel 64
1980-437: The TSS can still be used in a machine running in the 64 bit extended modes. In these modes the TSS is still useful as it stores: Also, the task register is expanded in these modes to be able to hold a 64-bit base address. IA-32 IA-32 (short for " Intel Architecture, 32-bit ", commonly called i386 ) is the 32-bit version of the x86 instruction set architecture , designed by Intel and first implemented in
2046-498: The TSS into the appropriate registers. Note that some modern operating systems such as Windows and Linux do not use these fields in the TSS as they implement software task switching. Note that during a hardware task switch, certain fields of the old TSS are updated with the CPU's current register contents before the values from the new TSS are read. Thus some TSS fields are read/write, while others are read-only: The PDBR field
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2112-502: The TSS to see if that program can access the specific port(s) in the IN or OUT instruction. If (all the) relevant bit(s) in the I/O port permissions bitmap is/are clear, the program is allowed access to the port(s), and the instruction is allowed to execute. If (any of) the relevant bit(s) is/are set - or if (any of) the bit(s) is/are past the TSS’ segment limit - the program does not have access and
2178-563: The TSS; the other features are only needed for hardware task switches, which the Linux kernel does not use. The x86 exception vector 10 is called the Invalid TSS exception (#TS). It is issued by the processor whenever something goes wrong with the TSS access. For example, if an interrupt happens in CPL=3 and is transferring control to CPL=0, the TSS is used to extract SS0 and ESP0/RSP0 for
2244-431: The amount of RAM that is usable or supported. Details on this point are given in the " Operating system compatibility and characteristics " section of this article. The architecture has two primary modes of operation: long mode and legacy mode. Long mode is the architecture's intended primary mode of operation; it is a combination of the processor's native 64-bit mode and a combined 32-bit and 16-bit compatibility mode. It
2310-471: The appearance of 64-bit extensions for the x86 architecture enabled 64-bit x86 processors by AMD and Intel to replace most RISC processor architectures previously used in such systems (including PA-RISC , SPARC , Alpha and others), as well as 32-bit x86, even though Intel itself initially tried unsuccessfully to replace x86 with a new incompatible 64-bit architecture in the Itanium processor. As of 2023 ,
2376-529: The architecture to configure virtual memory details before transitioning to higher modes. This mode is also used by any operating system that needs to communicate with the system firmware with a traditional BIOS -style interface. Intel 64 is Intel's implementation of x86-64, used and implemented in various processors made by Intel. Historically, AMD has developed and produced processors with instruction sets patterned after Intel's original designs, but with x86-64, roles were reversed: Intel found itself in
2442-811: The common capabilities between the 2003 AMD AMD64 and the 2004 Intel EM64T initial implementations in the AMD K8 and the Intel Prescott processor families Intel Nehalem and newer Intel "big" cores Intel (Atom) Silvermont and newer Intel "small" cores AMD Bulldozer and newer AMD "big" cores AMD Jaguar VIA Nano and Eden "C" features match the 2008 Intel Nehalem architecture, excluding Intel-specific instructions Intel Haswell and newer Intel "big" cores (AVX2 enabled models only) Intel (Atom) Gracemont and newer Intel "small" cores AMD Excavator and newer AMD "big" cores QEMU emulation (as of version 7.2) features match
2508-593: The contemporary prevalence of x86-64, as of today, IA-32 protected mode versions of many modern operating systems are still maintained, e.g. Microsoft Windows (until Windows 10 ), Windows Server (until Windows Server 2008 ) and the Debian Linux distribution. In spite of IA-32's name (and causing some potential confusion), the 64-bit evolution of x86 that originated out of AMD would not be known as "IA-64", that name instead belonging to Intel's Itanium architecture . The primary defining characteristic of IA-32
2574-450: The discontinued Intel Itanium architecture (formerly IA-64 ), which was originally intended to replace the x86 architecture. x86-64 and Itanium are not compatible on the native instruction set level, and operating systems and applications compiled for one architecture cannot be run on the other natively. AMD64 (also variously referred to by AMD in their literature and documentation as “AMD 64-bit Technology” and “AMD x86-64 Architecture”)
2640-448: The first implementations of the architecture, only the least significant 48 bits of a virtual address would actually be used in address translation ( page table lookup). In addition, the AMD specification requires that the most significant 16 bits of any virtual address, bits 48 through 63, must be copies of bit 47 (in a manner akin to sign extension ). If this requirement is not met,
2706-551: The full 256 TiB; they were restricted to just 8 TiB of user space and 8 TiB of kernel space. Windows did not support the entire 48-bit address space until Windows 8.1 , which was released in October 2013. The 64-bit addressing mode (" long mode ") is a superset of Physical Address Extensions (PAE); because of this, page sizes may be 4 KiB (2 bytes) or 2 MiB (2 bytes). Long mode also supports page sizes of 1 GiB (2 bytes). Rather than
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2772-589: The hardware will do an I/O privilege level (IOPL) check to see if the program has access to all I/O ports. If the Current Privilege Level (CPL) of the program is numerically greater than the I/O Privilege level (IOPL) (the program is less-privileged than what the IOPL specifies), the program does not have I/O port access to all ports. The hardware will then check the I/O permissions bitmap in
2838-433: The higher half is "docked" to the top of the address space and grows downwards. Also, enforcing the "canonical form" of addresses by checking the unused address bits prevents their use by the operating system in tagged pointers as flags, privilege markers, etc., as such use could become problematic when the architecture is extended to implement more virtual address bits. The first versions of Windows for x64 did not even use
2904-636: The instruction supersets offered by the 80486 , the P5 and the P6 microarchitectures respectively. These updates offered numerous additions alongside the base IA-32 set including floating-point capabilities and the MMX extensions . Intel was historically the largest manufacturer of IA-32 processors, with the second biggest supplier having been AMD . During the 1990s, VIA , Transmeta and other chip manufacturers also produced IA-32 compatible processors (e.g. WinChip ). In
2970-428: The interrupt or exception occurred. The processor then set the registers, including SS:ESP, to a known value specified in the TSS and saved the selector to the previous TSS. The problem here is that hardware task switching is not supported on AMD64. This is a 16-bit selector which allows linking this TSS with the previous one. This is only used for hardware task switching. See the IA-32 manuals for details. Although
3036-466: The modern era, Intel still produced IA-32 processors under the Intel Quark microcontroller platform until 2019; however, since the 2000s, the majority of manufacturers (Intel included) moved almost exclusively to implementing CPUs based on the 64-bit variant of x86, x86-64 . x86-64, by specification, offers legacy operating modes that operate on the IA-32 ISA for backwards compatibility. Even given
3102-577: The name Intel 64 for its implementation, paralleling AMD's use of the name AMD64. The first processor to implement Intel 64 was the multi-socket processor Xeon code-named Nocona in June 2004. In contrast, the initial Prescott chips (February 2004) did not enable this feature. Intel subsequently began selling Intel 64-enabled Pentium 4s using the E0 revision of the Prescott core, being sold on
3168-536: The number of cores), FX , Fusion/APU and Ryzen / Epyc . The primary defining characteristic of AMD64 is the availability of 64-bit general-purpose processor registers (for example, rax ), 64-bit integer arithmetic and logical operations, and 64-bit virtual addresses . The designers took the opportunity to make other improvements as well. Notable changes in the 64-bit extensions include: Although virtual addresses are 64 bits wide in 64-bit mode, current implementations (and all chips that are known to be in
3234-404: The number of them from 8 (some of which had limited or fixed functionality, e.g. for stack management) to 16 (fully general), and provides numerous other enhancements. Floating-point arithmetic is supported via mandatory SSE2 -like instructions , and x87 / MMX style registers are generally not used (but still available even in 64-bit mode); instead, a set of 16 vector registers , 128 bits each,
3300-471: The operating system kernel: For security purposes, the TSS should be placed in memory that is accessible only to the kernel . The TR register is a 16-bit register which holds a segment selector for the TSS. It may be loaded through the LTR instruction. LTR is a privileged instruction and acts in a manner similar to other segment register loads. The task register has two parts: a portion visible and accessible by
3366-568: The page table entry would be expanded to 128 bits to support additional hardware flags for page size and virtual address space size. The operating system can also limit the virtual address space. Details, where applicable, are given in the " Operating system compatibility and characteristics " section. Current AMD64 processors support a physical address space of up to 2 bytes of RAM, or 256 TiB . However, as of 2020 , there were no known x86-64 motherboards that support 256 TiB of RAM. The operating system may place additional limits on
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#17328010626863432-488: The planning stages) do not allow the entire virtual address space of 2 bytes (16 EiB ) to be used. This would be approximately four billion times the size of the virtual address space on 32-bit machines. Most operating systems and applications will not need such a large address space for the foreseeable future, so implementing such wide virtual addresses would simply increase the complexity and cost of address translation with no real benefit. AMD, therefore, decided that, in
3498-573: The position of adopting the ISA that AMD created as an extension to Intel's own x86 processor line. Intel's project was originally codenamed Yamhill (after the Yamhill River in Oregon's Willamette Valley). After several years of denying its existence, Intel announced at the February 2004 IDF that the project was indeed underway. Intel's chairman at the time, Craig Barrett , admitted that this
3564-429: The processor generates a general protection fault . This feature allows operating systems to grant selective port access to user programs. The TSS contains 6 fields for specifying the new stack pointer when a privilege level change happens. The field SS0 contains the stack segment selector for CPL=0, and the field ESP0/RSP0 contains the new ESP/RSP value for CPL=0. When an interrupt happens in protected (32-bit) mode,
3630-501: The processor will load the new stack from the IST instead. This allows known-good stacks to be used in case of serious errors ( NMI or Double fault for example). Previously, the entry for the exception or interrupt in the IDT pointed to a task gate, causing the processor to switch to the task that is pointed by the task gate. The original register values were saved in the TSS current at the time
3696-511: The processor will raise an exception. Addresses complying with this rule are referred to as "canonical form." Canonical form addresses run from 0 through 00007FFF'FFFFFFFF, and from FFFF8000'00000000 through FFFFFFFF'FFFFFFFF, for a total of 256 TiB of usable virtual address space. This is still 65,536 times larger than the virtual 4 GiB address space of 32-bit machines. This feature eases later scalability to true 64-bit addressing. Many operating systems (including, but not limited to,
3762-553: The program should have access. The I/O bitmap is a bit array of port access permissions; if the program has permission to access a port, a "0" is stored at the corresponding bit index, and if the program does not have permission, a "1" is stored there. If the TSS’ segment limit is less than the full bitmap, all missing bits are assumed to be "1". The feature operates as follows: when a program issues an x86 I/O port instruction such as IN or OUT (see x86 instruction listings - and note that there are byte-, word- and dword-length versions),
3828-410: The programmer and an invisible one that is automatically loaded from the TSS descriptor. The TSS may contain saved values of all the x86 registers. This is used for task switching . The operating system may load the TSS with the values of the registers that the new task needs and after executing a hardware task switch (such as with an IRET instruction) the x86 CPU will load the saved values from
3894-405: The stack switch. If the task register holds a bad TSS selector, a #TS fault will be generated. The Invalid TSS exception should never happen during normal operating system operation and is always related to kernel bugs or hardware failure. For more details on TSS exceptions, see Volume 3a, Chapter 6 of the IA-32 manual. The x86-64 architecture does not support hardware task switches. However
3960-450: The three-level page table system used by systems in PAE mode, systems running in long mode use four levels of page table: PAE's Page-Directory Pointer Table is extended from four entries to 512, and an additional Page-Map Level 4 (PML4) Table is added, containing 512 entries in 48-bit implementations. A full mapping hierarchy of 4 KiB pages for the whole 48-bit space would take
4026-491: The two instruction sets in the semantics of a few seldom used machine instructions (or situations), which are mainly used for system programming . Compilers generally produce executables (i.e. machine code ) that avoid any differences, at least for ordinary application programs . This is therefore of interest mainly to developers of compilers, operating systems and similar, which must deal with individual and special system instructions. In supercomputers tracked by TOP500 ,
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#17328010626864092-410: The x86-64 platform, many x86 applications could benefit from a 64-bit recompile , due to the additional registers in 64-bit code and guaranteed SSE2-based FPU support, which a compiler can use for optimization. However, applications that regularly handle integers wider than 32 bits, such as cryptographic algorithms, will need a rewrite of the code handling the huge integers in order to take advantage of
4158-534: Was created as an alternative to the radically different IA-64 architecture designed by Intel and Hewlett-Packard , which was backward-incompatible with IA-32 , the 32-bit version of the x86 architecture. AMD originally announced AMD64 in 1999 with a full specification available in August 2000. As AMD was never invited to be a contributing party for the IA-64 architecture and any kind of licensing seemed unlikely,
4224-425: Was forced to follow suit and introduced a modified NetBurst family which was software-compatible with AMD's specification. VIA Technologies introduced x86-64 in their VIA Isaiah architecture, with the VIA Nano . The x86-64 architecture was quickly adopted for desktop and laptop personal computers and servers which were commonly configured for 16 GiB ( gibibytes ) of memory or more. It has effectively replaced
4290-528: Was one of their worst-kept secrets. Intel's name for this instruction set has changed several times. The name used at the IDF was CT (presumably for Clackamas Technology , another codename from an Oregon river ); within weeks they began referring to it as IA-32e (for IA-32 extensions) and in March 2004 unveiled the "official" name EM64T (Extended Memory 64 Technology). In late 2006 Intel began instead using
4356-481: Was version 2.4. FreeBSD first added x86-64 support under the name "amd64" as an experimental architecture in 5.1-RELEASE in June 2003. It was included as a standard distribution architecture as of 5.2-RELEASE in January 2004. Since then, FreeBSD has designated it as a Tier 1 platform. The 6.0-RELEASE version cleaned up some quirks with running x86 executables under amd64, and most drivers work just as they do on
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