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69-487: TI began as a division of Geophysical Service Incorporated (GSI), a company that performed seismic surveys for oil exploration companies. GSI was now a subsidiary of TI, and TI wanted to apply the latest computer technology to the processing and analysis of seismic datasets. The ASC project started as the Advanced Seismic Computer . As the project developed, TI decided to expand its scope. "Seismic"

138-438: A cache controller, offering high-speed access to a semiconductor -based memory for the eight processor ports, and handling all communications to the 24-bit address space in main memory. The MCU was designed to operate asynchronously, allowing it to work at a variety of speeds and scale across a number of performance points. For instance, main memory could be constructed out of slower but less expensive core memory , although this

207-577: A preferred area of main storage. This is accomplished by a special SYSEVENT in MVS/370 through z/OS operating systems, wherein the application is, first, swapped- out from wherever it may be, presumably from a non-preferred area, to swap and page external storage, and is, second, swapped- in to a preferred area (SYSEVENT TRANSWAP). Thereafter, the application may be marked non-swappable by another special SYSEVENT (SYSEVENT DONTSWAP). Whenever such an application terminates, whether normally or abnormally,

276-631: A PP used synchronous instructions to transfer data between the channel and either the A register or PP memory. SCSI introduced in 1981 as a low cost channel equivalent to the IBM Block Multiplexer Channel is now ubiquitous in the form of the Fibre Channel Protocol and Serial Attached SCSI . Modern computers may have channels in the form of bus mastering peripheral devices, such as PCI direct memory access (DMA) devices. The rationale for these devices

345-545: A Transfer-in-Channel (TIC) CCW is executed, or a CCW is executed without chaining indicated. Command chaining tells the channel that the next CCW contains a new command. Data chaining indicates that the next CCW contains the address of additional data for the same command, allowing, for example, portions of one record to be written from or read to multiple data areas in storage (gather-writing and scatter-reading). Channel programs can modify their own operation during execution based on data read. For example, self modification

414-507: A bit-reverse instruction that was intended to speed up the calculation of fast Fourier transforms (FFTs). By the time the ASC was in production, better FFT algorithms had been developed that did not require this operation. TI offered a bounty to the first person to come up with a valid use for this instruction, but was never collected. When ASC machines first became available in the early 1970s, they outperformed almost all other machines, including

483-426: A device at a time. A selector channel supports one high-speed operation, transferring a block of data at a time. A block multiplexer supports a number of logically concurrent channel programs, but only one high-speed data transfer at a time. Channels may also differ in how they associate peripheral devices with storage buffers. In UNIVAC terminology, a channel may either be internally specified index (ISI), with

552-470: A dynamically programmable capability, is available within such channel programs, by use of the "status modifier" channel flag and the "transfer-in-channel" CCW. IBM CCWs are chained to form the channel program. Bits in the CCW indicates that the following location in storage contains a CCW that is part of the same channel program. The channel program normally executes sequential CCWs until an exception occurs,

621-489: A finite state machine. It is used to initiate an I/O operation, such as "read", "write" or "sense", on a channel-attached device. On system architectures that implement channel I/O, typically all devices are connected by channels, and so all I/O requires the use of CCWs. CCWs are organized into channel programs by the operating system, and I/O subroutine, a utility program, or by standalone software (such as test and diagnostic programs). A limited "branching" capability, hence

690-493: A major problem on modern SIMD designs as well, which is why considerable effort has been put into increasing memory throughput in modern computer designs (although largely unsuccessfully). In the ASC this was improved somewhat with a lookahead unit that predicted upcoming memory accesses and loaded them into the scalar registers invisibly, using a memory interface in the CPU called the memory buffer unit (MBU). The "Peripheral Processor"

759-468: A process generally called a "shifting channel state processor" (a type of barrel processor ), which implemented a specialized finite state machine (FSM). Each CPU cycle, every 32 nanoseconds in the 470V/6 and /5 and every 26 nanoseconds in the 470V/7 and /8, the "C-unit" read the complete status of next channel in priority sequence and its I/O Channel in-tags . The necessary actions defined by that channel's last state and its in-tags were performed: data

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828-452: A single box), and the IBM 2880 Block multiplexor channel (one or two block multiplexor channels in a single box). On the 303x processor complexes, the channels were implemented in independent channel directors in the same cabinet as the CPU, with each channel director implementing a group of channels. Much later, the channels were implemented as an on-board processor residing in the same box as

897-552: A single buffer and device active at a time, or externally specified index (ESI), with the device selecting which buffer to use. In the IBM System/360 and subsequent architectures, a channel program is a sequence of channel command words (CCWs) that are executed by the I/O channel subsystem. A channel program consists of one or more channel command words. The operating system signals the I/O channel subsystem to begin executing

966-594: A standard part of most mainframe designs and primary advantage mainframes have over smaller, faster, personal computers and network computing. The 1965 CDC 6600 supercomputer utilized 10 logically independent computers called peripheral processors (PPs) and 12 simple I/O channels for this role. PPs were a modified version of CDC's first personal computers, the 12-bit CDC 160 and 160A. The operating system initially resided and executed in PP0. The channels had no direct access to memory and could not cause interrupts; software on

1035-500: A third party or government. Channel controller In computing , channel I/O is a high-performance input/output (I/O) architecture that is implemented in various forms on a number of computer architectures, especially on mainframe computers . In the past, channels were generally implemented with custom devices, variously named channel , I/O processor , I/O controller , I/O synchronizer , or DMA controller . Many I/O tasks can be complex and require logic to be applied to

1104-517: Is always contained on cylinder X'0000', track X'0000', and block X'03' (80 bytes). The volume label always points to the VTOC, with a pointer of the form HHHH (that is, the VTOC must reside within the first 65,536 tracks). The VTOC's Format 4 DSCB defines the extent (size) of the VTOC, so the volume label only needs a pointer to the first track in the VTOC's extent, and as the Format 4 DSCB, which describes

1173-450: Is assumed, so the implied CCW at location 0 falls through to the continuation of the channel program at locations 8 and 16, and possibly elsewhere should one of those CCWs be a transfer-in-channel (TIC). To load a system, the implied Read IPL CCW reads the first block of the selected IPL device into the 24-byte data area at location 0, the channel continues with the second and third double words, which are CCWs, and this channel program loads

1242-401: Is correct for unblocked records (one record per block). For blocked records (more than one record per block), the recorded key must be the same as the highest key within that block (and the records must be in key sequence), and the following channel program would be utilized: If the dataset is allocated in tracks, and the end of the track is reached without the requested record being found

1311-433: Is device-independent. It is capable of IPL-ing from a card deck, from a magnetic tape, or from a direct access storage device , (DASD), e.g., disk, drum. The Read IPL (X'02') command, which is simulated by the CPU, is a Read EBCDIC Select Stacker 1 read command on the card reader and a Read command on tape media (which are inherently sequential access in nature), but a special Read-IPL command on DASD. DASD controllers accept

1380-805: Is the same as for the original channel controllers, namely off-loading transfer, interrupts, and context switching from the main CPU. Channel controllers have been made as small as single-chip designs with multiple channels on them, used in the NeXT computers for instance. The reference implementation of channel I/O is that of the IBM System/360 family of mainframes and its successors, but similar implementations have been adopted by IBM on other lines, e.g., 1410 and 7010 , 7030 , and by other mainframe vendors, such as Control Data , Bull ( General Electric / Honeywell ) and Unisys . Computer systems that use channel I/O have special hardware components that handle all input/output operations in their entirety independently of

1449-500: Is to move away from such PCIs, except where unavoidable. The first use of channel I/O was with the IBM 709 vacuum tube mainframe in 1957, whose Model 766 Data Synchronizer was the first channel controller. The 709's transistorized successor, the IBM 7090 , had two to eight 6-bit channels (the 7607) and a channel multiplexor (the 7606) which could control up to eight channels. The 7090 and 7094 could also have up to eight 8-bit channels with

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1518-466: Is used extensively in OS/360 ISAM . The following example reads a disk record identified by a recorded key . The track containing the record and the desired value of the key is known. The device control unit will search the track to find the requested record. In this example <> indicate that the channel program contains the storage address of the specified field. The TIC (transfer in

1587-518: The CDC STAR-100 , and under certain conditions matched that of the one-off ILLIAC IV . However, only seven had been installed when the Cray-1 was announced in 1975. The Cray-1 dedicated almost all of its design to sustained high-speed access to memory, including over one million 64-bit words of semiconductor memory and a cycle time that was one-fifth that of the ASC (12.5 ns). Although the ASC

1656-493: The ILLIAC IV supercomputer. The CPU had an extremely advanced architecture and organization for its era, supporting microcoded arithmetic and mathematical instructions that operated on scalars, vectors, or matrices. The vector processing facilities had a memory-to-memory architecture; where the vector operands were read from, and the resulting vector written to, memory. The CPU could have one, two, or four vector lanes, allowing

1725-766: The "C-Unit" for all channels which were emulated by this FSM. Channels could be easily reconfigured to the customer's choice of selector, byte multiplexor) or block multiplexor channel, without any significant restrictions by using maintenance console commands. "Two-byte interface" was also supported as was "Data-In/Data-Out" and other high-performance IBM channel options. Built-in channel-to-channel adapters were also offered, called CCAs in Amdahl-speak, but called CTCs or CTCAs in IBM-speak. A real game-changer, and this forced IBM to redesign its mainframes to provide similar channel capability and flexibility. IBM's initial response

1794-581: The 7909. While IBM used data channel commands on some of its computers, and allowed command chaining on, e.g., the 7090, most other vendors used channels that dealt with single records. However, some systems, e.g., GE-600 series , had more sophisticated I/O architectures. Later, the IBM System/360 and System/370 families of computer offered channel I/O on all models. For the lower-end System/360 Models 50 and below and System/370 Model 158 and below, channels were implemented in microcode on

1863-767: The Army Corps of Engineers in Vicksburg, Mississippi, for dam stress analysis. ASC #4 was used by NOAA at Princeton University for developing weather forecasting models. ASC systems #5 and #6 were installed at TI's main plant in Austin and also used by GSI for seismic data processing. ASC #7 went to the Naval Research Lab in Washington, D.C. for plasma physics studies. Geophysical Service Incorporated Geophysical Service Inc. (often abbreviated GSI )

1932-1112: The CPU from the overhead of starting, monitoring, and managing individual I/O operations. The specialized channel hardware, in turn, is dedicated to I/O and can carry it out more efficiently than the CPU (and entirely in parallel with the CPU). Channel I/O is not unlike the Direct Memory Access (DMA) of microcomputers, only more complex and advanced. On large mainframe computer systems, CPUs are only one of several powerful hardware components that work in parallel. Special input/output controllers (the exact names of which vary from one manufacturer to another) handle I/O exclusively, and these, in turn, are connected to hardware channels that also are dedicated to input and output. There may be several CPUs and several I/O processors. The overall architecture optimizes input/output performance without degrading pure CPU performance. Since most real-world applications of mainframe systems are heavily I/O-intensive business applications, this architecture helps provide

2001-402: The CPU to produce one to four vector results every cycle, depending on the number of vector lanes installed. The vector lanes were also used for scalar instructions, and each lane could keep up to 12 scalar instructions in-flight simultaneously. The CPU, with four lanes, allowed up to 36 instructions in total across the entire CPU. The processor had forty-eight 32-bit registers, a huge number for

2070-469: The CPU, and the CPU itself operated in one of two modes, either "CPU Mode" or "Channel Mode", with the channel mode 'stealing' cycles from the CPU mode. For larger IBM System/360 and System/370 computers the channels were still bulky and expensive separate components, such as the IBM 2860 Selector channel (one to three selector channels in a single box), the IBM 2870 Byte multiplexor channel (one multiplexer channel, and, optionally, one selector subchannel in

2139-550: The CPU, generally referred to as a "channel processor", and which was usually a RISC processor, but which could be a System/390 microprocessor with special microcode as in IBM's CMOS mainframes. Amdahl Corporation's hardware implementation of System/370 compatible channels was quite different. A single internal unit, called the "C-Unit", supported up to sixteen channels using the very same hardware for all supported channels. Two internal "C-Units" were possible, supporting up to 32 total channels. Each "C-Unit" independently performed

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2208-559: The I/O hardware signals an interrupt to the CPU. A channel is an independent hardware component that coordinates all I/O to a set of controllers or devices. It is not merely a medium of communication, despite the name; it is a programmable device that handles all details of I/O after being given a list of I/O operations to carry out (the channel program). Each channel may support one or more controllers and/or devices, but each channel program may only be directed at one of those connected devices. A channel program contains lists of commands to

2277-485: The I/O operation without interrupting the application program. On most systems channels operate using real (or physical) addresses , while the channel programs are built using virtual addresses . The operating system is responsible for translating these channel programs before executing them, and for this particular purpose the Input/Output Supervisor (IOS) has a special fast fix function which

2346-693: The Labrador coast for British Petroleum, sank off St. Anthony, Newfoundland, in the Strait of Belle Isle, resulting in the loss of 13 lives. In 1992, Davey Einarsson, a longtime executive of the original GSI, purchased the proprietary rights to GSI’s speculative data in the Canadian offshore, launching the new GSI in Calgary. Paul Einarsson is the COO and Chairman of weener Geophysical Service Incorporated. He joined

2415-459: The VTOC, is always the very first DSCB in the VTOC, HHHH also points to the Format 4 DSCB. If an attempt is made to IPL from a device that was not initialized with IPL Text, the system simply enters a wait state. The DASD (direct access storage device) initialization program, IBCDASDI, or the DASD initialization application, ICKDSF, places a wait state PSW and a dummy CCW string in the 24 bytes, should

2484-647: The X'02' command, seek to cylinder X'0000' head X'0000', skip to the index point (i.e., just past the track descriptor record (R0)) and then treat the Read IPL command as if it were a Read Data (X'06') command. Without this special DASD controller behavior, device-independent IPL would not be possible. On a DASD, the IPL Text is contained on cylinder X'0000', track X'0000', and record X'01' (24 bytes), and cylinder X'0000', track X'0000', and record X'02' (fairly large, certainly somewhat more than 3,000 bytes). The volume label

2553-473: The cage, below the raised floor as cables of the thickness of a thumb and directly connect to channel interfaces on bigger devices like tape subsystems, direct access storage devices (DASDs), terminal concentrators and other ESA/390 systems. Channels differ in the number and type of concurrent I/O operations they support. In IBM terminology, a multiplexer channel supports a number of concurrent interleaved slow-speed operations, each transferring one byte from

2622-399: The central processor as their working storage, while on other systems it is present in the channel hardware. Typically, there are standard interfaces between channels and external peripheral devices, and multiple channels can operate concurrently. A CPU typically designates a block of storage as, or sends, a relatively small channel program to the channel in order to handle I/O tasks, which

2691-421: The channel and controller can, in many cases, complete without further intervention from the CPU (exception: those channel programs which utilize 'program controlled interrupts', PCIs, to facilitate program loading, demand paging and other essential system tasks). When I/O transfer is complete or an error is detected, the controller typically communicates with the CPU through the channel using an interrupt . Since

2760-482: The channel itself and to the controller and device to which it is directed. Once the operating system has prepared a complete list of channel commands, it executes a single I/O machine instruction to initiate the channel program; the channel thereafter assumes control of the I/O operations until they are completed. It is possible to develop very complex channel programs, including testing of data and conditional branching within that channel program. This flexibility frees

2829-667: The channel normally has direct access to the main memory, it is also often referred to as a direct memory access (DMA) controller. In the most recent implementations, the channel program is initiated and the channel processor performs all required processing until either an ending condition or a program controlled interrupt (PCI). This eliminates much of the CPU—Channel interaction and greatly improves overall system performance. The channel may report several different types of ending conditions, which may be unambiguously normal, may unambiguously indicate an error or whose meaning may depend on

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2898-402: The channel program terminates and returns a "no record found" status indication. Similarly, if the dataset is allocated in cylinders, and the end of the cylinder is reached without the requested record being found the channel program terminates and returns a "no record found" status indication. In some cases, the system software has the option of updating the track or cylinder number and redriving

2967-409: The channel program with an SSCH (start sub-channel) instruction. The central processor is then free to proceed with non-I/O instructions until interrupted. When the channel operations are complete, the channel interrupts the central processor with an I/O interruption. In earlier models of the IBM mainframe line, the channel unit was an identifiable component, one for each channel. In modern mainframes,

3036-576: The channel) will cause the channel program to branch to the SEARCH command until a record with a matching key (or the end of the track) is encountered. When a record with a matching key is found the DASD controller will include Status Modifier in the channel status, causing the channel to skip the TIC CCW; thus the channel program will not branch and the channel will execute the READ command. The above example

3105-525: The channels are implemented using an independent RISC processor, the channel processor, one for all channels. IBM System/370 Extended Architecture and its successors replaced the earlier SIO ( start I/O ) and SIOF ( start I/O fast release ) machine instructions (System/360 and early System/370) with the SSCH ( start sub-channel ) instruction (ESA/370 and successors). Channel I/O provides considerable economies in input/output. For example, on IBM's Linux on IBM Z ,

3174-703: The company in 1997. GSI is the largest owner of marine seismic data in Canada, with its head office located in Calgary, Alberta. In 2013, GSI was involved in several cases of litigation for damages over disclosure of its confidential seismic data. The court challenges included litigation with the Canada-Newfoundland Offshore Petroleum Board, the Canada-Nova Scotia Offshore Petroleum Board, and companies that had obtained GSI data from

3243-433: The company was renamed Texas Instruments (TI) with GSI as a division. GSI was later sold by TI, repurchased, and finally sold again to Halliburton in 1988. Halliburton also acquired GeoSource, a competing geophysical contractor (formerly Petty-Ray Geophysical), and attempted to merge the two companies. However, the rivalry between the two entities endured and the merged entity known as Halliburton Geophysical Services (HGS)

3312-406: The context and the results of a subsequent sense operation. In some systems an I/O controller can request an automatic retry of some operations without CPU intervention. In earlier implementations, any error, no matter how small, required CPU intervention, and the overhead was, consequently, much higher. A program-controlled interruption (PCI) is still used by certain legacy operations, but the trend

3381-455: The data to convert formats and other similar duties. In these situations, the simplest solution is to ask the CPU to handle the logic, but because I/O devices are relatively slow, a CPU could waste time waiting for the data from the device. This situation is called 'I/O bound'. Channel architecture avoids this problem by processing some or all of the I/O task without the aid of the CPU by offloading

3450-516: The first portion of the system loading software elsewhere in main storage. The first double word contains a PSW which, when fetched at the conclusion of the IPL, causes the CPU to execute the IPL Text (bootstrap loader) read in by the CCW at location 8. The IPL Text then locates, loads and transfers control to the operating system's Nucleus. The Nucleus performs or initiates any necessary initialization and then commences normal OS operations. This IPL concept

3519-407: The formatting of an entire track of a DASD requires only one channel program (and thus only one I/O instruction), but multiple channel command words (one per block). The program is executed by the dedicated I/O processor, while the application processor (the CPU) is free for other work. A channel command word ( CCW ) is an instruction to a specialized I/O channel processor which is, in fact,

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3588-525: The operating system implicitly issues yet another special SYSEVENT on the application's behalf if it has not already done so (SYSEVENT OKSWAP). Even bootstrapping of the system, or Initial Program Load (IPL) in IBM nomenclature, is carried out by channels, although the process is partially simulated by the CPU through an implied Start I/O (SIO) instruction, an implied Channel Address Word (CAW) at location 0 and an implied channel command word (CCW) with an opcode of Read IPL, also at location 0. Command chaining

3657-452: The pages are unfixed. As page fixing and unfixing is a CPU-expensive process long-term page fixing is sometimes used to reduce the CPU cost. Here the virtual memory is page-fixed for the life of the application, rather than fixing and freeing around each I/O operation. An example of a program that can use long-term page fixing is Db2 . An alternative to long-term page fixing is moving the entire application, including all its data buffers, to

3726-494: The system to shuffle execution of programs on the CPU depending on what data was available on the memory bus at that time, minimizing "dead time" where the CPU had to wait for data from the memory. The PP also included a set of sixty-four 32-bit communications registers (CRs). The CRs stored the state required for communication between the various parts of the ASC: the CPU, VPs, and channel controllers . The ASC instruction set include

3795-413: The systems' CPU(s). The CPU of a system that uses channel I/O typically has only one machine instruction in its repertoire for input and output; this instruction is used to pass input/output commands to the specialized I/O hardware in the form of channel programs . I/O thereafter proceeds without intervention from the CPU until an event requiring notification of the operating system occurs, at which point

3864-470: The time. 16 of the registers were used for addressing, 16 for scalar operations, 8 for index offsets, and 8 for specifying the various parameters for vector instructions. Data was moved between the registers and memory by load/store instructions, which could transfer from 4–64 bits (two registers) at a time. Most vector processors tended to be memory bandwidth-limited, that is, they could process data faster than they could get it from memory. This remains

3933-434: The very high levels of throughput that distinguish mainframes from other types of computers. In IBM ESA/390 terminology, a channel is a parallel data connection inside the tree-like or hierarchically organized I/O subsystem. In System/390 I/O cages, channels either directly connect to devices which are installed inside the cage (communication adapter such as ESCON , FICON , Open Systems Adapter ) or they run outside of

4002-413: The work to dedicated logic. Channels are logically self-contained, with sufficient logic and working storage to handle I/O tasks. Some are powerful or flexible enough to be used as a computer on their own and can be construed as a form of coprocessor , for example, the 7909 Data Channel on an IBM 7090 or IBM 7094 ; however, most are not. On some systems the channels use memory or registers addressable by

4071-409: Was a Texas-based company founded by John Clarence Karcher and Eugene McDermott in 1930, for the purpose of using refraction and reflection seismology to explore for petroleum deposits. On December 6, 1941, the company was purchased by Eugene McDermott , Cecil Howard Green , J. Erik Jonsson , and H.B. Peacock. During World War II , the company produced submarine detection devices. In 1951,

4140-474: Was a separate system dedicated entirely to quickly running the operating system and programs running within it, as well as feeding data to the CPU. The PP was built out of eight "virtual processors" (VPs), which were designed to handle instructions and basic integer arithmetic only. Each VP had its own program counter and registers, and the system could thus run eight programs at the same time, limited only by memory accesses. Keeping eight programs running allowed

4209-493: Was based around a single high-speed shared memory, which was accessed by the CPU and eight I/O channel controllers, in an organization similar to Seymour Cray 's groundbreaking CDC 6600 . Memory was accessed solely under the control of the memory control unit (MCU). The MCU was a two-way, 256-bit per channel parallel network that could support up to eight independent processors, with a ninth channel for accessing "main memory" (referred to as "extended memory"). The MCU also acted as

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4278-470: Was designed into the OS Supervisor just for those "fixes" which are of relatively short duration (i.e., significantly shorter than "wall-clock time"). Pages containing data to be used by the I/O operation are locked into real memory, or page fixed . The channel program is copied and all virtual addresses are replaced by real addresses before the I/O operation is started. After the operation completes,

4347-500: Was in some ways a more expandable design, in the supercomputer market speed is preferred, and the Cray-1 was much faster. ASC sales ended almost overnight, and although an upgraded ASC had been designed with a cycle time one-fifth that of the original, Texas Instruments decided to exit the market. The ASC #1 prototype was a one pipe system and brought up in Austin, Texas, off site from TI's main plant for proprietary information reasons. It

4416-663: Was later upgraded to two pipes and renamed as ASC # 1A. It was then used by TI's GSI division for seismic data processing. ASC #2 was leased to Shell Oil Company in the Netherlands and also used for seismic data processing. ASC #3 was installed at the Redstone Arsenal in Huntsville, Alabama, for Anti Ballistic Missile Interception technology development. With the SALT Treaty , the system was later redeployed to

4485-459: Was not profitable. After several years of losses, in 1994, Halliburton sold HGS to Western Atlas (formerly Western Geophysical until its merger with Dresser Atlas in 1987). Western Atlas was bought by Baker Hughes in 1998 and then merged into WesternGeco in 2000 through a joint venture with Schlumberger in which Schlumberger held the majority share (70%). On July 3, 1981, MS Arctic Explorer , chartered to GSI to conduct seismic surveys off

4554-447: Was not used in practice. At the fastest, it could sustain transfer rates of 80 million 32-bit words per second per port, for a total transfer rate of 640 million words per second. This was well beyond the capabilities of even the fastest memories of the era. The CPU had a 60 ns clock cycle (16.67 MHz clock frequency) and its logic was built from 20- gate emitter-coupled logic integrated circuits originally developed by TI for

4623-413: Was read from or written to main storage, the operating system program was interrupted if such interruption was specified by the channel program's Program Control Interrupt flag, and the "C-Unit" finally stored that channel's next state and set its I/O Channel out-tags , and then went on to the next lower priority channel. Preemption was possible, in some instances. Sufficient FIFO storage was provided within

4692-454: Was replaced by "Scientific" in the name, allowing the project to retain the designation ASC. Originally the software, including an operating system and a FORTRAN compiler, were done under contract by Computer Usage Company , under direction of George R. Trimble, Jr. but later taken over by TI itself. Southern Methodist University in Dallas developed an ALGOL compiler for the ASC. The ASC

4761-639: Was to include stripped-down Model 158s, operating in "Channel Mode", only, as the Model 303x channel units. In the Amdahl "C-unit" any channel could be any type, selector, byte multiplexor, or block multiplexor, without reserving channels 0 and 4 for the byte multiplexers, as on some IBM models. Some of the earliest commercial non-IBM channel systems were on the UNIVAC 490 , CDC 1604 , Burroughs B5000 , UNIVAC 1107 and GE 635 . Since then, channel controllers have been

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