Misplaced Pages

#540459

67-462: The operating system and files could be served from a VAX/VMS server running the company's VAX/VMS Services for MS-DOS software , which went through several name changes, finally becoming Pathworks . Alternatively an optional expansion box containing either 20 MB or 40 MB hard disk could be purchased which allowed it to operate as a more conventional stand-alone PC. The basic system contained an 8 MHz Intel 80286 CPU with 1 Mbyte of RAM,

134-470: A Q22-bus interface with DMA transfers. The MicroVAX II was succeeded by many further MicroVAX models with much improved performance and memory. Further VLSI VAX processors followed in the form of the V-11, CVAX , CVAX SOC ("System On Chip", a single-chip CVAX), Rigel , Mariah and NVAX implementations. The VAX microprocessors extended the architecture to inexpensive workstations and later also supplanted

201-407: A "one-address format" because each instruction includes the address of the data. One-address machines have the disadvantage that even simple actions like an addition require multiple instructions, each of which takes up scarce memory, and requires time to be read. Consider the simple task of adding two numbers, 5 + 4. In this case, the program would have to load the value 5 into the accumulator with

268-416: A 1.2 MB RX33 5¼-inch floppy disk drive, a 14-inch (diagonal) amber or green monochrome CRT and a thinwire Ethernet interface all contained in the system unit. It was also provided with a parallel printer port and a serial communications port. A separate mouse and LK250 keyboard were used with the device. As well as the expansion box, an 80287 numeric coprocessor could be ordered as an option, and

335-409: A collection of data values, encoded as numbers and referred to by their addresses , also a numerical value. This means the same operations applied to the data can be applied to the addresses themselves. While being worked on, data can be temporarily held in processor registers , scratchpad values that can be accessed very quickly. Registers are used, for example, when adding up strings of numbers into

402-470: A more powerful instruction set. The same basic idea was employed for the Intel 8086 , although, to allow for more radical extensions, binary -compatibility with the 8080 was not attempted here. It maintained some degree of non-orthogonality for the sake of high code density at the time. The 32-bit extension of this architecture that was introduced with the 80386 , was somewhat more orthogonal despite keeping all

469-415: A one-address format if a single address register is used. In this case, a number of new modes become available: Orthogonality is the principle that every instruction should be able to use any supported addressing mode. In this example, if the direct addressing version of ADD is available, all the others should be as well. The reason for this design is not aesthetic, the goal is to reduce the total size of

536-493: A program's object code . By providing a variety of addressing modes, the ISA allows the programmer to choose the one that precisely matches the need of their program at that point, and thereby reduce the need to use multiple instructions to achieve the same end. This means the total number of instructions is reduced, both saving memory and improving performance. Orthogonality was often described as being highly "bit efficient". Keeping

603-462: A simple two-address format of instructions, there is no way to change the address, so 1,000 additions have to be written in the machine language . ISAs fix this problem with the concept of indirect addressing , in which the address of the next point of data is not a constant, but itself held in memory or a machine register. This means the programmer can change the address by performing addition on that memory location or register. ISAs also often include

670-599: A successor to the 16-bit PDP-11 , one of the most successful minicomputers in history with approximately 600,000 units sold. The system was designed to offer backward compatibility with the PDP-11 while extending the memory to a full 32-bit implementation and adding demand paged virtual memory . The name VAX refers to its Virtual Address eXtension concept that allowed programs to make use of this newly available memory while still being compatible with unmodified user mode PDP-11 code. The name "VAX-11", used on early models,

737-462: A total. In early computers, the instruction set architecture (ISA) often used a single register, in which case it was known as the accumulator . Instructions included an address for the operand. For instance, an ADD address instruction would cause the CPU to retrieve the number in memory found at that address and then add it to the value already in the accumulator. This very simple example ISA has

SECTION 10

#1732776318541

804-457: Is " orthogonal " in the sense that the instruction type and the addressing mode may vary independently. An orthogonal instruction set does not impose a limitation that requires a certain instruction to use a specific register so there is little overlapping of instruction functionality. Orthogonality was considered a major goal for processor designers in the 1970s, and the VAX-11 is often used as

871-510: Is Digital's VAX/VMS (renamed to OpenVMS in 1991 or early 1992 when it was ported to Alpha , modified to comply with POSIX standards, and branded as compliant with XPG4 by the X/Open consortium). The VAX architecture and VMS operating system were " engineered concurrently " to take maximum advantage of each other, as was the initial implementation of the VAXcluster facility. During

938-521: The LOAD address instruction, use the ADD address instruction pointing to the address for the 4, and finally SAVE address to store the result, 9, back to another memory location. Further improvements can be found by providing the address of both of the operands in a single instruction, for instance, ADD address 1 , address 2 . Such "two-address format" ISAs are very common. One can further extend

1005-584: The DECstation and DECsystem respectively, using processors from MIPS Computer Systems . In 1992 DEC introduced their own RISC instruction set architecture, the Alpha AXP (later renamed Alpha), and their own Alpha-based microprocessor, the DECchip 21064 , a high performance 64-bit design capable of running OpenVMS. In August 2000, Compaq announced that the remaining VAX models would be discontinued by

1072-613: The PC and the stack pointer could be affected by the ordinary instructions using all of the ordinary data modes. "Immediate" mode (hardcoded numbers within an instruction, such as ADD #4, R1 (R1 = R1 + 4) was implemented as the mode "register indirect, autoincrement" and specifying the program counter (R7) as the register to use reference for indirection and to autoincrement. (Encoded as ADD (R7)+,R1 .word 4.) The PDP-11 used 3-bit fields for addressing modes (0-7) so there were (electronically) 8 addressing modes. An additional 3-bit field specified

1139-528: The VAX/VMS operating system . VAX has been perceived as the quintessential CISC ISA, with its very large number of assembly language programmer-friendly addressing modes and machine instructions, highly orthogonal instruction set architecture, and instructions for complex operations such as queue insertion or deletion, number formatting, and polynomial evaluation. The name "VAX" originated as an acronym for Virtual Address eXtension , both because

1206-741: The VAXstation workstations in the mid-1980s. The MicroVAX was superseded by the VAX 4000 , the VAX 8000 was superseded by the VAX 6000 in the late 1980s and the mainframe-class VAX 9000 was introduced. In the early 1990s, the fault-tolerant VAXft was introduced, as were the Alpha compatible VAX 7000/10000 . A variant of various VAX-based systems were sold as the VAXserver . System Industries developed an ability to give more than one DEC CPU, but not at

1273-521: The call stack for temporary storage. On the VAX, with 16 registers, this might require 16 instructions to save the data and another 16 to restore it. Using the mask, a single 16-bit value performs the same operations internally in hardware, saving time and memory. Since register masks are a form of data embedded within the executable code, they can make linear parsing of the machine code difficult. This can complicate optimization techniques that are applied on machine code. The native VAX operating system

1340-453: The mathematical concept : an orthogonal function set is easy to use as a basis into expanded functions, ensuring that parts don’t affect another if we change one part. At their core, all general purpose computers work in the same underlying fashion; data stored in a main memory is read by the central processing unit (CPU) into a fast temporary memory (e.g. CPU registers ), acted on, and then written back to main memory. Memory consists of

1407-458: The 1970s demonstrated that the flexibility offered by orthogonal modes was rarely or never used in actual problems. In particular, an effort at IBM studied traces of code running on the System/370 and demonstrated that only a fraction of the available modes were being used in actual programs. Similar studies, often about the VAX, demonstrated the same pattern. In some cases, it was shown that

SECTION 20

#1732776318541

1474-781: The 1980s, a hypervisor for the VAX architecture named VMM (Virtual Machine Monitor), also known as the VAX Security Kernel , was developed at Digital with the aim of allowing multiple isolated instances of VMS and ULTRIX to be run on the same hardware. VMM was intended to achieve TCSEC A1 compliance. By the late 1980s, it was operational on VAX 8000 series hardware, but was abandoned before release to customers. Other VAX operating systems have included various releases of Berkeley Software Distribution (BSD) UNIX up to 4.3BSD , Ultrix -32, VAXELN , and Xinu . More recently, NetBSD and OpenBSD have supported various VAX models and some work has been done on porting Linux to

1541-529: The 8-bit accumulator (the A-register), while 16-bit operations could be performed only on the 16-bit pointer/accumulator (the HL-register pair), whereas simple operations, such as increment, were possible on all seven 8-bit registers. This was largely due to a desire to keep all opcodes one byte long. The binary-compatible Z80 later added prefix-codes to escape from this 1-byte limit and allow for

1608-598: The 8086 instructions and their extended counterparts. However, the encoding-strategy used still shows many traces from the 8008 and 8080 (and Z80). For instance, single-byte encodings remain for certain frequent operations such as push and pop of registers and constants; and the primary accumulator, the EAX register , employs shorter encodings than the other registers on certain types of operations. Observations like this are sometimes exploited for code optimization in both compilers and hand written code. A number of studies through

1675-526: The 8100 and 8200 class machines. The VAX 11-730 and 725 low-end machines were built using AMD Am2901 bit-slice components for the ALU. The MicroVAX I represented a major transition within the VAX family. At the time of its design, it was not yet possible to implement the full VAX architecture as a single VLSI chip (or even a few VLSI chips as was later done with the V-11 CPU of the VAX 8200/8300). Instead,

1742-531: The MC68000 (68k) used separate registers to store data and the addresses of data in memory. The ISA was orthogonal to the extent that addresses could only be used in those registers, but there was no restriction on which of the registers could be used by different instructions. Likewise, the data registers were also orthogonal across instructions. Unlike the PDP-11, the 68000 only supported one general addressing mode for two-parameter instructions. The other parameter

1809-510: The MicroVAX I was the first VAX implementation to move some of the more complex VAX instructions (such as the packed decimal and related opcodes) into emulation software. This partitioning substantially reduced the amount of microcode required and was referred to as the "MicroVAX" architecture. In the MicroVAX I, the ALU and registers were implemented as a single gate-array chip while the rest of

1876-505: The PDP-11's 3-bit fields, the VAX-11's 4-bit sub-bytes resulted in 16 addressing modes (0–15). However, addressing modes 0–3 were "short immediate" for immediate data of 6 bits or less (the 2 low-order bits of the addressing mode being the 2 high-order bits of the immediate data, when prepended to the remaining 4 bits in that data-addressing byte). Since addressing modes 0-3 were identical, this made 13 (electronic) addressing modes, but as in

1943-471: The PDP-11, the Stack Pointer and Program Counter were in the general register file (R14 and R15). The general form of a VAX-11 instruction would be: Each component being one byte , the opcode a value in the range 0–255, and each operand consisting of two nibbles , the upper 4 bits specifying an addressing mode, and the lower 4 bits (usually) specifying a register number (R0–R15). In contrast to

2010-413: The PDP-11, the use of the Stack Pointer (R14) and Program Counter (R15) created a total of over 15 conceptual addressing modes (with the assembler program translating the source code into the actual stack-pointer or program-counter based addressing mode needed). Motorola's designers attempted to make the assembly language orthogonal while the underlying machine language was somewhat less so. Unlike PDP-11,

2077-730: The VAX architecture. OpenBSD discontinued support for the architecture in September 2016. The first VAX model sold was the VAX-11/780 , which was introduced on October 25, 1977, at the Digital Equipment Corporation's Annual Meeting of Shareholders. Bill Strecker, C. Gordon Bell 's doctoral student at Carnegie Mellon University , was responsible for the architecture. Many different models with different prices, performance levels, and capacities were subsequently created. VAX superminicomputers were very popular in

VAXmate - Misplaced Pages Continue

2144-540: The VAX processor (from the hard drives), and either RSX-11S or RT-11 on the LSI-11 (from the single density single drive floppy disk). The VAX went through many different implementations. The original VAX 11/780 was implemented in TTL and filled a four-by-five-foot cabinet with a single CPU . Through the 1980s, the high-end of the family was continually improved using ever-faster discrete components, an evolution that ended with

2211-427: The VAX was seen as a 32-bit extension of the older 16-bit PDP-11 and because it was (after Prime Computer ) an early adopter of virtual memory to manage this larger address space. Early versions of the VAX processor implement a "compatibility mode" that emulates many of the PDP-11's instructions, giving it the 11 in VAX-11 to highlight this compatibility. Later versions offloaded the compatibility mode and some of

2278-552: The ability to offset an address from an initial location, by adding a value held in one of its registers, in some cases a special index register . Others carry out this addition automatically as part of the instructions that use it. The variety of addressing modes leads to a profusion of slightly different instructions. Considering a one-address ISA, for even a single instruction, ADD , we now have many possible "addressing modes": Many ISAs also have registers that can be used for addressing as well as math tasks. This can be used in

2345-451: The addressing mode specifier bits separate from the opcode operation bits produces an orthogonal instruction set. As the ultimate end of orthogonal design is simply to allow any instruction to use any type of address, implementing orthogonality is often simply a case of adding more wiring between the parts of the processor. However, it also adds to the complexity of the instruction decoder, the circuitry that reads an instruction from memory at

2412-741: The aggregate performance of a VAXcluster . (The performance of the VAX-11/780 still serves as the baseline metric in the BRL-CAD Benchmark, a performance analysis suite included in the BRL-CAD solid modeling software distribution.) The VAX-11/780 included a subordinate stand-alone LSI-11 computer that performed microcode load, booting, and diagnostic functions for the parent computer. This was dropped from subsequent VAX models. Enterprising VAX-11/780 users could therefore run three different Digital Equipment Corporation operating systems: VMS on

2479-440: The benchmark for this concept. However, the introduction of RISC design philosophies in the 1980s significantly reversed the trend against more orthogonality. Modern CPUs often simulate orthogonality in a preprocessing step before performing the actual tasks in a RISC-like core. This "simulated orthogonality" in general is a broader concept, encompassing the notions of decoupling and completeness in function libraries , like in

2546-406: The complexity of the instructions meant they took longer to perform than the sequence of smaller instructions, with the canonical example of this being the VAX's INDEX instruction. During this same period, semiconductor memories were rapidly increasing in size and decreasing in cost. However, they were not improving in speed at the same rate. This meant the time needed to access data from memory

2613-486: The concept to a "three-address format" where the SAVE is also folded into an expanded ADD address 1 , address 2 , address of result . It is often the case that the basic computer word is much larger than needed to hold just the instruction and an address, and in most systems, there are leftover bits that can be used to hold a constant instead of an address. Instructions can be further improved if they allow any one of

2680-402: The constants in a program are between 0 and 10, with 0 representing between 20 and 30% of the total. Additionally, between 30 and 40% of all the values in a program are constants, with simple variables (as opposed to arrays or such) another 35 to 40%. If the processor uses a larger instruction word, like 32-bits, two register numbers and a constant can be encoded in a single instruction as long as

2747-474: The designers could afford. It was in the 1970s that the introduction of large scale integration significantly reduced the complexity of computer designs and fully orthogonal designs began to emerge. By the 1980s, such designs could be implemented on a single-chip CPU. In the late 1970s, with the first high-powered fully orthogonal designs emerging, the goal widened to become the high-level language computer architecture , or HLLCA for short. Just as orthogonality

VAXmate - Misplaced Pages Continue

2814-558: The early 1980s. For a while the VAX-11/780 was used as a standard in CPU benchmarks . It was initially described as a one- MIPS machine, because its performance was equivalent to an IBM System/360 that ran at one MIPS, and the System/360 implementations had previously been de facto performance standards. The actual number of instructions executed in 1 second was about 500,000, which led to complaints of marketing exaggeration. The result

2881-407: The elimination of the separate data and address registers found in the 68k. The 8-bit Intel 8080 (as well as the 8085 and 8051) microprocessor was basically a slightly extended accumulator-based design and therefore not orthogonal. An assembly-language programmer or compiler writer had to be mindful of which operations were possible on each register: Most 8-bit operations could be performed only on

2948-411: The end of the year, but old systems remain in widespread use. The Stromasys CHARON-VAX and SIMH software-based VAX emulators remain available. VMS is now developed by VMS Software Incorporated, albeit only for the Alpha , HPE Integrity , and x86-64 platforms. The VAX virtual memory is divided into four sections. Each is one gigabyte (in the context of addressing, 2 bytes) in size: For VMS, P0

3015-569: The high-end VAX models. This wide range of platforms (mainframe to workstation) using one architecture was unique in the computer industry at that time. Sundry graphics were etched onto the CVAX microprocessor die. The phrase CVAX... when you care enough to steal the very best was etched in broken Russian as a play on a Hallmark Cards slogan, intended as a message to Soviet engineers who were known to be both purloining DEC computers for military applications and reverse engineering their chip design. By

3082-480: The instruction itself does not use too many bits. These observations led to the abandonment of the orthogonal design as a primary goal of processor design, and the rise of the RISC philosophy in the 1980s. RISC processors generally have only two addressing modes, direct (constant) and register. All of the other modes found in older processors are handled explicitly using load and store instructions moving data to and from

3149-501: The introduction of the VAX 9000 in October 1989. This design proved too complex and expensive and was ultimately abandoned not long after introduction. CPU implementations that consisted of multiple emitter-coupled logic (ECL) gate array or macrocell array chips included the VAX 8600 and 8800 superminis and finally the VAX 9000 mainframe class machines. CPU implementations that consisted of multiple MOSFET custom chips included

3216-443: The late 1980s, the VAX microprocessors had grown in power to be competitive with discrete designs. This led to the abandonment of the 8000 and 9000 series and their replacement by Rigel-powered models of the VAX 6000 , and later by NVAX-powered VAX 7000 systems. In DEC's product offerings, the VAX architecture was eventually superseded by RISC technology. In 1989 DEC introduced a range of workstations and servers that ran Ultrix ,

3283-515: The late 20th century. The VAX-11/780 , introduced October 25, 1977, was the first of a range of popular and influential computers implementing the VAX ISA. The VAX family was a huge success for DEC, with the last members arriving in the early 1990s. The VAX was succeeded by the DEC Alpha , which included several features from VAX machines to make porting from the VAX easier. VAX was designed as

3350-414: The less used CISC instructions to emulation in the operating system software. The VAX instruction set was designed to be powerful and orthogonal . When it was introduced, many programs were written in assembly language, so having a "programmer-friendly" instruction set was important. In time, as more programs were written in high-level programming languages , the instruction set became less visible, and

3417-410: The location pointed to by the program counter and then decides how to process it. In the example ISA outlined above, the ADD.C instruction using direct encoding already has the data it needs to run the instruction and no further processing is needed, the decoder simply sends the value into the arithmetic logic unit (ALU). However, if the ADD.A instruction is used, the address has to be read,

SECTION 50

#1732776318541

3484-603: The machine control was conventional logic. A full VLSI ( microprocessor ) implementation of the MicroVAX architecture arrived with the MicroVAX II's 78032 (or DC333) CPU and 78132 (DC335) FPU. The 78032 was the first microprocessor with an on-board memory management unit The MicroVAX II was based on a single, quad-sized processor board which carried the processor chips and ran the MicroVMS or Ultrix -32 operating systems . The machine featured 1 MB of on-board memory and

3551-506: The memory could be expanded by 2 MB with another option to 3 MB. In North America, an internal modem was also available. It was superseded by the DECstation 200 and 300 in January 1989. VAX VAX (an acronym for Virtual Address eXtension ) is a series of computers featuring a 32-bit instruction set architecture (ISA) and virtual memory that was developed and sold by Digital Equipment Corporation (DEC) in

3618-419: The only ones much concerned about it were compiler writers. One unusual aspect of the VAX instruction set is the presence of register masks at the start of each subprogram. These are arbitrary bit patterns that specify, when control is passed to the subprogram, which registers are to be preserved. On most architectures, it is up to the compiler to produce instructions to save out the needed data, typically using

3685-422: The operands to be replaced by a constant. For instance, ADD address 1 , constant 1 eliminates one memory cycle, and ADD constant 1 , constant 2 another. Further complexity arises when one considers common patterns in which memory is accessed. One very common pattern is that a single operation may be applied across a large amount of similar data. For instance, one might want to add up 1,000 numbers. In

3752-402: The program to be translated more directly into the ISA. The PDP-11 was substantially orthogonal (primarily excepting its floating point instructions). Most integer instructions could operate on either 1-byte or 2-byte values and could access data stored in registers, stored as part of the instruction, stored in memory, or stored in memory and pointed to by addresses in registers or memory. Even

3819-409: The programmer to improve code density at the cost of making the CPU itself more complex. When memory was small and expensive, especially during the era of drum memory or core memory , orthogonality was highly desirable. However, the complexity was often beyond what could be achieved using current technology. For this reason, most machines from the 1960s offered only partial orthogonality, as much as

3886-650: The registers (R0–R5, SP, PC). Immediate and absolute address operands applying the two autoincrement modes to the Program Counter (R7), provided a total of 10 conceptual addressing modes. Most two operand instructions supported all addressing modes for both parameters. The VAX-11 extended the PDP-11's orthogonality to all data types, including floating point numbers. Instructions such as 'ADD' were divided into data-size dependent variants such as ADDB, ADDW, ADDL, ADDP, ADDF for add byte, word, longword, packed BCD and single-precision floating point, respectively. Like

3953-556: The same time, write access to a shared disk. They implemented an enhancement named SImultaneous Machine ACceSs ( SIMACS ), which allowed their special disk controller to set a semaphore flag for disk access, allowing multiple WRITES to the same files; the disk is shared by multiple DEC systems. SIMACS also existed on PDP-11 RSTS systems. Canceled systems include the BVAX , a high-end emitter-coupled logic (ECL) based VAX, and two other ECL-based VAX models: Argonaut and Raven . Raven

4020-434: The value at that memory location read, and then the ALU can continue. This series of events will take much longer to complete and requires more internal steps. As a result, the time needed to complete different variations of an instruction can vary widely, which adds complexity to the overall CPU design. Therefore, orthogonality represents a tradeoff in design; the computer designer can choose to offer more addressing modes to

4087-524: Was always a register, with the exception of MOV. The MOV instructions supported all addressing modes for both parameters. In contrast, the NS320xx series were originally designed as single-chip implementations of the VAX-11 ISA. Although this had to change due to legal issues, the resulting system retained much of the VAX-11's overall design philosophy and remained completely orthogonal. This included

SECTION 60

#1732776318541

4154-501: Was canceled in 1990. A VAX named Gemini was also canceled, which was a fall-back in case the LSI-based Scorpio failed. It never shipped. A number of VAX clones, both authorized and unauthorized, were produced. Examples include: Orthogonal instruction set In computer engineering , an orthogonal instruction set is an instruction set architecture where all instruction types can use all addressing modes . It

4221-517: Was chosen to highlight this capability. The VAX ISA is considered a complex instruction set computer (CISC) design. DEC quickly dropped the −11 branding as PDP-11 compatibility was no longer a major concern. The line expanded to both high-end mainframes like the VAX 9000 as well as to the workstation -scale systems like the VAXstation series. The VAX family ultimately contained ten distinct designs and over 100 individual models in total. All of them were compatible with each other and normally ran

4288-492: Was desired to improve the bit density of machine language, HLLCA's goal was to improve the bit density of high-level languages like ALGOL 68 . These languages generally used an activation record , a type of complex stack that stored temporary values, which the ISAs generally did not directly support and had to be implemented using many individual instructions from the underlying ISA. Adding support for these structures would allow

4355-492: Was growing in relative terms in comparison to the speed of the CPUs. This argued for the inclusion of more registers, giving the CPU more temporary values to work with. A larger number of registers meant more bits in the computer word would be needed to encode the register number, which suggested that the instructions themselves be reduced in number to free up room. Finally, a paper by Andrew Tanenbaum demonstrated that 97% of all

4422-456: Was the definition of a "VAX MIPS", the speed of a VAX-11/780; a computer performing at 27 VAX MIPS would run the same program roughly 27 times faster than the VAX-11/780. Within the Digital community the term VUP ( VAX Unit of Performance ) was the more common term, because MIPS do not compare well across different architectures. The related term cluster VUPs was informally used to describe

4489-420: Was used for user process space, P1 for process stack, S0 for the operating system, and S1 was reserved. The VAX has four hardware implemented privilege modes: The process status longword contains 32 bits: The first VAX-based system was the VAX-11/780 , a member of the VAX-11 family. The high-end VAX 8600 replaced the VAX-11/780 in October 1984 and was joined by the entry-level MicroVAX minicomputers and

#540459