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55-475: XCR can stand for: Extended Control Register in the x86 architecture Robinson Armament XCR , a multi-caliber, gas piston combat rifle Vatry Airport in France (IATA code) Topics referred to by the same term [REDACTED] This disambiguation page lists articles associated with the title XCR . If an internal link led you here, you may wish to change

110-523: A 386 to be set up to act like it had a flat memory model in protected mode despite the fact that it uses a segmented memory model in all modes was arguably the most important feature change for the x86 processor family until AMD released the x86-64 in 2003. Several new instructions have been added to 386: BSF, BSR, BT, BTS, BTR, BTC, CDQ, CWDE, LFS, LGS, LSS, MOVSX, MOVZX, SETcc, SHLD, SHRD. Two new segment registers have been added (FS and GS) for general-purpose programs. The single Machine Status Word of

165-427: A complete simulation of system board. This die contains the 386 CPU core, AT Bus Controller, Memory Controller, Internal Bus Controller, Cache Control Logic along with Cache Tag SRAM and Clock. This CPU contains 855,000 transistors using one-micron CHMOS IV technology. It was available for USD $ 176 in 1,000 unit in quantities. The 25-MHz version was available in samples for USD $ 189 in 1,000-piece quantities, that version

220-431: A critical constraint at the time. Performance differences were due not only to differing data-bus widths, but also due to performance-enhancing cache memories often employed on boards using the original chip. This version can run the 32-bit application software at 70 to 90 percent compare to the regular Intel386 DX CPU. The original 80386 was subsequently renamed i386DX to avoid confusion. However, Intel subsequently used

275-424: A double sigma (ΣΣ), and affected processors were marked "16 BIT S/W ONLY". These latter processors were sold as good parts, since at the time 32-bit capability was not relevant for most users. The i387 math coprocessor was not ready in time for the introduction of the 80386, and so many of the early 80386 motherboards instead provided a socket and hardware logic to make use of an 80287 . In this configuration

330-531: A limited set of internal signals and flags. When IBM developed a paging version of the System/360 , they added 16 control registers to the design for what became the 360/67 . IBM did not provide control registers on other S/360 models, but made them a standard part of System/370 , although with different register and bit assignments. As IBM added new features to the architecture, e.g., DAS , S/370-XA , S/370-ESA , ESA/390 , they added additional fields to

385-657: A wide range of upgrades, for both SX and DX systems. The most popular ones were based on the Cyrix 486DLC/SLC core, which typically offered a substantial speed improvement due to its more efficient instruction pipeline and internal L1 SRAM cache. The cache was usually 1 KB, or sometimes 8 KB in the TI variant. Some of these upgrade chips (such as the 486DRx2/SRx2) were marketed by Cyrix themselves, but they were more commonly found in kits offered by upgrade specialists such as Kingston, Evergreen Technologies and Improve-It Technologies. Some of

440-534: Is a control register which is used to toggle the storing or loading of registers related to specific CPU features using the XSAVE/XRSTOR instructions. It is also used with some features to enable or disable the processor's ability to execute their corresponding instructions. It can be changed using the privileged XSETBV read using the unprivileged XGETBV instructions. There is also the IA32_XSS MSR, which

495-494: Is a daughtercard with 20-MHz 386SX and 16-Kbyte direct-mapped cache SRAM memory. It directly plugs into the existing 286 socket with no cables, jumpers or switches. In the winter of 1992, an additional to this module now supported to IBM PS/2 Model 50 Z , 30 286 and 25 286 systems. Both modules were available for USD $ 495. A specially packaged Intel 486 DX and a dummy floating-point unit (FPU) designed as pin-compatible replacements for an i386 processor and i387 FPU. This

550-650: Is assumed, specifically, that the DS and ES segments address the same region of memory. The first PC based on the Intel 80386 was the Compaq Deskpro 386 . By extending the 16/24-bit IBM PC/AT standard into a natively 32-bit computing environment, Compaq became the first company to design and manufacture such a major technical hardware advance on the PC platform. IBM was offered use of the 80386, but had manufacturing rights for

605-460: Is copied one byte (8-bit character) at a time. The example code uses the EBP (base pointer) register to establish a call frame , an area on the stack that contains all of the parameters and local variables for the execution of the subroutine. This kind of calling convention supports reentrant and recursive code and has been used by Algol-like languages since the late 1950s. A flat memory model

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660-616: Is enabled, hence when the PG bit is set in CR0. CR3 enables the processor to translate linear addresses into physical addresses by locating the page directory and page tables for the current task. Typically, the upper 20 bits of CR3 become the page directory base register (PDBR), which stores the physical address of the first page directory. If the PCIDE bit in CR4 is set, the lowest 12 bits are used for

715-635: Is located at address DA0h . The IA32_XSS MSR controls bits of XCR0 which are considered to be "supervisor" state, and should be invisible to regular programs. It operates with the privileged XSAVES and XRSTORS instructions by adding supervisor state to the data they operate with. Put simply, if the X87 state was enabled in XCR0 and PT state was enabled in IA32_XSS, the XSAVE instruction would only store X87 state, while

770-600: Is the 32 Bit version of the old Machine Status Word (MSW) register. The MSW register was expanded to the Control Register with the appearance of the i386 processor. Reserved, the CPU will throw a # UD exception when trying to access it. Contains a value called Page Fault Linear Address (PFLA). When a page fault occurs, the address the program attempted to access is stored in the CR2 register. Used when virtual addressing

825-648: Is the Relocation exception address register. CR4 is the extended mask register for channels 0-31. Each bit is the 1/0 channel mask for the corresponding channel. CR5 is reserved for the extended mask register for channels 32–63. Each bit is the 1/0 channel mask for the corresponding channel. CR6 contains two mode flags plus extensions to the PSW mask bits. Control Register 8 contains the assignments of Processor Storage units 1–4 to central processing units (CPUs) and channel controllers (CCs). Control Register 9 contains

880-400: Is to be blocked. For example, loading TPR with a value of 9 (1001b) blocks all interrupts with a priority class of 9 or less, while allowing all interrupts with a priority class of 10 or more to be recognized. Loading TPR with 0 enables all external interrupts. Loading TPR with 15 (1111b) disables all external interrupts. The TPR is cleared to 0 on reset. XCR0, or Extended Control Register 0,

935-584: The IBM S/390 are an evolutionary enhancement to the control registers on the earlier ESA/370 , S/370-XA and S/370 processors. For details on which fields are dependent on specific features, consult the Principles of Operation. The control registers of z/Architecture are an evolutionary enhancement to the control registers of the earlier ESA/390 on the IBM S/390 processors. For details on which fields are dependent on specific features, consult

990-568: The Intel 80286 , the 80386 added a three-stage instruction pipeline which it brings up to total of 6-stage instruction pipeline, extended the architecture from 16-bits to 32-bits, and added an on-chip memory management unit . This paging translation unit made it much easier to implement operating systems that used virtual memory . It also offered support for register debugging . The 80386 featured three operating modes: real mode, protected mode and virtual mode. The protected mode , which debuted in

1045-706: The SYSCALL /SYSRET instruction, and later for entering and exiting long mode . This register becomes architectural in AMD64 and has been adopted by Intel as IA32_EFER. Its MSR number is 0xC0000080. CR8 is a new register accessible in 64-bit mode using the REX prefix. CR8 is used to prioritize external interrupts and is referred to as the task-priority register (TPR). The AMD64 architecture allows software to define up to 15 external interrupt-priority classes. Priority classes are numbered from 1 to 15, with priority-class 1 being

1100-488: The process-context identifier (PCID). Used in protected mode to control operations such as virtual-8086 support, enabling I/O breakpoints, page size extension and machine-check exceptions . If PAE is enabled or the processor is in x86-64 long mode this bit is ignored. Reserved, same case as CR1. Extended Feature Enable Register (EFER) is a model-specific register added in the AMD K6 processor, to allow enabling

1155-451: The "DX" suffix to refer to the floating-point capability of the i486DX. The 387SX was an 80387 part that was compatible with the 386SX (i.e. with a 16-bit databus). The 386SX was packaged in a surface-mount QFP and sometimes offered in a socket to allow for an upgrade. The 16 MHz 386SX contains the 100-lead BQFP. It was available for USD $ 165 in quantities of 1000. It has the performance of 2.5 to 3 MIPS as well. The low-power version

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1210-524: The 286 grew into eight control registers CR0–CR7. Debug registers DR0–DR7 were added for hardware breakpoints. New forms of the MOV instruction are used to access them. The chief architect in the development of the 80386 was John H. Crawford . He was responsible for extending the 80286 architecture and instruction set to 32-bits, and then led the microprogram development for the 80386 chip. The i486 and P5 Pentium line of processors were descendants of

1265-423: The 286, was extended to allow the 386 to address up to 4 GB of memory. With the addition of segmented addressing system, it can expand up to 64 terabytes of virtual memory. The all new virtual 8086 mode (or VM86 ) made it possible to run one or more real mode programs in a protected environment, although some programs were not compatible. It features scaled indexing and 64-bit barrel shifter. The ability for

1320-401: The 386DX remained the high-end variant used in workstations, servers, and other demanding tasks. The CPU remained fully 32-bit internally, but the 16-bit bus was intended to simplify circuit-board layout and reduce total cost. The 16-bit bus simplified designs but hampered performance. Only 24 pins were connected to the address bus, therefore limiting addressing to 16  MB , but this was not

1375-413: The 80286, was extended to allow the 386 to address up to 4 GB of memory. With the addition of segmented addressing system, it can expand up to 64 terabytes of virtual memory. The all new virtual 8086 mode (or VM86 ) made it possible to run one or more real mode programs in a protected environment, although some programs were not compatible. The 32-bit i386 can correctly execute most code intended for

1430-406: The 80386 to debut at 16 MHz. However, due to poor yields, it was instead introduced at 12.5 MHz. Early in production, Intel discovered a marginal circuit that could cause a system to return incorrect results from 32-bit multiply operations. Not all of the processors already manufactured were affected, so Intel tested its inventory. Processors that were found to be bug-free were marked with

1485-596: The 80386's mainstream adoption. The first personal computer to make use of the 80386 was the Deskpro 386 , designed and manufactured by Compaq ; this marked the first time a fundamental component in the IBM PC compatible de facto standard was updated by a company other than IBM . The first versions of the 386 had 275,000 transistors. The 20 MHz version operates at 4–5 MIPS . It also performs between 8,000 and 9,000 Dhrystones per second. The 25 MHz 386 version

1540-523: The CPU being unaware, which caused problems on CPUs with internal caches. Overall, it was very difficult to configure upgrades to produce the results advertised on the packaging, and upgrades were often not very stable or not fully compatible. Original version, released in October 1985. The 16 MHz version was available for 299  USD in quantities of 100. The 20 MHz version was available for US$ 599 in quantities of 100. The 33 MHz version

1595-611: The FPU operated asynchronously to the CPU, usually with a clock rate of 10 MHz. The original Compaq Deskpro 386 is an example of such design. However, this was an annoyance to those who depended on floating-point performance, as the performance advantages of the 80387 over the 80287 were significant. Intel later offered a modified version of its 486DX in i386 packaging, branded as the Intel RapidCAD . This provided an upgrade path for users with i386-compatible hardware. The upgrade

1650-468: The Principles of Operation. Because z/Architecture expands the control registers from 32 bits to 64, the bit numbering differs from that in ESA/390. only) The CR0 register is 32 bits long on the 386 and higher processors. On x64 processors in long mode , it (and the other control registers) is 64 bits long. CR0 has various control flags that modify the basic operation of the processor. Register CR0

1705-479: The assignments of Processor Storage units 5–8 to central processing units (CPUs) and channel controllers (CCs). Control Register 10 contains the Processor storage address assignment codes. Control Register 11 contains channel controller (CC) assignments. CR12 contains I/O Control Unit Partitioning. CR13 contains I/O Control Unit Partitioning. CR14 contains indicators. The control registers of ESA/390 on

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1760-530: The chip for embedded systems . Such systems using an i386 or one of many derivatives are common in aerospace technology and electronic musical instruments, among others. Some mobile phones also used (later fully static CMOS variants of) the i386 processor, such as the BlackBerry 950 and Nokia 9000 Communicator . Linux continued to support i386 processors until December 11, 2012, when the kernel cut 386-specific instructions in version 3.8. The processor

1815-522: The chips in significant quantities commenced in June 1986, along with the first plug-in device that allowed existing 80286-based computers to be upgraded to the 386, the Translator 386 by American Computer and Peripheral . The 80386 being sole sourced made the CPU very expensive. Mainboards for 80386-based computer systems were cumbersome and expensive at first, but manufacturing was justified upon

1870-438: The control registers. With z/Architecture , IBM doubled the control register size to 64 bits. On the 360/67 , CR0 and CR2 are used by address translation, CR 4-6 contain miscellaneous flags including interrupt masks and Extended Control Mode, and CR 8-14 contain the switch settings on the 2167 Configuration Unit. Control Register 0 contains the address of the segment table for dynamic address translation. Control register 2

1925-527: The earlier 80286 . IBM therefore chose to rely on that processor for a couple more years. The early success of the Compaq Deskpro 386 played an important role in legitimizing the PC "clone" industry and in de-emphasizing IBM's role within it. The first computer system sold with the 386SX was the Compaq Deskpro 386S , released in July 1988. Prior to the 386, the difficulty of manufacturing microchips and

1980-442: The earlier 16-bit processors such as 8086 and 80286 that were ubiquitous in early PCs . As the original implementation of the 32-bit extension of the 80286 architecture, the i386 instruction set, programming model, and binary encodings are still the common denominator for all 32-bit x86 processors, which is termed the i386 architecture , x86 , or IA-32 , depending on context. Over the years, successively newer implementations of

2035-509: The fastest CPU upgrade modules featured the IBM SLC/DLC family (notable for its 16 KB L1 cache), or even the Intel 486 itself. Many 386 upgrade kits were advertised as being simple drop-in replacements, but often required complicated software to control the cache or clock doubling. Part of the problem was that on most 386 motherboards, the A20 line was controlled entirely by the motherboard with

2090-413: The i386 design. The following data types are directly supported and thus implemented by one or more i386 machine instructions ; these data types are briefly described here. : The following i386 assembly source code is for a subroutine named _strtolower that copies a null-terminated ASCIIZ character string from one location to another, converting all alphabetic characters to lower case. The string

2145-559: The i386DX. The i386SL was first available at 20 MHz clock speed, with the 25 MHz model later added. With this system, it reduced up to 40% foot space than the Intel386 SX system. That translate to lighter and more portable cost-effective system. Dave Vannier, the chief architect designed this microprocessor. It took them two years to complete this design since it uses the existing 386 architecture to implement. That assist with advanced computer-aided design tools which includes

2200-437: The link to point directly to the intended article. Retrieved from " https://en.wikipedia.org/w/index.php?title=XCR&oldid=962865131 " Category : Disambiguation pages Hidden categories: Short description is different from Wikidata All article disambiguation pages All disambiguation pages Control register#XCR0 and XSS The early CPU lacked dedicated control registers, and relied on

2255-461: The lowest and priority-class 15 the highest. CR8 uses the four low-order bits for specifying a task priority and the remaining 60 bits are reserved and must be written with zeros. System software can use the TPR register to temporarily block low-priority interrupts from interrupting a high-priority task. This is accomplished by loading TPR with a value corresponding to the highest-priority interrupt that

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2310-653: The maintenance burden around SMP primitives, the Linux kernel developers cut support from the development codebase in December 2012, later released as kernel version 3.8. Among the BSDs , FreeBSD 's 5.x releases were the last to support the 386; support for the 386SX was cut with release 5.2, while the remaining 386 support was removed with the 6.0 release in 2005. OpenBSD removed 386 support with version 4.2 (2007), DragonFly BSD with release 1.12 (2008), and NetBSD with

2365-494: The privileged XSAVES would store both X87 and PT states. Because it is an MSR, it can be accessed using the RDMSR and WRMSR instructions. Intel 80386 The Intel 386 , originally released as the 80386 and later renamed i386 , was the first x86 32-bit microprocessor designed by Intel . Pre-production samples of the 386 were released to select developers in 1985, while mass production commenced in 1986. The processor

2420-703: The processor as second sources . This decision was ultimately crucial to Intel's success in the market. The 386 was the first significant microprocessor to be single-sourced . Single-sourcing the 386 allowed Intel greater control over its development and substantially greater profits in later years. AMD introduced its compatible Am386 processor in March 1991 after overcoming legal obstacles, thus ending Intel's 4.7-year monopoly on 386-compatible processors. From 1991 IBM also manufactured 386 chips under license for use only in IBM PCs and boards. Intel originally intended for

2475-412: The same architecture have become several hundreds of times faster than the original 80386 (and thousands of times faster than the 8086). Development of i386 technology began in 1982 under the internal name of P3. The tape-out of the 80386 development was finalized in July 1985. The 80386 was introduced as pre-production samples for software development workstations in October 1985. Manufacturing of

2530-418: The uncertainty of reliable supply made it desirable that any mass-market semiconductor be multi-sourced, that is, made by two or more manufacturers, the second and subsequent companies manufacturing under license from the originating company. The 386 was for a time (4.7 years) only available from Intel, since Andy Grove , Intel's CEO at the time, made the decision not to encourage other manufacturers to produce

2585-463: Was a pair of chips that replaced both the i386 and i387. Since the 486DX design contained an FPU , the chip that replaced the i386 contained the floating-point functionality, and the chip that replaced the i387 served very little purpose. However, the latter chip was necessary in order to provide the FERR signal to the mainboard and appear to function as a normal floating-point unit. Third parties offered

2640-774: Was a significant evolution in the x86 architecture, and extended a long line of processors that stretched back to the Intel 8008 . The predecessor of the 80386 was the Intel 80286 , a 16-bit processor with a segment -based memory management and protection system. The 80386 added a three-stage instruction pipeline which it brought up to total of 6-stage instruction pipeline, extended the architecture from 16-bits to 32-bits , and added an on-chip memory management unit . This paging translation unit made it much easier to implement operating systems that used virtual memory . It also offered support for register debugging . The 80386 featured three operating modes: real mode, protected mode and virtual mode. The protected mode , which debuted in

2695-486: Was a significant evolution in the x86 architecture, extending a long line of processors that stretched back to the Intel 8008 . The 386 was the central processing unit (CPU) of many workstations and high-end personal computers of the time. The 386 began to fall out of public use starting with the release of the i486 processor in 1989, while in embedded systems the 386 remained in widespread use until Intel finally discontinued it in 2007. Compared to its predecessor

2750-663: Was an embedded version of the 80386SX which did not support real mode and paging in the MMU. System and power management and built in peripheral and support functions: Two 82C59A interrupt controllers; Timer, Counter (3 channels); Asynchronous SIO (2 channels); Synchronous SIO (1 channel); Watchdog timer (Hardware/Software); PIO . Usable with 80387SX or i387SL FPUs. Transparent power management mode, integrated MMU and TTL compatible inputs (only 386SXSA). Usable with i387SX or i387SL FPUs. Transparent power management mode and integrated MMU . Usable with i387SX or i387SL FPUs. Windows 95

2805-510: Was available on April 10, 1989. The military version was made using the CHMOS III process technology. It was made to withstand 105 Rads (Si) or greater. It was available for US$ 945 each in quantities of 100. In 1988, Intel introduced the 80386SX , most often referred to as the 386SX , a cut-down version of the 80386 with a 16-bit data bus, mainly intended for lower-cost PCs aimed at the home, educational, and small-business markets, while

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2860-575: Was available on April 10, 1989. This version that uses 20 to 30 percent less power and has higher operating temperature up to 100 °C than the regular version. The 80386SL was introduced as a power-efficient version for laptop computers . The processor offered several power-management options (e.g. SMM ), as well as different "sleep" modes to conserve battery power. It also contained support for an external cache of 16 to 64 KB . The extra functions and circuit implementation techniques caused this variant to have over 3 times as many transistors as

2915-432: Was capable of 7 MIPS. A 33 MHz 80386 was reportedly measured to operate at about 11.4 and 11.5 MIPS. At that same speed, it has the performance of 8 VAX MIPS . These processors were running about 4.4 clocks per instruction. In May 2006, Intel announced that i386 production would stop at the end of September 2007. Although it had long been obsolete as a personal computer CPU, Intel and others had continued making

2970-477: Was finally made available in production by the end of 1991. It supports up to 32 Megabytes of physical address space. There was a 20-MHz cacheless version of Intel386 SL microprocessor, at the press time samples of this version were available for USD $ 101 in 1,000-piece quantities. In May 1991, Intel introduced an upgrade for IBM PS/2 Model 50 and 60 systems which contain 80286 microprocessors, converting them to full blown 32-bit systems. The SnapIn 386 module

3025-536: Was the only entry in the Windows 9x series to officially support the 386, requiring at least a 386DX, though a 486 or better was recommended; Windows 98 requires a 486DX or higher. In the Windows NT family, Windows NT 3.51 was the last version with 386 support. Debian GNU/Linux dropped 386 support with the release of 3.1 ( Sarge ) in 2005 and completely removed support in 2007 with 4.0 ( Etch ). Citing

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