Misplaced Pages

#465534

67-605: The X-MP's main improvement over the Cray-1 was that it was a shared-memory parallel vector processor , the first such computer from Cray Research. It housed up to four CPUs in a mainframe that was nearly identical in outside appearance to the Cray-1. The X-MP CPU had a faster 9.5  nanosecond clock cycle (105 MHz), compared to 12.5 ns for the Cray-1A. It was built from bipolar gate-array integrated circuits containing 16 emitter-coupled logic gates each. The CPU

134-437: A variable that is shared between them. Without synchronization, the instructions between the two threads may be interleaved in any order. For example, consider the following program: If instruction 1B is executed between 1A and 3A, or if instruction 1A is executed between 1B and 3B, the program will produce incorrect data. This is known as a race condition . The programmer must use a lock to provide mutual exclusion . A lock

201-486: A chassis similar to the horseshoe-shaped X-MP, but with an extra rectangular cabinet added in the middle (containing the CPU boards), thus forming a "Y" shape in plan view. The system could be configured with one or two Model D IOSs (Input/Output Subsystems) and an optional Solid State Disk (SSD) of 256 MB to 4GB capacity. The Y-MP had a measured GFLOPS of 2.144 and a peak GFLOPS of 2.667 in both 1988 and 1989. The Model D Y-MP

268-532: A combination of parallelism and concurrency characteristics. Parallel computers can be roughly classified according to the level at which the hardware supports parallelism, with multi-core and multi-processor computers having multiple processing elements within a single machine, while clusters , MPPs , and grids use multiple computers to work on the same task. Specialized parallel computer architectures are sometimes used alongside traditional processors, for accelerating specific tasks. In some cases parallelism

335-461: A completely new design, was introduced in 1985. A very different compact four-processor design with from 64 MW (megaword) to 512 MW (512 MB to 4 GB) of main memory, it was specified to 500 MFLOPS but was slower than the X-MP on certain calculations due to its high memory latency. The Cray Y-MP upgrade of the X-MP series was announced in 1988; it also had a new design, replacing

402-795: A guest operating system facility. UNICOS became the main OS from 1986 onwards. The DOE ran the Cray Time Sharing System OS instead. See the Software section for the Cray-1 for a more detailed elaboration of software (language compiler, assembler, operating systems, and applications) as X-MPs and Cray-1s were mostly compatible. Cray Research announced the X-MP Extended Architecture series in 1986. The EA series CPU had an 8.5 ns clock cycle (117 MHz), and

469-472: A long chain of dependent calculations; there are usually opportunities to execute independent calculations in parallel. Let P i and P j be two program segments. Bernstein's conditions describe when the two are independent and can be executed in parallel. For P i , let I i be all of the input variables and O i the output variables, and likewise for P j . P i and P j are independent if they satisfy Violation of

536-404: A more realistic assessment of the parallel performance. Understanding data dependencies is fundamental in implementing parallel algorithms . No program can run more quickly than the longest chain of dependent calculations (known as the critical path ), since calculations that depend upon prior calculations in the chain must be executed in order. However, most algorithms do not consist of just

603-520: A multi-core processor can issue multiple instructions per clock cycle from multiple instruction streams. IBM 's Cell microprocessor , designed for use in the Sony PlayStation 3 , is a prominent multi-core processor. Each core in a multi-core processor can potentially be superscalar as well—that is, on every clock cycle, each core can issue multiple instructions from one thread. Simultaneous multithreading (of which Intel's Hyper-Threading

670-403: A node), or n-dimensional mesh . Parallel computers based on interconnected networks need to have some kind of routing to enable the passing of messages between nodes that are not directly connected. The medium used for communication between the processors is likely to be hierarchical in large multiprocessor machines. Parallel computers can be roughly classified according to the level at which

737-543: A pipelined processor is a RISC processor, with five stages: instruction fetch (IF), instruction decode (ID), execute (EX), memory access (MEM), and register write back (WB). The Pentium 4 processor had a 35-stage pipeline. Most modern processors also have multiple execution units . They usually combine this feature with pipelining and thus can issue more than one instruction per clock cycle ( IPC > 1 ). These processors are known as superscalar processors. Superscalar processors differ from multi-core processors in that

SECTION 10

#1732779842466

804-471: A result, shared memory computer architectures do not scale as well as distributed memory systems do. Processor–processor and processor–memory communication can be implemented in hardware in several ways, including via shared (either multiported or multiplexed ) memory, a crossbar switch , a shared bus or an interconnect network of a myriad of topologies including star , ring , tree , hypercube , fat hypercube (a hypercube with more than one processor at

871-412: A single address space ), or distributed memory (in which each processing element has its own local address space). Distributed memory refers to the fact that the memory is logically distributed, but often implies that it is physically distributed as well. Distributed shared memory and memory virtualization combine the two approaches, where the processing element has its own local memory and access to

938-500: A sufficient amount of memory bandwidth exists. A distributed computer (also known as a distributed memory multiprocessor) is a distributed memory computer system in which the processing elements are connected by a network. Distributed computers are highly scalable. The terms " concurrent computing ", "parallel computing", and "distributed computing" have a lot of overlap, and no clear distinction exists between them. The same system may be characterized both as "parallel" and "distributed";

1005-512: A time from multiple threads. A symmetric multiprocessor (SMP) is a computer system with multiple identical processors that share memory and connect via a bus . Bus contention prevents bus architectures from scaling. As a result, SMPs generally do not comprise more than 32 processors. Because of the small size of the processors and the significant reduction in the requirements for bus bandwidth achieved by large caches, such symmetric multiprocessors are extremely cost-effective, provided that

1072-416: Is a programming language construct that allows one thread to take control of a variable and prevent other threads from reading or writing it, until that variable is unlocked. The thread holding the lock is free to execute its critical section (the section of a program that requires exclusive access to some variable), and to unlock the data when it is finished. Therefore, to guarantee correct program execution,

1139-608: Is achieved by balancing enhancements to both parallelizable and non-parallelizable components of a task. Furthermore, it reveals that increasing the number of processors yields diminishing returns, with negligible speedup gains beyond a certain point. Amdahl's Law has limitations, including assumptions of fixed workload, neglecting inter-process communication and synchronization overheads, primarily focusing on computational aspect and ignoring extrinsic factors such as data persistence, I/O operations, and memory access overheads. Gustafson's law and Universal Scalability Law give

1206-486: Is constructed and implemented as a serial stream of instructions. These instructions are executed on a central processing unit on one computer. Only one instruction may execute at a time—after that instruction is finished, the next one is executed. Parallel computing, on the other hand, uses multiple processing elements simultaneously to solve a problem. This is accomplished by breaking the problem into independent parts so that each processing element can execute its part of

1273-516: Is equivalent to an entirely sequential program. The single-instruction-multiple-data (SIMD) classification is analogous to doing the same operation repeatedly over a large data set. This is commonly done in signal processing applications. Multiple-instruction-single-data (MISD) is a rarely used classification. While computer architectures to deal with this were devised (such as systolic arrays ), few applications that fit this class materialized. Multiple-instruction-multiple-data (MIMD) programs are by far

1340-465: Is known as burst buffer , which is typically built from arrays of non-volatile memory physically distributed across multiple I/O nodes. Computer architectures in which each element of main memory can be accessed with equal latency and bandwidth are known as uniform memory access (UMA) systems. Typically, that can be achieved only by a shared memory system, in which the memory is not physically distributed. A system that does not have this property

1407-429: Is known as a non-uniform memory access (NUMA) architecture. Distributed memory systems have non-uniform memory access. Computer systems make use of caches —small and fast memories located close to the processor which store temporary copies of memory values (nearby in both the physical and logical sense). Parallel computer systems have difficulties with caches that may store the same value in more than one location, with

SECTION 20

#1732779842466

1474-493: Is necessary, such as semaphores , barriers or some other synchronization method . Subtasks in a parallel program are often called threads . Some parallel computer architectures use smaller, lightweight versions of threads known as fibers , while others use bigger versions known as processes . However, "threads" is generally accepted as a generic term for subtasks. Threads will often need synchronized access to an object or other resource , for example when they must update

1541-429: Is the best known) was an early form of pseudo-multi-coreism. A processor capable of concurrent multithreading includes multiple execution units in the same processing unit—that is it has a superscalar architecture—and can issue multiple instructions per clock cycle from multiple threads. Temporal multithreading on the other hand includes a single execution unit in the same processing unit and can issue one instruction at

1608-529: Is the characteristic of a parallel program that "entirely different calculations can be performed on either the same or different sets of data". This contrasts with data parallelism, where the same calculation is performed on the same or different sets of data. Task parallelism involves the decomposition of a task into sub-tasks and then allocating each sub-task to a processor for execution. The processors would then execute these sub-tasks concurrently and often cooperatively. Task parallelism does not usually scale with

1675-455: Is the computing unit of the processor and in multi-core processors each core is independent and can access the same memory concurrently. Multi-core processors have brought parallel computing to desktop computers . Thus parallelization of serial programs has become a mainstream programming task. In 2012 quad-core processors became standard for desktop computers , while servers have 10+ core processors. From Moore's law it can be predicted that

1742-440: Is transparent to the programmer, such as in bit-level or instruction-level parallelism, but explicitly parallel algorithms , particularly those that use concurrency, are more difficult to write than sequential ones, because concurrency introduces several new classes of potential software bugs , of which race conditions are the most common. Communication and synchronization between the different subtasks are typically some of

1809-646: The Y-MP ;2E , Y-MP 4E , Y-MP 8E and Y-MP 8I , the latter being a single-cabinet ( I for Integrated ) version of the two-cabinet 8E. The 2E and 4E were later available with optional secondary air cooling. The Y-MP M90 was a large-memory variant of the Y-MP Model E introduced in 1992. This replaced the SRAM of the Y-MP with up to 32 GB of slower, but physically smaller DRAM devices. The Y-MP M90

1876-561: The speedup from parallelization would be linear—doubling the number of processing elements should halve the runtime, and doubling it a second time should again halve the runtime. However, very few parallel algorithms achieve optimal speedup. Most of them have a near-linear speedup for small numbers of processing elements, which flattens out into a constant value for large numbers of processing elements. The maximum potential speedup of an overall system can be calculated by Amdahl's law . Amdahl's Law indicates that optimal performance improvement

1943-406: The 16-gate ECL gate arrays with a more compact VLSI gate array with larger circuit boards. It was a major improvement of the X-MP supporting up to eight processors. Parallel computing Parallel computing is a type of computation in which many calculations or processes are carried out simultaneously. Large problems can often be divided into smaller ones, which can then be solved at

2010-423: The 1970s until about 1986, speed-up in computer architecture was driven by doubling computer word size —the amount of information the processor can manipulate per cycle. Increasing the word size reduces the number of instructions the processor must execute to perform an operation on variables whose sizes are greater than the length of the word. For example, where an 8-bit processor must add two 16-bit integers ,

2077-614: The Cray-1M were renamed Cray X-MP/1s. This configuration was first used for Cray Research's UNIX port. In 1984, improved models of the X-MP were announced, consisting of one, two, and four-processor systems with 4 and 8 million word configurations. The top-end system was the X-MP/48, which contained four CPUs with a theoretical peak system performance of over 800 MFLOPS and 8 million words of memory. The CPUs in these models introduced vector gather/scatter memory reference instructions to

Cray X-MP - Misplaced Pages Continue

2144-484: The above program can be rewritten to use locks: One thread will successfully lock variable V, while the other thread will be locked out —unable to proceed until V is unlocked again. This guarantees correct execution of the program. Locks may be necessary to ensure correct program execution when threads must serialize access to resources, but their use can greatly slow a program and may affect its reliability . Locking multiple variables using non-atomic locks introduces

2211-443: The algorithm simultaneously with the others. The processing elements can be diverse and include resources such as a single computer with multiple processors, several networked computers, specialized hardware, or any combination of the above. Historically parallel computing was used for scientific computing and the simulation of scientific problems, particularly in the natural and engineering sciences , such as meteorology . This led to

2278-486: The amount of power used in a processor. Increasing processor power consumption led ultimately to Intel 's May 8, 2004 cancellation of its Tejas and Jayhawk processors, which is generally cited as the end of frequency scaling as the dominant computer architecture paradigm. To deal with the problem of power consumption and overheating the major central processing unit (CPU or processor) manufacturers started to produce power efficient processors with multiple cores. The core

2345-462: The available cores. However, for a serial software program to take full advantage of the multi-core architecture the programmer needs to restructure and parallelize the code. A speed-up of application software runtime will no longer be achieved through frequency scaling, instead programmers will need to parallelize their software code to take advantage of the increasing computing power of multicore architectures. Main article: Amdahl's law Optimally,

2412-460: The average time it takes to execute an instruction. An increase in frequency thus decreases runtime for all compute-bound programs. However, power consumption P by a chip is given by the equation P = C × V × F , where C is the capacitance being switched per clock cycle (proportional to the number of transistors whose inputs change), V is voltage , and F is the processor frequency (cycles per second). Increases in frequency increase

2479-444: The costs associated with merging data from multiple processes. Specifically, inter-process communication and synchronization can lead to overheads that are substantially higher—often by two or more orders of magnitude—compared to processing the same data on a single thread. Therefore, the overall improvement should be carefully evaluated. From the advent of very-large-scale integration (VLSI) computer-chip fabrication technology in

2546-400: The design of parallel hardware and software, as well as high performance computing . Frequency scaling was the dominant reason for improvements in computer performance from the mid-1980s until 2004. The runtime of a program is equal to the number of instructions multiplied by the average time per instruction. Maintaining everything else constant, increasing the clock frequency decreases

2613-497: The dominant paradigm in computer architecture , mainly in the form of multi-core processors . In computer science , parallelism and concurrency are two different things: a parallel program uses multiple CPU cores , each core performing a task independently. On the other hand, concurrency enables a program to deal with multiple tasks even on a single CPU core; the core switches between tasks (i.e. threads ) without necessarily completing each one. A program can have both, neither or

2680-457: The easiest to parallelize. Michael J. Flynn created one of the earliest classification systems for parallel (and sequential) computers and programs, now known as Flynn's taxonomy . Flynn classified programs and computers by whether they were operating using a single set or multiple sets of instructions, and whether or not those instructions were using a single set or multiple sets of data. The single-instruction-single-data (SISD) classification

2747-436: The first condition introduces a flow dependency, corresponding to the first segment producing a result used by the second segment. The second condition represents an anti-dependency, when the second segment produces a variable needed by the first segment. The third and final condition represents an output dependency: when two segments write to the same location, the result comes from the logically last executed segment. Consider

Cray X-MP - Misplaced Pages Continue

2814-551: The following functions, which demonstrate several kinds of dependencies: In this example, instruction 3 cannot be executed before (or even in parallel with) instruction 2, because instruction 3 uses a result from instruction 2. It violates condition 1, and thus introduces a flow dependency. In this example, there are no dependencies between the instructions, so they can all be run in parallel. Bernstein's conditions do not allow memory to be shared between different processes. For that, some means of enforcing an ordering between accesses

2881-415: The greatest obstacles to getting optimal parallel program performance. A theoretical upper bound on the speed-up of a single program as a result of parallelization is given by Amdahl's law , which states that it is limited by the fraction of time for which the parallelization can be utilised. Traditionally, computer software has been written for serial computation . To solve a problem, an algorithm

2948-547: The hardware supports parallelism. This classification is broadly analogous to the distance between basic computing nodes. These are not mutually exclusive; for example, clusters of symmetric multiprocessors are relatively common. A multi-core processor is a processor that includes multiple processing units (called "cores") on the same chip. This processor differs from a superscalar processor, which includes multiple execution units and can issue multiple instructions per clock cycle from one instruction stream (thread); in contrast,

3015-608: The introduction of 32-bit processors, which has been a standard in general-purpose computing for two decades. Not until the early 2000s, with the advent of x86-64 architectures, did 64-bit processors become commonplace. A computer program is, in essence, a stream of instructions executed by a processor. Without instruction-level parallelism, a processor can only issue less than one instruction per clock cycle ( IPC < 1 ). These processors are known as subscalar processors. These instructions can be re-ordered and combined into groups which are then executed in parallel without changing

3082-511: The memory on non-local processors. Accesses to local memory are typically faster than accesses to non-local memory. On the supercomputers , distributed shared memory space can be implemented using the programming model such as PGAS . This model allows processes on one compute node to transparently access the remote memory of another compute node. All compute nodes are also connected to an external shared memory system via high-speed interconnect, such as Infiniband , this external shared memory system

3149-442: The most common type of parallel programs. According to David A. Patterson and John L. Hennessy , "Some machines are hybrids of these categories, of course, but this classic model has survived because it is simple, easy to understand, and gives a good first approximation. It is also—perhaps because of its understandability—the most widely used scheme." Parallel computing can incur significant overhead in practice, primarily due to

3216-474: The number of cores per processor will double every 18–24 months. This could mean that after 2020 a typical processor will have dozens or hundreds of cores, however in reality the standard is somewhere in the region of 4 to 16 cores, with some designs having a mix of performance and efficiency cores (such as ARM's big.LITTLE design) due to thermal and design constraints. An operating system can ensure that different tasks and user programs are run in parallel on

3283-824: The overhead from resource contention or communication dominates the time spent on other computation, further parallelization (that is, splitting the workload over even more threads) increases rather than decreases the amount of time required to finish. This problem, known as parallel slowdown , can be improved in some cases by software analysis and redesign. Applications are often classified according to how often their subtasks need to synchronize or communicate with each other. An application exhibits fine-grained parallelism if its subtasks must communicate many times per second; it exhibits coarse-grained parallelism if they do not communicate many times per second, and it exhibits embarrassing parallelism if they rarely or never have to communicate. Embarrassingly parallel applications are considered

3350-452: The possibility of incorrect program execution. These computers require a cache coherency system, which keeps track of cached values and strategically purges them, thus ensuring correct program execution. Bus snooping is one of the most common methods for keeping track of which values are being accessed (and thus should be purged). Designing large, high-performance cache coherence systems is a very difficult problem in computer architecture. As

3417-495: The possibility of program deadlock . An atomic lock locks multiple variables all at once. If it cannot lock all of them, it does not lock any of them. If two threads each need to lock the same two variables using non-atomic locks, it is possible that one thread will lock one of them and the second thread will lock the second variable. In such a case, neither thread can complete, and deadlock results. Many parallel programs require that their subtasks act in synchrony . This requires

SECTION 50

#1732779842466

3484-564: The processor must first add the 8 lower-order bits from each integer using the standard addition instruction, then add the 8 higher-order bits using an add-with-carry instruction and the carry bit from the lower order addition; thus, an 8-bit processor requires two instructions to complete a single operation, where a 16-bit processor would be able to complete the operation with a single instruction. Historically, 4-bit microprocessors were replaced with 8-bit, then 16-bit, then 32-bit microprocessors. This trend generally came to an end with

3551-401: The processors in a typical distributed system run concurrently in parallel. Cray Y-MP The Cray Y-MP was a supercomputer sold by Cray Research from 1988, and the successor to the company's X-MP . The Y-MP retained software compatibility with the X-MP, but extended the address registers from 24 to 32 bits. High-density VLSI ECL technology was used and a new liquid-cooling system

3618-418: The product line. The amount of main memory supported was increased to a maximum of 16 million words, depending on the model. The main memory was built from bipolar or MOS SRAM ICs, depending on the model. The system initially ran the proprietary Cray Operating System (COS) and was object-code compatible with the Cray-1. A UNIX System V derivative initially named CX-OS and finally renamed UNICOS ran through

3685-629: The result of the program. This is known as instruction-level parallelism. Advances in instruction-level parallelism dominated computer architecture from the mid-1980s until the mid-1990s. All modern processors have multi-stage instruction pipelines . Each stage in the pipeline corresponds to a different action the processor performs on that instruction in that stage; a processor with an N -stage pipeline can have up to N different instructions at different stages of completion and thus can issue one instruction per clock cycle ( IPC = 1 ). These processors are known as scalar processors. The canonical example of

3752-440: The same time. There are several different forms of parallel computing: bit-level , instruction-level , data , and task parallelism . Parallelism has long been employed in high-performance computing , but has gained broader interest due to the physical constraints preventing frequency scaling . As power consumption (and consequently heat generation) by computers has become a concern in recent years, parallel computing has become

3819-473: The several execution units are not entire processors (i.e. processing units). Instructions can be grouped together only if there is no data dependency between them. Scoreboarding and the Tomasulo algorithm (which is similar to scoreboarding but makes use of register renaming ) are two of the most common techniques for implementing out-of-order execution and instruction-level parallelism. Task parallelisms

3886-432: The size of a problem. Superword level parallelism is a vectorization technique based on loop unrolling and basic block vectorization. It is distinct from loop vectorization algorithms in that it can exploit parallelism of inline code , such as manipulating coordinates, color channels or in loops unrolled by hand. Main memory in a parallel computer is either shared memory (shared between all processing elements in

3953-576: The use of a barrier . Barriers are typically implemented using a lock or a semaphore . One class of algorithms, known as lock-free and wait-free algorithms , altogether avoids the use of locks and barriers. However, this approach is generally difficult to implement and requires correctly designed data structures. Not all parallelization results in speed-up. Generally, as a task is split up into more and more threads, those threads spend an ever-increasing portion of their time communicating with each other or waiting on each other for access to resources. Once

4020-609: Was also available in variants with up to two, four or eight processors ( M92 , M94 and M98 respectively). Later, the model name was abbreviated to the Cray M90 series. The Y-MP C90 series is described separately. In 1992, Cray launched the cheaper Y-MP EL ( Entry Level ) model. This was a reimplementation of the Y-MP architecture in CMOS technology, based on the S-2 design acquired by Cray from Supertek Computers in 1990. The EL

4087-673: Was also supported. Each EA series CPU's peak performance was 234 MFLOPS. For a four-processor system, the peak performance was 942 MFLOPS. The Input/Output (I/O) subsystem could have two to four I/O processors with a total of 2 to 32 disk storage units. The DD-39 and DD-49 hard drives made by Ibis with a raw transfer rate of 13.3 MB/s each stored 1200 megabyte (blocked and formatted) with 5.9 MB/s and 9.8 MB/s transfer rates (unstriped), respectively. Optional solid-state drives were available with 256, 512 or 1024 MB capacities with transfer rates of 100 to 1,000 MB/s per channel. Up to 38 gigabytes of data storage

SECTION 60

#1732779842466

4154-573: Was an air-cooled system with a completely different VMEbus -based IOS. EL configurations with up to four processors (each with a peak performance of 133 megaflops) and 32 MB to 1 GB of DRAM were available. The Y-MP EL was later developed into the Cray EL90 series ( EL92 , EL94 and EL98 ). The Y-MP EL came in a cabinet much smaller than the traditional room-filling Cray 2010×1270×810 mm (height × width × depth) and 635 kg in weight—and could be powered from regular mains power. In

4221-426: Was built from macrocell array and gate array ICs. The EA series extended the width of the A and B registers to 32 bits and performed 32-bit address arithmetic, increasing the amount of memory theoretically addressable to 2 billion words. The largest configuration produced was 64 million words of MOS SRAM in 64 banks. For compatibility with existing software written for the Cray-1 and older X-MP models, 24-bit addressing

4288-517: Was devised. The Y-MP ran the Cray UNICOS operating system . The Y-MP could be equipped with two, four or eight vector processors , with two functional units each and a clock cycle time of 6 ns (167 MHz). Peak performance was thus 333 megaflops per processor. Main memory comprised 128, 256 or 512 MB of SRAM . The original Y-MP (otherwise known as the Y-MP Model D ) was housed in

4355-437: Was possible. For magnetic tape I/O, the system could interface with IBM 3420 and 3480 tape units directly without a lot of CPU processing. A 1984 X-MP/48 cost about US$ 15 million plus the cost of disks . In 1985 Bell Labs purchased a Cray X-MP/24 for $ 10.5 million along with eight DD-49 1.2 GB drives for an additional $ 1 million. They received $ 1.5 million of trade-in credit for their Cray-1. The Cray-2 ,

4422-457: Was superseded in 1990 by the Y-MP Model E , which replaced IOS Model D with IOS Model E , providing twice the I/O throughput. The Y-shaped chassis was dropped in favor of one or two rectangular cabinets (each with a separate connected cabinet containing the liquid-cooling system), depending on configuration. Maximum RAM was increased to 2 GB and up to eight IOSs were possible. Model E variants included

4489-524: Was very similar to the Cray-1 CPU in architecture, but had better memory bandwidth (with two read ports and one write port to the main memory instead of only one read/write port) and improved chaining support. Each CPU had a theoretical peak performance of 200 MFLOPS. The X-MP initially supported 2 million 64-bit words (16 MB) of main memory in 16 banks, respectively. The main memory was built from 4 Kbit bipolar SRAM ICs. CMOS memory versions of

#465534