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20-536: The A8 is manufactured on a 20 nm process by TSMC , which replaced Samsung as the manufacturer of Apple's mobile device processors. It contains 2 billion transistors. Despite having twice the number of transistors of the A7, the A8's physical size has been reduced by 13% to 89 mm (0.138 in). The A8 uses LPDDR3-1333 RAM on a 64-bit memory interface; in the iPhone 6/6 Plus, sixth generation iPod Touch , and HomePod ,

40-692: A 1998 patent. On October 14, 2015, a district judge found Apple guilty of infringing U.S. patent US 5781752   , "Table based data speculation circuit for parallel processing computer", on the Apple A7 and A8 processors. The patent is owned by Wisconsin Alumni Research Foundation (WARF), a firm affiliated with the University of Wisconsin . On July 24, 2017, Apple was ordered to pay WARF $ 506 million for patent infringement. Apple filed an appellate brief on October 26, 2017, with

60-401: A 22 nm SOI process. International Technology Roadmap for Semiconductors The International Technology Roadmap for Semiconductors ( ITRS ) is a set of documents that was coordinated and organized by Semiconductor Research Corporation and produced by a group of experts in the semiconductor industry . These experts were representative of the sponsoring organisations, including

80-540: A key element of the technology and associated supply chain. Traditionally, the ITRS roadmap was updated in even years, and completely revised in odd years. The last revision of the ITRS Roadmap was published in 2013 . The methodology and the physics behind the scaling results for 2013 tables is described in transistor roadmap projection using predictive full-band atomistic modeling which covers double gate MOSFETs over

100-667: Is a 4-shader-cluster PowerVR Series 6XT . However the GPU features custom shader cores designed by Apple. On October 16, 2014, Apple introduced a variant of the A8, the A8X , in the iPad Air 2 . Compared with the A8, the A8X has an enhanced 8-shader-cluster GPU and improved CPU performance due to one extra core and higher frequency. The A8 has video codec encoding support for H.264 . It has decoding support for H.264, MPEG‑4 , and Motion JPEG . The A8's branch predictor has been claimed to infringe on

120-461: Is dual core, and as used in the iPhone 6 has a frequency of 1.4 GHz, supporting Apple's claim of it being 25% faster than the A7 . It also supports the notion of this being a second generation enhanced Cyclone core called Typhoon , and not an entirely new architecture which would supposedly mean a more significant performance gain per Hz. The A8 also integrates a graphics processing unit (GPU) which

140-490: The Intel Ivy Bridge processors. Since at least 1997, "process nodes" have been named purely on a marketing basis, and have no relation to the dimensions on the integrated circuit; neither gate length, metal pitch or gate pitch on a "22nm" device is twenty-two nanometers. The ITRS 2006 Front End Process Update indicates that equivalent physical oxide thickness will not scale below 0.5 nm (about twice

160-707: The Semiconductor Industry Associations of Taiwan , South Korea , the United States, Europe, Japan , and China. As of 2017, ITRS is no longer being updated. Its successor is the International Roadmap for Devices and Systems . The documents carried disclaimer: "The ITRS is devised and intended for technology assessment only and is without regard to any commercial considerations pertaining to individual products or equipment". The documents represent best opinion on

180-777: The U.S. Court of Appeals for the Federal Circuit , that argued that Apple did not infringe on the patent owned by the Wisconsin Alumni Research Foundation. On September 28, 2018, the ruling was overturned on appeal and the award thrown out by the U.S. Federal Circuit Court of Appeals. The patent expired in December 2016. 22 nanometer The "22 nm" node is the process step following 32 nm in CMOS MOSFET semiconductor device fabrication . The typical half-pitch (i.e., half

200-466: The 15 years to 2028. With the generally acknowledged sunsetting of Moore's law and, ITRS issuing in 2016 its final roadmap, a new initiative for a more generalized roadmapping was started through the IEEE's Rebooting Computing initiative, named the International Roadmap for Devices and Systems (IRDS). In April 2014, the ITRS committee announced it would be reorganizing the ITRS roadmap to better suit

220-444: The A8 has 1 GB RAM included in the package. Meanwhile, the A8 in the iPad Mini 4 and 4th generation Apple TV is packaged with 2 GB RAM. The A8 CPU has a per-core L1 cache of 64  KB for data and 64 KB for instructions, an L2 cache of 1  MB shared by both CPU cores, and a 4 MB L3 cache that services the entire SoC. As its predecessor, it has a 6 decode, 6 issue, 9 wide, out-of-order design. The processor

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240-484: The SIA became closer to its European, Japanese, Korean, and Taiwanese counterparts by creating the first global roadmap: The International Technology Roadmap for Semiconductors (ITRS). This international group has (as of the 2003 edition) 936 companies which were affiliated with working groups within the ITRS. The organization was divided into Technical Working Groups (TWGs) which eventually grew in number to 17, each focusing on

260-399: The diameter of a silicon atom ), which is the expected value at the 22 nm node. This is an indication that CMOS scaling in this area has reached a wall at this point, possibly disturbing Moore's law . The 20-nanometre node is an intermediate half-node die shrink based on the 22-nanometre process. TSMC began mass production of 20   nm nodes in 2014. The 22 nm process

280-475: The directions of research and time-lines up to about 15 years into the future for the following areas of technology: Constructing an integrated circuit , or any semiconductor device, requires a series of operations—photolithography, etching, metal deposition, and so on. As the industry evolved, each of these operations were typically performed by specialized machines built by a variety of commercial companies. This specialization may potentially make it difficult for

300-542: The distance between identical features in an array) for a memory cell using the process is around 22  nm . It was first demonstrated by semiconductor companies for use in RAM memory in 2008. In 2010, Toshiba began shipping 24 nm flash memory chips, and Samsung Electronics began mass-producing 20 nm flash memory chips. The first consumer-level CPU deliveries using a 22 nm process started in April 2012 with

320-400: The industry to advance, since in many cases it does no good for one company to introduce a new product if the other needed steps are not available around the same time. A technology roadmap can help this by giving an idea when a certain capability will be needed. Then each supplier can target this date for their piece of the puzzle. With the progressive externalization of production tools to

340-399: The second half of 2011. SRAM cell size is said to be 0.092 μm , smallest reported to date. On January 3, 2010, Intel and Micron Technology announced the first in a family of 25 nm NAND devices. On May 2, 2011, Intel announced its first 22 nm microprocessor, codenamed Ivy Bridge , using a FinFET technology called 3-D tri-gate . IBM's POWER8 processors are produced in

360-626: The suppliers of specialized equipment, participants identified a need for a clear roadmap to anticipate the evolution of the market and to plan and control the technological needs of IC production. For several years, the Semiconductor Industry Association (SIA) gave this responsibility of coordination to the United States, which led to the creation of an American style roadmap, the National Technology Roadmap for Semiconductors (NTRS). In 1998,

380-512: Was printed using immersion lithography . The 22 nm node may be the first time where the gate length is not necessarily smaller than the technology node designation. For example, a 25 nm gate length would be typical for the 22 nm node. On September 22, 2009, during the Intel Developer Forum Fall 2009 , Intel showed a 22 nm wafer and announced that chips with 22 nm technology would be available in

400-480: Was superseded by commercial 14 nm FinFET technology in 2014. On August 18, 2008, AMD , Freescale , IBM , STMicroelectronics , Toshiba , and the College of Nanoscale Science and Engineering (CNSE) announced that they jointly developed and manufactured a 22 nm SRAM cell, built on a traditional six- transistor design on a 300 mm wafer , which had a memory cell size of just 0.1 μm . The cell

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