Intrinsity was a privately held Austin, Texas based fabless semiconductor company ; it was founded in 1997 as EVSX on the remnants of Exponential Technology and changed its name to Intrinsity in 2000. It had around 100 employees and supplied tools and services for highly efficient semiconductor logic design, enabling high performance microprocessors with fewer transistors and low power consumption. The acquisition of the firm by Apple Inc. was confirmed on April 27, 2010.
24-488: Intrinsity's main selling point was its Fast14 technology, a set of design tools implemented in custom EDA software, for using dynamic logic and novel signal encodings to permit greater processor speeds in a given process than naive static design can offer. Concepts used in Fast14 are described in a white paper: and include the use of multi-phase clocks so that synchronisation is not required at every cycle boundary (that is,
48-422: A design flow that chip designers use to design and analyze entire semiconductor chips. Since a modern semiconductor chip can have billions of components, EDA tools are essential for their design; this article in particular describes EDA specifically with respect to integrated circuits (ICs). The earliest electronic design automation is attributed to IBM with the documentation of its 700 series computers in
72-574: A 1 GHz implementation of the ARM Cortex-A8 chip; it had developed a similar high-speed implementation of the Cortex-R4 chip two years earlier. Electronic design automation Electronic design automation ( EDA ), also referred to as electronic computer-aided design ( ECAD ), is a category of software tools for designing electronic systems such as integrated circuits and printed circuit boards . The tools work together in
96-458: A business. Daisy Systems , Mentor Graphics and Valid Logic Systems were all founded around this time and collectively referred to as DMV. In 1981, the U.S. Department of Defense additionally began funding of VHDL as a hardware description language. Within a few years, there were many companies specializing in EDA, each with a slightly different emphasis. The first trade show for EDA was held at
120-477: A constant speed, regardless of activity in the model. Optimized implementations may take advantage of low model activity to speed up simulation by skipping evaluation of gates whose inputs didn't change. In comparison to event simulation, cycle simulation tends to be faster, to scale better, and to be better suited for hardware acceleration / emulation. However, chip design trends point to event simulation gaining relative performance due to activity factor reduction in
144-530: A large number of projects per wafer , with several copies of chips from each project remaining preserved. Cooperating fabricators either donated the processed wafers or sold them at cost, as they saw the program as helpful to their own long-term growth. 1981 marked the beginning of EDA as an industry. For many years, the larger electronic companies, such as Hewlett-Packard , Tektronix and Intel , had pursued EDA internally, with managers and developers beginning to spin out of these companies to concentrate on EDA as
168-409: A pipelined design does not require latches at every clock cycle); 1-of-N encoding where a signal with N states is carried as a voltage on one of N wires with the other N-1 grounded, rather than being carried on log(N) wires which can be in arbitrary states; and a variety of sophisticated routing algorithms including ones which permute the order of the wires in a bundle carrying a 1-of-N signal in such
192-426: A way as to reduce noise exposure, and ones which allow complicated gates to 'borrow' delay from simple ones to allow a shorter clock cycle than a more pessimistic design approach permits. Converters between the two signal encodings are readily available, and are useful for interfacing to blocks of static logic. This technology has been used to implement ARM , MIPS and Power ISA cores, which Intrinsity licences under
216-443: Is the use of simulation software to predict the behavior of digital circuits and hardware description languages . Simulation can be performed at varying degrees of physical abstraction , such as at the transistor level , gate level , register-transfer level (RTL), electronic system-level (ESL), or behavioral level. Logic simulation may be used as part of the verification process in designing hardware. Simulations have
240-747: The Design Automation Conference in 1984 and in 1986, Verilog , another popular high-level design language, was first introduced as a hardware description language by Gateway Design Automation . Simulators quickly followed these introductions, permitting direct simulation of chip designs and executable specifications. Within several years, back-ends were developed to perform logic synthesis . Current digital flows are extremely modular, with front ends producing standardized design descriptions that compile into invocations of units similar to cells without regard to their individual technology. Cells implement logic or other electronic functions via
264-497: The Espresso heuristic logic minimizer , responsible for circuit complexity reductions and Magic , a computer-aided design platform. Another crucial development was the formation of MOSIS , a consortium of universities and fabricators that developed an inexpensive way to train student chip designers by producing real integrated circuits. The basic concept was to use reliable, low-cost, relatively low-technology IC processes and pack
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#1732801310590288-445: The 1950s. Prior to the development of EDA, integrated circuits were designed by hand and manually laid out. Some advanced shops used geometric software to generate tapes for a Gerber photoplotter , responsible for generating a monochromatic exposure image, but even those copied digital recordings of mechanically drawn components. The process was fundamentally graphic, with the translation from electronics to graphics done manually;
312-409: The advantage of providing a familiar look and feel to the user in that it is constructed from the same language and symbols used in design. By allowing the user to interact directly with the design, simulation is a natural way for the designer to get feedback on their design. The level of effort required to debug and then verify the design is proportional to the maturity of the design. That is, early in
336-408: The best-known company from this era was Calma , whose GDSII format is still in use today. By the mid-1970s, developers started to automate circuit design in addition to drafting and the first placement and routing tools were developed; as this occurred, the proceedings of the Design Automation Conference catalogued the large majority of the developments of the time. The next era began following
360-504: The circuit on a field-programmable gate array instead. Formal verification can also be explored as an alternative to simulation, although a formal proof is not always possible or convenient. A prospective way to accelerate logic simulation is using distributed and parallel computations. To help gauge the thoroughness of a simulation, tools exist for assessing code coverage , functional coverage, finite state machine (FSM) coverage, and many other metrics. Event simulation allows
384-940: The components are, in general, less ideal. EDA for electronics has rapidly increased in importance with the continuous scaling of semiconductor technology. Some users are foundry operators, who operate the semiconductor fabrication facilities ("fabs") and additional individuals responsible for utilising the technology design-service companies who use EDA software to evaluate an incoming design for manufacturing readiness. EDA tools are also used for programming design functionality into FPGAs or field-programmable gate arrays, customisable integrated circuit designs. Design flow primarily remains characterised via several primary components; these include: Market capitalization and company name as of March 2023: Market capitalization and company name as of December 2011 : Many EDA companies acquire small companies with software or other technology that can be adapted to their core business. Most of
408-400: The design to contain simple timing information – the delay needed for a signal to travel from one place to another. During simulation, signal changes are tracked in the form of events. A change at a certain time triggers an event after a certain delay. Events are sorted by the time when they will occur, and when all events for a particular time have been handled, the simulated time is advanced to
432-480: The design's life, bugs and incorrect behavior are usually found quickly. As the design matures, the simulation will require more time and resources to run, and errors will take progressively longer to be found. This is particularly problematic when simulating components for modern-day systems; every component that changes state in a single clock cycle on the simulation will require several clock cycles to simulate. A straightforward approach to this issue may be to emulate
456-425: The languages and tools have evolved, this general approach of specifying the desired behavior in a textual programming language and letting the tools derive the detailed physical design remains the basis of digital IC design today. The earliest EDA tools were produced academically. One of the most famous was the "Berkeley VLSI Tools Tarball", a set of UNIX utilities used to design early VLSI systems. Widely used were
480-435: The market leaders are amalgamations of many smaller companies and this trend is helped by the tendency of software companies to design tools as accessories that fit naturally into a larger vendor's suite of programs on digital circuitry ; many new tools incorporate analog design and mixed systems. This is happening due to a trend to place entire electronic systems on a single chip . Logic simulation Logic simulation
504-498: The name of FastCores ; the first implementation was FastMATH , a MIPS -based DSP -like microprocessor implemented in 130 nm technology and introduced in 2002. It operates at 15 W power at 2.0 GHz and 1 V, and 6 W power at 1 GHz and 0.85 V; it was awarded Best Extreme Processor in 2003 by Microprocessor Report . The design took 16 months by a team of 45 engineers. In July 2009, Intrinsity announced that it had developed in collaboration with Samsung
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#1732801310590528-470: The publication of "Introduction to VLSI Systems" by Carver Mead and Lynn Conway in 1980; considered the standard textbook for chip design. The result was an increase in the complexity of the chips that could be designed, with improved access to design verification tools that used logic simulation . The chips were easier to lay out and more likely to function correctly, since their designs could be simulated more thoroughly prior to construction. Although
552-461: The time of the next scheduled event. How fast an event simulation runs depends on the number of events to be processed (the amount of activity in the model). While event simulation can provide some feedback regarding signal timing, it is not a replacement for static timing analysis . In cycle simulation, it is not possible to specify delays. A cycle-accurate model is used, and every gate is evaluated in every cycle. Cycle simulation therefore runs at
576-481: The utilisation of a particular integrated circuit technology. Fabricators generally provide libraries of components for their production processes, with simulation models that fit standard simulation tools. Most analog circuits are still designed in a manual fashion, requiring specialist knowledge that is unique to analog design (such as matching concepts). Hence, analog EDA tools are far less modular, since many more functions are required, they interact more strongly and
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