Misplaced Pages

#458541

24-571: The Open Core Protocol ( OCP ) is a protocol for on-chip subsystem communications. It is an openly licensed, core-centric protocol and defines a bus-independent, configurable interface. OCP International Partnership ( OCP-IP ) produces OCP specifications. OCP data transfer models range from simple request-grant handshaking through pipelined request-response to complex out-of-order operations. Legacy IP cores can be adapted to OCP, while new implementations may take advantage of advanced features: designers select only those features and signals encompassing

48-492: A digital signal processor (DSP) is developed from soft cores of RTL format, and it can be targeted to various technologies or different foundries to yield different implementations. The process of IP hardening is from soft core to generate re-usable hard (hardware) cores . A main advantage of such hard IP is its predictable characteristics as the IP has been pre-implemented, while it offers flexibility of soft cores. It might come with

72-467: A chip (SoC) products. This initiative comprehensively fulfills system-level integration requirements by promoting IP core reusability and reducing design time, risk and manufacturing costs for SoC designs. Design teams developing consumer, data processing , telecom (wireless or wired), datacom and mass storage applications can gain significant benefits from the OCP-IP solution. Corporate members have

96-651: A core's specific data, control and test configuration. The Open Core Protocol (OCP) is one of several FPGA processor interconnects used to connect soft FPGA peripherals to FPGA CPUs—both soft microprocessor and hard-macro processor . Other such interconnects include Advanced eXtensible Interface (AXI), Avalon , and the Wishbone bus . FPGA vendor Altera joined the Open Core Protocol International Partnership in 2010. OCP International Partnership In 2000, Accellera

120-428: A discrete integrated circuit component for printed circuit board design. Each is a reusable component of design logic with a defined interface and behavior that has been verified by its creator and is integrated into a larger design. IP cores are commonly offered as synthesizable RTL in a hardware description language such as Verilog or VHDL . These are analogous to low-level languages such as C in

144-523: A language for describing registers in components. SPIRIT stood for "Structure for Packaging, Integrating and Re-using IP within Tool-flows". In June 2009 it was announced that SPIRIT would merge with Accellera. There were four levels of membership in the SPIRIT consortium. The Board of Directors (BoD) was the ruling body. Members around the time of the merge were: Contributing members performed

168-527: A lower-level physical description that is specific to a particular process technology. Hard cores usually offer better predictability of chip timing performance and area for their particular technology. Analog and mixed-signal logic are generally distributed as hard cores. Hence, analog IP ( SerDes , PLLs , DAC , ADC , PHYs , etc.) are provided to chip makers in transistor-layout format (such as GDSII ). Digital IP cores are sometimes offered in layout format as well. Low-level transistor layouts must obey

192-483: A right to be eligible for election to the Board of Directors. Associate member companies have voting rights in all of Accellera's Technical Working Groups. The following EDA standards developed by Accellera were ratified by IEEE by 2019: The following EDA initiatives were developed by Accellera: IP core In electronic design , a semiconductor intellectual property core ( SIP core ), IP core or IP block

216-536: A set of models for simulations for verification. The effort to harden soft IP requires employing the quality of the target technology, goals of design and the methodology. The hard IP has been proven in the target technology and application. E.g. the hard core in GDS II format is said to clean in DRC ( design rule checking ), and LVS (see Layout versus schematic ). I.e. that can pass all the rules required for manufacturing by

240-572: Is a reusable unit of logic, cell, or integrated circuit layout design that is the intellectual property of one party. IP cores can be licensed to another party or owned and used by a single party. The term comes from the licensing of the patent or source code copyright that exists in the design. Designers of system on chip (SoC), application-specific integrated circuits (ASIC) and systems of field-programmable gate array (FPGA) logic can use IP cores as building blocks. The licensing and use of IP cores in chip design came into common practice in

264-521: Is analogous to an assembly code listing in the field of computer programming. A netlist gives the IP core vendor reasonable protection against reverse engineering. See also Integrated circuit layout design protection . Both netlist and synthesizable cores are called soft cores since both allow a synthesis , placement and routing ( SPR ) design flow. Hard cores (or hard macros) are analog or digital IP cores whose function cannot be significantly modified by chip designers. These are generally defined as

SECTION 10

#1732791662459

288-866: The 8051 and PIC , to 32-bit and 64-bit processors such as the ARM architectures or RISC-V architectures . Such processors form the "brains" of many embedded systems . They are usually RISC instruction sets rather than CISC instruction sets like x86 because less logic is required. Therefore, designs are smaller. Further, x86 leaders Intel and AMD heavily protect their processor designs' intellectual property and don't use this business model for their x86-64 lines of microprocessors . IP cores are also licensed for various peripheral controllers such as for PCI Express , SDRAM , Ethernet , LCD display , AC'97 audio, and USB . Many of those interfaces require both digital logic and analog IP cores to drive and receive high speed, high voltage, or high impedance signals outside of

312-587: The Open Core Protocol (OCP) standard, the intellectual property of the OCP International Partnership (OCP-IP). The SPIRIT Consortium was a group of vendors and users of electronic design automation (EDA) tools, defining standards for the exchange of System-on-a-chip (SoC) design information. The standards defined included IP-XACT , an XML schema for vendor-neutral descriptions of design components, and SystemRDL ,

336-440: The star IP , include ARM Holdings and Synopsys . Gartner Group estimated the total value of sales related to silicon intellectual property at US $ 1.5 billion in 2005 with annual growth expected around 30%. IP hardening is a process to re-use proven designs and generate fast time-to-market, low-risk-in-fabrication solutions to provide intellectual property (IP) (or silicon intellectual property) of design cores. For example,

360-424: The 1990s. There were many licensors and also many foundries competing on the market. In 2013, the most widely licensed IP cores were from Arm Holdings (43.2% market share), Synopsys Inc. (13.9% market share), Imagination Technologies (9% market share) and Cadence Design Systems (5.1% market share). The use of an IP core in chip design is comparable to the use of a library for computer programming or

384-612: The SystemRDL Alliance and then developed IP-XACT . The merger was completed in April 2010. SPIRIT stood for "Structure for Packaging, Integrating and Re-using IP within Tool-flows". In December 2011, Accellera and the Open SystemC Initiative (OSCI) approved their merger, adopting the name Accellera Systems Initiative (Accellera) while continuing to develop SystemC . In October 2013, Accellera acquired

408-476: The chip. "Hardwired" (as opposed to software programmable soft microprocessors described above) digital logic IP cores are also licensed for fixed functions such as MP3 audio decode, 3D GPU , digital video encode/decode, and other DSP functions such as FFT , DCT , or Viterbi coding. IP core developers and licensors range in size from individuals to multi-billion-dollar corporations. Developers, as well as their chip-making customers, are located throughout

432-473: The customers are semiconductor companies or module developers with in-house semiconductor development. A company wishing to fabricate a complex device may license in the rights to use another company's well-tested functional blocks such as a microprocessor , instead of developing their own design, which would require additional time and cost. The silicon IP industry has had stable growth for many years. The most successful silicon IP companies, often referred to as

456-549: The field of computer programming. IP cores delivered to chip designers as RTL permit chip designers to modify designs at the functional level, though many IP vendors offer no warranty or support for modified designs. IP cores are also sometimes offered as generic gate-level netlists . The netlist is a Boolean-algebra representation of the IP's logical function implemented as generic gates or process -specific standard cells . An IP core implemented as generic gates can be compiled for any process technology. A gate-level netlist

480-481: The standardization work and donate time and effort to the production of new specifications. Reviewing member status was a free membership for companies. These get early access to specifications to facilitate a deep review round of each proposal before it goes public. Associate member status was similar to a reviewing membership but for academics and other not-for-profit organizations. The Open Core Protocol International Partnership Association, Inc. ( OCP-IP )

504-489: The target foundry 's process design rules. Therefore, hard cores delivered for one foundry's process cannot be easily ported to a different process or foundry. Merchant foundry operators (such as IBM , Fujitsu , Samsung , TI , etc.) offer various hard-macro IP functions built for their own foundry processes, helping to ensure customer lock-in . Many of the best known IP cores are soft microprocessor designs. Their instruction sets vary from small 8-bit processors, such as

SECTION 20

#1732791662459

528-429: The world. Silicon intellectual property ( SIP , silicon IP ) is a business model for a semiconductor company where it licenses its technology to a customer as intellectual property . A company with such a business model is a fabless semiconductor company , which doesn't provide physical chips to its customers but merely facilitates the customer's development of chips by offering certain functional blocks. Typically,

552-453: Was an independent, non-profit semiconductor industry consortium formed to administer the support, promotion and enhancement of the Open Core Protocol (OCP). OCP was the first fully supported, openly licensed, comprehensive, interface socket for semiconductor intellectual property (IP) cores. The mission of OCP-IP was to address problems relating to design, verification, and testing which are common to IP core reuse in " plug and play " system on

576-414: Was founded from the merger of Open Verilog International (OVI) and VHDL International , the developers of Verilog and VHDL respectively. Both were originally formed nine years earlier in 1991. In June 2009, a merger was announced between Accellera and The SPIRIT Consortium , another major EDA standards organization focused on IP deployment and reuse. The SPIRIT Consortium obtained SystemRDL from

#458541