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60-873: MMU may refer to: Science and technology [ edit ] Memory management unit , a computer component Manned Maneuvering Unit , a NASA spacesuit rocket pack Milli mass unit , an unofficial unit of mass Minimum Mapping Unit , a spatial measure used in remote sensing and cartography Education [ edit ] Manchester Metropolitan University , in England Marymount University , in Arlington, Virginia Mount Mansfield Union High School , in Jericho, Vermont Mount Meru University , in Tanzania Mountains of

120-441: A 1 KB tiny page. ARM uses a two-level page table if using 4 KB and 64 KB pages, or just a one-level page table for 1 MB sections and 16 MB sections. TLB updates are performed automatically by page table walking hardware. PTEs include read/write access permission based on privilege, cacheability information, an NX bit , and a non-secure bit. DEC Alpha processors divide memory into 8 KB , 16 KB , 32 KB , or 64 KB ;

180-424: A page table , containing one page table entry (PTE) per virtual page, to map virtual page numbers to physical page numbers in main memory. Multi-level page tables are often used to reduce the size of the page table. An associative cache of PTEs is called a translation lookaside buffer (TLB) and is used to avoid the necessity of accessing the main memory every time a virtual address is mapped. Other MMUs may have

240-426: A 16-bit address that made it too small as memory sizes increased in the 1970s. This was addressed by expanding the physical memory bus to 18-bits, and using an MMU to add two more bits based on other pins on the processor bus to indicate which program was accessing memory. Another use of this same technique, although not referred to as paging but bank switching , was widely used by early 8-bit microprocessors like

300-408: A TLB exception occurs when processing a TLB exception, a double fault TLB exception, it is dispatched to its own exception handler . MIPS32 and MIPS32r2 support 32 bits of virtual address space and up to 36 bits of physical address space. MIPS64 supports up to 64 bits of virtual address space and up to 59 bits of physical address space. The original Sun-1 is a single-board computer built around

360-646: A context is 1024 pages or 2 MB. The maximum physical address that can be mapped simultaneously is also 2 MB. The context register is important in a multitasking operating system because it allows the CPU to switch between processes without reloading all the translation state information. The 4-bit context register can switch between 16 sections of the segment map under supervisor control, which allows 16 contexts to be mapped concurrently. Each context has its own virtual address space. Sharing of virtual address space and inter-context communications can be provided by writing

420-462: A contiguous series of fixed-sized blocks. This is similar to the modern demand paging system in that the result is a series of pages, but in these earlier systems the list of pages is fixed in size and normally stored in some form of fast memory like static RAM to improve performance. In this case, the two parts of the address stored by the MMU are known as the segment number and page index . Consider

480-461: A fault on write bit. The MIPS architecture supports one to 64 entries in the TLB. The number of TLB entries is configurable at CPU configuration before synthesis. TLB entries are dual. Each TLB entry maps a virtual page number (VPN2) to either one of two page frame numbers (PFN0 or PFN1), depending on the least significant bit of the virtual address that is not part of the page mask . This bit and

540-442: A fixed set of blocks instead of loading them on demand. The difference between these two approaches is the size of the contiguous block of memory; paged systems break up main memory into a series of equal sized blocks, while segmented systems generally allow for variable sizes. Early memory management systems, often implemented in software, set aside a portion of memory to hold a series of mappings. These consisted of pairs of values,

600-511: A game by Capcom Milli Muharip Uçak , a Turkish fighter aircraft in development Topics referred to by the same term [REDACTED] This disambiguation page lists articles associated with the title MMU . If an internal link led you here, you may wish to change the link to point directly to the intended article. Retrieved from " https://en.wikipedia.org/w/index.php?title=MMU&oldid=1187368860 " Category : Disambiguation pages Hidden categories: Short description

660-418: A list of page number originally expressed by the program and the actual page number in main memory. When it attempts to access memory, the MMU reads the segment number from the processor's memory bus, finds the corresponding entry for that program in its internal memory, and expresses the mapped version of the value on the memory's bus while the lower bits of the original address are passed through unchanged. Like

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720-433: A page table entry or other per-page information prohibits access to a particular virtual page, perhaps because no physical random-access memory (RAM) has been allocated to that virtual page. In this case, the MMU signals a page fault to the CPU. The operating system (OS) then handles the situation, perhaps by trying to find a spare frame of RAM and set up the page map to map it to the requested virtual address. If no RAM

780-438: A private array of memory, registers, or static RAM that holds a set of mapping information. The virtual page number may be directly used as an index into the page table or other mapping information, or it may be further divided, with bits at a given level used as an index into a table of lower-level tables into which bits at the next level down are used as an index, with two or more levels of indexing. The physical page number

840-481: A processor design with 24-bit addressing, like the original Motorola 68000 . In such a system, the MMU splits the virtual address into parts, for instance, the 13 least significant bits for the page index and the remaining 11 most significant bits as the segment number. This results a list of 2048 pages of 8 kB each. In this approach, memory requests result in one or more pages being granted to that program, which may not be contiguous in main memory. The MMU maintains

900-440: A program to access memory it has not previously requested, which prevents a misbehaving program from using up all memory or malicious code from reading data from another program. They also often manage a processor cache , which stores recently accessed data in a very fast memory and thus reduces the need to talk to the slower main memory. In some implementations, they are also responsible for bus arbitration , controlling access to

960-562: A request, but this is spread out and cannot be allocated. On systems where programs start and stop over time, this can eventually lead to memory being highly fragmented and no large blocks remaining. A number of algorithms were developed to address this problem. Segmenting was widely used on microcomputer platforms of the 1980s. Among the MMUs that used this concept were the Motorola 68451 and Signetics 68905, but many other examples exist. It

1020-785: A set of bits to index the root level of the tree, a set of bits to index the middle level of the tree, a set of bits to index the leaf level of the tree, and remaining bits that pass through to the physical address without modification, indexing a byte within the page. The sizes of the fields are dependent on the page size; all three tree index fields are the same size. The OpenVMS AXP PALcode supports full read and write permission bits for user, supervisor, executive, and kernel modes, and also supports fault on read/write/execute bits are also supported. The DEC OSF/1 PALcode supports full read and write permission bits for user and kernel modes, and also supports fault on read/write/execute bits are also supported. The Windows NT AXP PALcode can either walk

1080-473: A set of bits to index the root level of the tree, a set of bits to index the top level of the tree, a set of bits to index the leaf level of the tree, and remaining bits that pass through to the physical address without modification, indexing a byte within the page. The sizes of the fields are dependent on the page size. The Windows NT AXP PALcode supports a page being accessible only from kernel mode or being accessible from user and kernel mode, and also supports

1140-427: A single-level page table in a virtual address space or a two-level page table in physical address space. The upper 32 bits of an address are ignored. For a single-level page table, addresses are broken down into a set of bits to index the page table and remaining bits that pass through to the physical address without modification, indexing a byte within the page. For a two-level page table, addresses are borken down into

1200-487: A uniform fashion. The MMU is implemented in hardware on the CPU board. The MMU consists of a context register, a segment map and a page map. Virtual addresses from the CPU are translated into intermediate addresses by the segment map, which in turn are translated into physical addresses by the page map. The page size is 2 KB and the segment size is 32 KB which gives 16 pages per segment. Up to 16 contexts can be mapped concurrently. The maximum logical address space for

1260-456: Is a method of virtual memory management. In a system that uses demand paging, the operating system copies a disk page into physical memory only when an attempt is made to access it and that page is not already in memory ( i.e. , if a page fault occurs). It follows that a process begins execution with none of its pages in physical memory, and triggers many page faults until most of its working set of pages are present in physical memory. This

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1320-471: Is an example of a lazy loading technique. Demand paging only brings pages into memory when an executing process demands them. This is often referred to as lazy loading , as only those pages demanded by the process are swapped from secondary storage to main memory . Contrast this to pure swapping, where all memory for a process is swapped from secondary storage to main memory when the process starts up or resumes execution. Commonly, to achieve this process

1380-454: Is combined with the page offset to give the complete physical address. A page table entry or other per-page information may also include information about whether the page has been written to (the dirty bit ), when it was last used (the accessed bit , for a least recently used (LRU) page replacement algorithm ), what kind of processes ( user mode or supervisor mode ) may read and write it, and whether it should be cached . Sometimes,

1440-403: Is different from Wikidata All article disambiguation pages All disambiguation pages Memory management unit In modern systems, programs generally have addresses that access the theoretical maximum memory of the computer architecture , 32 or 64 bits. The MMU maps the addresses from each program into separate areas in physical memory, which is generally much smaller than

1500-552: Is free, it may be necessary to choose an existing page (known as a victim ), using some replacement algorithm , and save it to disk (a process called paging ). With some MMUs, there can also be a shortage of PTEs, in which case the OS will have to free one for the new mapping. The MMU may also generate illegal access error conditions or invalid page faults upon illegal or non-existing memory accesses, respectively, leading to segmentation fault or bus error conditions when handled by

1560-446: Is one of the benefits of paging . However, paged mapping causes another problem, internal fragmentation . This occurs when a program requests a block of memory that does not cleanly map into a page, for instance, if a program requests a 1 KB buffer to perform file work. In this case, the request results in an entire page being set aside even though only 1 KB of the page will ever be used; if pages are larger than 1 KB,

1620-399: Is very small. An OS may treat multiple pages as if they were a single larger page. For example, Linux on VAX groups eight pages together. Thus, the system is viewed as having 4 KB pages. The VAX divides memory into four fixed-purpose regions, each 1 GB in size. They are: Page tables are big linear arrays. Normally, this would be very wasteful when addresses are used at both ends of

1680-593: The MOS 6502 . For instance, the Atari MMU would express additional bits on the address bus to select among several banks of DRAM memory based on which of the chips was currently active, normally the CPU or ANTIC . This was used to expand the available memory on the Atari 130XE to 128 kB. The Commodore 128 used a similar approach. Most modern systems divide memory into pages that are 4–64 KB in size, often with

1740-495: The Motorola 68000 microprocessor and introduced in 1982. It includes the original Sun 1 memory management unit that provides address translation, memory protection, memory sharing and memory allocation for multiple processes running on the CPU. All access of the CPU to private on-board RAM, external Multibus memory, on-board I/O and the Multibus I/O runs through the MMU, where address translation and protection are done in

1800-514: The Motorola 68020 , and have a similar memory management unit. The page size is increased to 8 KB . (The later models are built around the Motorola 68030 and use the 68030's on-chip MMU.) The Sun-4 workstations are built around various SPARC microprocessors, and have a memory management unit similar to that of the Sun-3 workstations. Demand paging In computer operating systems , demand paging (as opposed to anticipatory paging )

1860-592: The Zilog Z8000 family of processors. Later microprocessors (such as the Motorola 68030 and the Zilog Z280 ) placed the MMU together with the CPU on the same integrated circuit, as did the Intel 80286 and later x86 microprocessors. While this article concentrates on modern MMUs, commonly based on demand paging, early systems used base and bounds addressing that further developed into segmentation , or used

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1920-494: The base and limit , although many other terms have been used. When the operating system requested memory to load a program, or a program requested more memory to hold data from a file for instance, it would call the memory handling library . This examined the mappings to look for an area in main memory large enough to hold the request. If such a block was found, a new entry was entered into the table. From then on, when that program accessed memory, all of its addresses were offset by

1980-471: The operating system . The OS will then select a lesser-used block in memory, write it to backing storage such as a hard drive if it has been modified since it was read in, read the page from backing storage into that block, and set up the MMU to map the block to the originally requested page so the program can use it. This is known as demand paging . Modern MMUs generally perform additional memory-related tasks as well. Memory protection blocks attempts by

2040-457: The 1980s. This problem can be reduced by making the pages larger, say 64 kB instead of 8. Now the page index uses 16 bits and the resulting page table is 64 kB, which is more tractable. Moving to a larger page size leads to the second problem, increased internal fragmentation. A program that generates a series of requests for small block will be assigned large blocks and thereby waste large amounts of memory. The paged translation approach

2100-558: The CPU, with four processor registers holding base values accessed directly by the program. These mapped only the upper 4 bits of the 20-bit address, and there was no equivalent of a limit, which was simply the lower 16-bits of the address and thus a fixed 64 kB. Later entries in the x86 architecture series used different approaches. Some systems, such as the GE 645 and its successors, used both segmentation and paging. The table of segments, instead of containing per-segment entries giving

2160-464: The MMU when trapping into OS code. The IBM System/360 Model 67 , which was introduced August, 1965, included an MMU called a dynamic address translation (DAT) box. It has the unusual feature of storing accessed and dirty bits outside of the page table (along with the four bit protection key for all S/360 processors). They refer to physical memory rather than virtual memory, and are accessed by special-purpose instructions. This reduces overhead for

2220-815: The Moon University , in Fort Portal, Uganda Multimedia University , in Malaysia Myanmar Maritime University Other [ edit ] Mobile Meteorological Unit , a deployable weather forecasting support unit of the British Armed Forces Monomethylurea, one of the ureas , used in synthetic medications Morristown Municipal Airport (IATA code MMU), in New Jersey Mega Man Universe ,

2280-520: The OS, which would otherwise need to propagate accessed and dirty bits from the page tables to a more physically oriented data structure. This makes OS-level virtualization , later called paravirtualization , easier. Starting in August, 1972, the IBM System/370 has a similar MMU, although it initially supported only a 24-bit virtual address space rather than the 32-bit virtual address space of

2340-532: The System/360 Model 67. It also stores the accessed and dirty bits outside the page table. In early 1983, the System/370-XA architecture expanded the virtual address space to 31 bits, and in 2000, the 64-bit z/Architecture was introduced, with the address space expanded to 64 bits; those continue to store the accessed and dirty bits outside the page table. VAX pages are 512 bytes, which

2400-454: The accessed bit if they are to operate efficiently. Typically, the OS will periodically unmap pages so that page-not-present faults can be used to let the OS set an accessed bit. ARM architecture -based application processors implement an MMU defined by ARM's virtual memory system architecture. The current architecture defines PTEs for describing 4 KB and 64 KB pages, 1 MB sections and 16 MB super-sections; legacy versions also defined

2460-411: The base value. When the program is done with the memory it requested and releases, or the program exits, the entries associated with it are released. This style of access, over time, became common in the mainframe market and was known as segmented translation , although a variety of terms are used here as well. This style has the advantage of simplicity; the memory blocks are continuous and thus only

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2520-402: The capability to use so-called huge pages of 2 MB or 1 GB in size (often both variants are possible). Page translations are cached in a translation lookaside buffer (TLB). Some systems, mainly older RISC designs, trap into the OS when a page translation is not found in the TLB. Most systems use a hardware-based tree walker. Most systems allow the MMU to be disabled, but some disable

2580-452: The installed memory. Another common technique, found mostly on larger machines, was segmented translation, which allowed for variable-size blocks of memory that better mapped onto program requests. This was efficient but did not map as well onto virtual memory. Some early systems, especially 8-bit systems, used very simple MMUs to perform bank switching . Modern MMUs typically divide the virtual address space (the range of addresses used by

2640-416: The memory bus among the many parts of the computer that desire access. Prior to VM systems becoming widespread in the 1990s, earlier MMU designs were more varied. Common among these was paged translation, which was similar to modern demand paging in that it used fixed-size blocks, but had a fixed-size list of pages that divided up memory; this meant that the block size was a function of the number of pages and

2700-432: The operating system. In some cases, a page fault may indicate a software bug , which can be prevented by using memory protection as one of key benefits of an MMU: an operating system can use it to protect against errant programs by disallowing access to memory that a particular program should not have access to. Typically, an operating system assigns each program its own virtual address space. A paged MMU also mitigates

2760-455: The page mask bits are not stored in the VPN2. Each TLB entry has its own page size, which can be any value from 1 KB to 256 MB in multiples of four. Each PFN in a TLB entry has a caching attribute, a dirty and a valid status bit. A VPN2 has a global status bit and an OS assigned ID which participates in the virtual address TLB entry match, if the global status bit is set to zero. A PFN stores

2820-400: The page size is dependent on the processor. pages. After a TLB miss, low-level firmware machine code (here called PALcode ) walks a page table. The OpenVMS AXP PALcode and DEC OSF/1 PALcode walk a three-level tree-structured page table. Addresses are broken down into an unused set of bits (containing the same value as the uppermost bit of the index into the root level of the tree),

2880-401: The physical address without the page mask bits. A TLB refill exception is generated when there are no entries in the TLB that match the mapped virtual address. A TLB invalid exception is generated when there is a match but the entry is marked invalid. A TLB modified exception is generated when a store instruction references a mapped address and the matching entry's dirty status is not set. If

2940-414: The physical base address and length of the segment, contains entries giving the physical base address of a page table for the segment, in addition to the length of the segment. Physical memory is divided into fixed-size pages, and the same techniques used for purely page-based demand paging are used for segment-and-page-based demand paging. Another approach to memory handling is to break up main memory into

3000-467: The possible range, but the page tables for P0 and P1 space are stored in the paged S0 space. Thus, there is effectively a two-level tree , allowing applications to have sparse memory layout without wasting a lot of space on unused page table entries. Unlike page table entries in most MMUs, page table entries in the VAX MMU lack an accessed bit . OSes which implement paging must find some way to emulate

3060-416: The problem of external fragmentation of memory. After blocks of memory have been allocated and freed, the free memory may become fragmented (discontinuous) so that the largest contiguous block of free memory may be much smaller than the total amount. With virtual memory, a contiguous range of virtual addresses can be mapped to several non-contiguous blocks of physical memory; this non-contiguous allocation

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3120-425: The processor) into pages , each having a size which is a power of 2, usually a few kilobytes , but they may be much larger. Programs reference memory using the natural address size of the machine, typically 32 or 64-bits in modern systems. The bottom bits of the address (the offset within a page) are left unchanged. The upper address bits are the virtual page numbers. Most MMUs use an in-memory table of items called

3180-614: The remainder of the page is wasted. If many small allocations of this sort are made, memory can be used up even though much of it remains empty. In some early microprocessor designs, memory management was performed by a separate integrated circuit such as the VLSI Technology VI475 (1986), the Motorola 68851 (1984) used with the Motorola 68020 CPU in the Macintosh II , or the Z8010 and Z8015 (1985) used with

3240-443: The same values in to the segment or page maps of different contexts. Additional contexts can be handled by treating the segment map as a context cache and replacing out-of-date contexts on a least-recently used basis. The context register makes no distinction between user and supervisor states. Interrupts and traps do not switch contexts, which requires that all valid interrupt vectors always be mapped in page 0 of context, as well as

3300-518: The segmented case, programs see its memory as a single contiguous block. There are two disadvantages to this approach. The first is that as the virtual address space expands, the amount of memory needed to hold the mapping increases as well. For instance, in the 68020 the addresses are 32-bits wide, meaning the segment number for the same 8 kB page size is now the upper 19 bits and the mapping table expands to 512 kB in size, far beyond what could be implemented in hardware for reasonable cost in

3360-401: The theoretical maximum. This is possible because programs rarely use large amounts of memory at any one time. Most modern operating systems (OS) work in concert with an MMU to provide virtual memory (VM) support. The MMU tracks memory use in fixed-size blocks known as pages , and if a program refers to a location in a page that is not in physical memory, the MMU will cause an interrupt to

3420-482: The two values, base and limit, need to be stored. Each entry corresponds to a block of memory used by a single program, and the translation is invisible to the program, which sees main memory starting at address zero and extending to some fixed value. The disadvantage of this approach is that it leads to an effect known as external fragmentation . This occurs when memory allocations are released but are non-contiguous. In this case, enough memory may be available to handle

3480-492: The valid supervisor stack. The Sun-2 workstations are similar; they are built around the Motorola 68010 microprocessor and have a similar memory management unit, with 2 KB pages and 32 KB segments. The context register has a 3-bit system context used in supervisor state and a 3-bit user context used in user state. The Sun-3 workstations, except for the Sun-3/80, Sun-3/460, Sun-3/470, and Sun-3/480, are built around

3540-581: Was also supported in software implementations; one example is Apple's MultiFinder , released in 1987 for the Macintosh platform. Each program was allocated an amount of memory that was pre-selected in the Finder and translation from virtual to physical was accomplished within the programs using handles . A more common example is the Intel 8088 used in the IBM PC . This implemented a very simple MMU inside

3600-527: Was widely used by microprocessor MMUs in the 1970s and early 80s, including the Signetics 68905 (which could operate in either mode). Both Signetics and Philips produced a version of the 68000 that combined the 68905 on the same physical chip, the 68070. Another use of this technique is to expand the size of the physical address when the virtual address is too small. For instance, the PDP-11 originally had

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