Management Data Input/Output ( MDIO ), also known as Serial Management Interface ( SMI ) or Media Independent Interface Management ( MIIM ), is a serial bus defined for the Ethernet family of IEEE 802.3 standards for the Media Independent Interface , or MII . The MII connects media access control (MAC) devices with Ethernet physical layer (PHY) circuits. The MAC device controlling the MDIO is called the Station Management Entity (SME).
5-493: MII has two signal interfaces: The MDIO interface is implemented by two signals: The bus only supports a single MAC as the master, and can have up to 32 PHY slaves. The MDC can be periodic, with a minimum period of 400 ns, which corresponds to a maximum frequency of 2.5 MHz. Newer chips, however, allow faster accesses. For example, the DP83640 supports a 25 MHz maximum clock rate for MDC. The MDIO requires
10-517: A specific pull-up resistor of 1.5 kΩ to 10 kΩ, taking into account the total worst-case leakage current of 32 PHYs and one MAC. Before a register access, PHY devices generally require a preamble of 32 ones to be sent by the MAC on the MDIO line. The access consists of 16 control bits, followed by 16 data bits. The control bits consist of 2 start bits, 2 access type bits (read or write),
15-460: The PHY address (5 bits), the register address (5 bits), and 2 "turnaround" bits. During a write command, the MAC provides address and data. For a read command, the PHY takes over the MDIO line during the turnaround bit times, supplies the MAC with the register data requested, then releases the MDIO line. When the MAC drives the MDIO line, it has to guarantee a stable value 10 ns (setup time) before
20-463: The clock. PRE_32 The first field in the MDIO header is the Preamble. During the preamble, the MAC sends 32 bits, all '1', on the MDIO line. ST The Start field consists of 2 bits and always contains the combination '01'. OP The Opcode consists of 2 bits. There are two possible opcodes, read '10' or write '01'. PA5 5 bits, PHY address. RA5 The Register Address field indicates
25-407: The rising edge of the clock MDC. Further, MDIO has to remain stable 10 ns (hold time) after the rising edge of MDC. When the PHY drives the MDIO line, the PHY has to provide the MDIO signal between 0 and 300 ns after the rising edge of the clock. Hence, with a minimum clock period of 400 ns (2.5 MHz maximum clock rate) the MAC can safely sample MDIO during the second half of the low cycle of
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