A solid-state drive ( SSD ) is a type of solid-state storage device that uses integrated circuits to store data persistently . It is sometimes called semiconductor storage device , solid-state device , or solid-state disk .
100-698: SSDs rely on non-volatile memory, typically NAND flash , to store data in memory cells. The performance and endurance of SSDs vary depending on the number of bits stored per cell, ranging from high-performing single-level cells (SLC) to more affordable but slower quad-level cells (QLC). In addition to flash-based SSDs, other technologies such as 3D XPoint offer faster speeds and higher endurance through different data storage mechanisms. Unlike traditional hard disk drives (HDDs), SSDs have no moving parts, allowing them to deliver faster data access speeds, reduced latency, increased resistance to physical shock, lower power consumption, and silent operation. Often interfaced to
200-474: A Samsung 970 EVO NVMe M.2 SSD (2018) with 1 TB of capacity has an endurance rating of 600 TBW. Recovering data from SSDs presents challenges due to the non-linear and complex nature of data storage in solid-state drives. The internal operations of SSDs vary by manufacturer, with commands (e.g. TRIM and the ATA Secure Erase) and programs like (e.g. hdparm ) being able to erase and modify
300-426: A cache (configurable as write-through or write-back ) for a conventional, magnetic hard disk drive. A similar technology is available on HighPoint 's RocketHybrid PCIe card. Solid-state hybrid drives (SSHDs) are based on the same principle, but integrate some amount of flash memory on board of a conventional drive instead of using a separate SSD. The flash layer in these drives can be accessed independently from
400-409: A live SD operating system are easily write-locked . Combined with a cloud computing environment or other writable medium, an OS booted from a write-locked SD card is reliable, persistent and impervious to permanent corruption. In 2011, Intel introduced a caching mechanism for their Z68 chipset (and mobile derivatives) called Smart Response Technology , which allows a SATA SSD to be used as
500-640: A 1024 GB flash chip, with eight stacked 96-layer V-NAND chips and with QLC technology. Flash memory stores information in an array of memory cells made from floating-gate transistors . In single-level cell (SLC) devices, each cell stores only one bit of information. Multi-level cell (MLC) devices, including triple-level cell (TLC) devices, can store more than one bit per cell. The floating gate may be conductive (typically polysilicon in most kinds of flash memory) or non-conductive (as in SONOS flash memory). In flash memory, each memory cell resembles
600-489: A 16 GB flash memory chip that was manufactured with 24 stacked NAND flash chips using a wafer bonding process. Toshiba also used an eight-layer 3D IC for their 32 GB THGBM flash chip in 2008. In 2010, Toshiba used a 16-layer 3D IC for their 128 GB THGBM2 flash chip, which was manufactured with 16 stacked 8 GB chips. In the 2010s, 3D ICs came into widespread commercial use for NAND flash memory in mobile devices . In 2016, Micron and Intel introduced
700-433: A 64 MB NOR flash memory chip. In 2009, Toshiba and SanDisk introduced NAND flash chips with QLC technology storing 4 bits per cell and holding a capacity of 64 Gbit. Samsung Electronics introduced triple-level cell (TLC) technology storing 3-bits per cell, and began mass-producing NAND chips with TLC technology in 2010. Charge trap flash (CTF) technology replaces the polysilicon floating gate, which
800-663: A DRAM SSD. DRAM-based SSDs are often used for tasks where data must be accessed at high speeds with low latency, such as in high-performance computing or certain server environments. 3D XPoint is a type of non-volatile memory technology developed by Intel and Micron, announced in 2015. It operates by changing the electrical resistance of materials in its cells, offering much faster access times than NAND flash. 3D XPoint-based SSDs, such as Intel’s Optane drives, provide lower latency and higher endurance than NAND-based drives, although they are more expensive per gigabyte. Drives known as hybrid drives or solid-state hybrid drives (SSHDs) use
900-432: A block of data is re-written to the flash memory, it is written to a new location. However, flash memory blocks that never get replacement data would sustain no additional wear, thus the name comes only from the dynamic data being recycled. Such a device may last longer than one with no wear leveling, but there are blocks still remaining as active even though the device is no longer operable. The other type of wear leveling
1000-548: A certain number of faults (NOR flash, as is used for a BIOS ROM, is expected to be fault-free). Manufacturers try to maximize the amount of usable storage by shrinking the size of the transistors or cells, however the industry can avoid this and achieve higher storage densities per die by using 3D NAND, which stacks cells on top of each other. NAND flash cells are read by analysing their response to various voltages. NAND flash uses tunnel injection for writing and tunnel release for erasing. NAND flash memory forms
1100-517: A charge-trapping mechanism for NOR flash memory cells. CTF was later commercialized by AMD and Fujitsu in 2002. 3D V-NAND (vertical NAND) technology stacks NAND flash memory cells vertically within a chip using 3D charge trap flash (CTP) technology. 3D V-NAND technology was first announced by Toshiba in 2007, and the first device, with 24 layers, was first commercialized by Samsung Electronics in 2013. 3D integrated circuit (3D IC) technology stacks integrated circuit (IC) chips vertically into
SECTION 10
#17327756933261200-803: A controller, which manages the data flow between the NAND memory and the host computer. The controller is an embedded processor that runs firmware to optimize performance, managing data, and ensuring data integrity. Some of the primary functions performed by the controller are: The overall performance of an SSD can scale with the number of parallel NAND chips and the efficiency of the controller. For example, controllers that enable parallel processing of NAND flash chips can improve bandwidth and reduce latency. Micron and Intel pioneered faster SSDs by implementing techniques such as data striping and interleaving to enhance read/write speeds. More recently, SandForce introduced controllers that incorporate data compression to reduce
1300-466: A different architecture, relying on a serial access approach. This makes NAND suitable for high-density data storage but less efficient for random access tasks. NAND flash is often employed in scenarios where cost-effective, high-capacity storage is crucial, such as in USB drives, memory cards, and solid-state drives ( SSDs ). The primary differentiator lies in their use cases and internal structures. NOR flash
1400-501: A fast read access time but it is not as fast as static RAM or ROM. In portable devices, it is preferred to use flash memory because of its mechanical shock resistance since mechanical drives are more prone to mechanical damage. Because erase cycles are slow, the large block sizes used in flash memory erasing give it a significant speed advantage over non-flash EEPROM when writing large amounts of data. As of 2019, flash memory costs greatly less than byte-programmable EEPROM and had become
1500-465: A few blocks reach their end of life, such a device becomes inoperable. The first type of wear leveling is called dynamic wear leveling and it uses a map to link logical block addresses (LBAs) from the OS to the physical flash memory. Each time the OS writes replacement data, the map is updated so the original physical block is marked as invalid data, and a new block is linked to that map entry. Each time
1600-420: A hybrid of spinning disks and flash memory. Some SSDs use magnetoresistive random-access memory (MRAM) for storing data. Many flash-based SSDs include a small amount of volatile DRAM as a cache, similar to the buffers in hard disk drives. This cache can temporarily hold data while it is being written to the flash memory, and it also stores metadata such as the mapping of logical blocks to physical locations on
1700-741: A limited lifetime number of writes, and also slow down as they reach their full storage capacity. SSDs also have internal parallelism that allows them to manage multiple operations simultaneously, which enhances their performance. Unlike HDDs and similar electromechanical magnetic storage , SSDs do not have moving mechanical parts, which provides advantages such as resistance to physical shock, quieter operation, and faster access times. Their lower latency results in higher input/output rates (IOPS) than HDDs. Some SSDs are combined with traditional hard drives in hybrid configurations, such as Intel's Hystor and Apple's Fusion Drive . These drives use both flash memory and spinning magnetic disks in order to improve
1800-862: A lower cost than pure SSDs. An SSD stores data in semiconductor cells, with its properties varying according to the number of bits stored in each cell (between 1 and 4). Single-level cells (SLC) store one bit of data per cell and provide higher performance and endurance. In contrast, multi-level cells (MLC), triple-level cells (TLC), and quad-level cells (QLC) store more data per cell but have lower performance and endurance. SSDs using 3D XPoint technology, such as Intel’s Optane, store data by changing electrical resistance instead of storing electrical charges in cells, which can provide faster speeds and longer data persistence compared to conventional flash memory. SSDs based on NAND flash slowly leak charge when not powered, while heavily-used consumer drives may start losing data typically after one to two year in storage. SSDs have
1900-425: A more typical 10,000 or 100,000 erase cycles, up to 1,000,000 erase cycles. NOR-based flash was the basis of early flash-based removable media; CompactFlash was originally based on it, though later cards moved to less expensive NAND flash. NAND flash has reduced erase and write times, and requires less chip area per cell, thus allowing greater storage density and lower cost per bit than NOR flash. However,
2000-518: A planar charge trap cell into a cylindrical form. As of 2020, 3D NAND flash memories by Micron and Intel instead use floating gates, however, Micron 128 layer and above 3D NAND memories use a conventional charge trap structure, due to the dissolution of the partnership between Micron and Intel. Charge trap 3D NAND flash is thinner than floating gate 3D NAND. In floating gate 3D NAND, the memory cells are completely separated from one another, whereas in charge trap 3D NAND, vertical groups of memory cells share
2100-421: A separate die inside the package. The origins of flash memory can be traced back to the development of the floating-gate MOSFET (FGMOS) , also known as the floating-gate transistor. The original MOSFET was invented at Bell Labs between 1955 and 1960, after Frosch and Derick discovered surface passivation and used their discovery to create the first planar transistors. Dawon Kahng went on to develop
SECTION 20
#17327756933262200-489: A single 3D IC chip package. Toshiba introduced 3D IC technology to NAND flash memory in April 2007, when they debuted a 16 GB eMMC compliant (product number THGAM0G7D8DBAI6, often abbreviated THGAM on consumer websites) embedded NAND flash memory chip, which was manufactured with eight stacked 2 GB NAND flash chips. In September 2007, Hynix Semiconductor (now SK Hynix ) introduced 24-layer 3D IC technology, with
2300-424: A single memory product. A single-level NOR flash cell in its default state is logically equivalent to a binary "1" value, because current will flow through the channel under application of an appropriate voltage to the control gate, so that the bitline voltage is pulled down. A NOR flash cell can be programmed, or set to a binary "0" value, by the following procedure: To erase a NOR flash cell (resetting it to
2400-409: A single supply voltage and produce the high voltages that are required using on-chip charge pumps . Over half the energy used by a 1.8 V-NAND flash chip is lost in the charge pump itself. Since boost converters are inherently more efficient than charge pumps, researchers developing low-power SSDs have proposed returning to the dual Vcc/Vpp supply voltages used on all early flash chips, driving
2500-488: A standard metal–oxide–semiconductor field-effect transistor (MOSFET) except that the transistor has two gates instead of one. The cells can be seen as an electrical switch in which current flows between two terminals (source and drain) and is controlled by a floating gate (FG) and a control gate (CG). The CG is similar to the gate in other MOS transistors, but below this, there is the FG insulated all around by an oxide layer. The FG
2600-625: A sudden power loss. Some consumer SSDs have built-in capacitors to save critical data such as the Flash Translation Layer (FTL) mapping table. Examples include the Crucial M500 and Intel 320 series. Enterprise-class SSDs, such as the Intel DC S3700 series, often come with more robust power-loss protection mechanisms like supercapacitors or batteries. The host interface of an SSD refers to the physical connector and
2700-735: A system in the same way as HDDs, SSDs are used in a variety of devices, including personal computers , enterprise servers , and mobile devices . However, SSDs are generally more expensive on a per-gigabyte basis and have a finite number of write cycles, which can lead to data loss over time. Despite these limitations, SSDs are increasingly replacing HDDs, especially in performance-critical applications and as primary storage in many consumer devices. SSDs come in various form factors and interface types, including SATA , PCIe , and NVMe , each offering different levels of performance. Hybrid storage solutions, such as solid-state hybrid drives (SSHDs), combine SSD and HDD technologies to offer improved performance at
2800-482: A technology known as CMOS Under the Array/CMOS Under Array (CUA), Core over Periphery (COP), Periphery Under Cell (PUA), or Xtacking, in which the control circuitry for the flash memory is placed under or above the flash memory cell array. This has allowed for an increase in the number of planes or sections a flash memory chip has, increasing from 2 planes to 4, without increasing the area dedicated to
2900-843: A time. NAND flash also uses floating-gate transistors , but they are connected in a way that resembles a NAND gate : several transistors are connected in series, and the bit line is pulled low only if all the word lines are pulled high (above the transistors' V T ). These groups are then connected via some additional transistors to a NOR-style bit line array in the same way that single transistors are linked in NOR ;flash. Compared to NOR flash, replacing single transistors with serial-linked groups adds an extra level of addressing. Whereas NOR flash might address memory by page then word, NAND flash might address it by page, word and bit. Bit-level addressing suits bit-serial applications (such as hard disk emulation), which access only one bit at
3000-453: A time. Execute-in-place applications, on the other hand, require every bit in a word to be accessed simultaneously. This requires word-level addressing. In any case, both bit and word addressing modes are possible with either NOR or NAND flash. To read data, first the desired group is selected (in the same way that a single transistor is selected from a NOR array). Next, most of the word lines are pulled up above V T2 , while one of them
3100-506: A type of flash memory with a charge trap method. In 1998, Boaz Eitan of Saifun Semiconductors (later acquired by Spansion ) patented a flash memory technology named NROM that took advantage of a charge trapping layer to replace the conventional floating gate used in conventional flash memory designs. In 2000, an Advanced Micro Devices (AMD) research team led by Richard M. Fastow, Egyptian engineer Khaled Z. Ahmed and Jordanian engineer Sameer Haddad (who later joined Spansion) demonstrated
Solid-state drive - Misplaced Pages Continue
3200-450: A variation, the floating-gate MOSFET, with Taiwanese-American engineer Simon Min Sze at Bell Labs in 1967. They proposed that it could be used as floating-gate memory cells for storing a form of programmable read-only memory ( PROM ) that is both non-volatile and re-programmable. Early types of floating-gate memory included EPROM (erasable PROM) and EEPROM (electrically erasable PROM) in
3300-460: Is transparent , and conventional file system such as FAT can be used on them as-is. Wear leveling can also be implemented in software by special-purpose file systems such as JFFS2 and YAFFS on flash media or UDF on optical media. All three are log-structured file systems in that they treat their media as circular logs and write to them in sequential passes. File systems which implement copy-on-write strategies, such as ZFS , also implement
3400-597: Is a technique for prolonging the service life of some kinds of erasable computer storage media, such as flash memory , which is used in solid-state drives (SSDs) and USB flash drives , and phase-change memory . There are several wear leveling mechanisms that provide varying levels of longevity enhancement in such memory systems. The term preemptive wear leveling (PWL) has been used by Western Digital to describe their preservation technique used on hard disk drives (HDDs) designed for storing audio and video data. However, HDDs generally are not wear-leveled devices in
3500-515: Is also often used to store configuration data in digital products, a task previously made possible by EEPROM or battery-powered static RAM . A key disadvantage of flash memory is that it can endure only a relatively small number of write cycles in a specific block. NOR flash is known for its direct random access capabilities, making it apt for executing code directly. Its architecture allows for individual byte access, facilitating faster read speeds compared to NAND flash. NAND flash memory operates with
3600-484: Is an electronic non-volatile computer memory storage medium that can be electrically erased and reprogrammed. The two main types of flash memory, NOR flash and NAND flash , are named for the NOR and NAND logic gates . Both use the same cell design, consisting of floating-gate MOSFETs . They differ at the circuit level depending on whether the state of the bit line or word lines is pulled high or low: in NAND flash,
3700-444: Is an electrically insulating tunnel oxide layer between the floating gate and the silicon, so the gate "floats" above the silicon. The oxide keeps the electrons confined to the floating gate. Degradation or wear (and the limited endurance of floating gate Flash memory) occurs due to the extremely high electric field (10 million volts per centimeter) experienced by the oxide. Such high voltage densities can break atomic bonds over time in
3800-517: Is called static wear leveling which also uses a map to link the LBA to physical memory addresses. Static wear leveling works the same as dynamic wear leveling except the static blocks that do not change are periodically moved so that these low usage cells are able to be used by other data. This rotational effect enables an SSD to continue to operate until most of the blocks are near their end of life. Both dynamic and static wear leveling are implemented at
3900-525: Is interposed between the CG and the MOSFET channel. Because the FG is electrically isolated by its insulating layer, electrons placed on it are trapped. When the FG is charged with electrons, this charge screens the electric field from the CG, thus, increasing the threshold voltage (V T ) of the cell. This means that the V T of the cell can be changed between the uncharged FG threshold voltage (V T1 ) and
4000-484: Is optimal for applications requiring quick access to individual bytes, like in embedded systems for program execution. NAND flash, on the other hand, shines in scenarios demanding cost-effective, high-capacity storage with sequential data access. Flash memory is used in computers , PDAs , digital audio players , digital cameras , mobile phones , synthesizers , video games , scientific instrumentation , industrial robotics , and medical electronics . Flash memory has
4100-463: Is prioritized over cost or non-volatility. Many SSDs, such as NVDIMM devices, are equipped with backup power sources such as internal batteries or external AC/DC adapters. These power sources ensure data is transferred to a backup system (usually NAND flash or another storage medium) in the event of power loss, preventing data corruption or loss. Similarly, ULLtraDIMM devices use components designed for DIMM modules, but only use flash memory, similar to
Solid-state drive - Misplaced Pages Continue
4200-636: Is programmed in blocks while EEPROM is programmed in bytes. According to Toshiba, the name "flash" was suggested by Masuoka's colleague, Shōji Ariizumi, because the erasure process of the memory contents reminded him of the flash of a camera . Masuoka and colleagues presented the invention of NOR flash in 1984, and then NAND flash at the IEEE 1987 International Electron Devices Meeting (IEDM) held in San Francisco. Toshiba commercially launched NAND flash memory in 1987. Intel Corporation introduced
4300-422: Is pulled up to V I . The series group will conduct (and pull the bit line low) if the selected bit has not been programmed. Despite the additional transistors, the reduction in ground wires and bit lines allows a denser layout and greater storage capacity per chip. (The ground wires and bit lines are actually much wider than the lines in the diagrams.) In addition, NAND flash is typically permitted to contain
4400-484: Is sandwiched between a blocking gate oxide above and a tunneling oxide below it, with an electrically insulating silicon nitride layer; the silicon nitride layer traps electrons. In theory, CTF is less prone to electron leakage, providing improved data retention. Because CTF replaces the polysilicon with an electrically insulating nitride, it allows for smaller cells and higher endurance (lower degradation or wear). However, electrons can become trapped and accumulate in
4500-513: Is thus highly suitable for use in mass-storage devices, such as memory cards and solid-state drives (SSD). For example, SSDs store data using multiple NAND flash memory chips. The first NAND-based removable memory card format was SmartMedia , released in 1995. Many others followed, including MultiMediaCard , Secure Digital , Memory Stick , and xD-Picture Card . A new generation of memory card formats, including RS-MMC , miniSD and microSD , feature extremely small form factors. For example,
4600-483: Is written to the flash. Without wear leveling, the underlying flash controller must permanently assign the logical addresses from the operating system (OS) to the physical addresses of the flash memory. This means that every write to a previously written block must first be read, erased, modified, and re-written to the same location. This approach is very time-consuming and frequently written locations will wear out quickly, while other locations will not be used at all. Once
4700-465: The magnetic storage by the host using ATA-8 commands, allowing the operating system to manage it. For example, Microsoft's ReadyDrive technology explicitly stores portions of the hibernation file in the cache of these drives when the system hibernates, making the subsequent resume faster. Dual-drive hybrid systems are combining the usage of separate SSD and HDD devices installed in the same computer, with overall performance optimization managed by
4800-502: The "1" state), a large voltage of the opposite polarity is applied between the CG and source terminal, pulling the electrons off the FG through Fowler–Nordheim tunneling (FN tunneling). This is known as Negative gate source source erase. Newer NOR memories can erase using negative gate channel erase, which biases the wordline on a NOR memory cell block and the P-well of the memory cell block to allow FN tunneling to be carried out, erasing
4900-712: The 1970s. However, early floating-gate memory required engineers to build a memory cell for each bit of data, which proved to be cumbersome, slow, and expensive, restricting floating-gate memory to niche applications in the 1970s, such as military equipment and the earliest experimental mobile phones . Modern EEPROM based on Fowler-Nordheim tunnelling to erase data was invented by Bernward and patented by Siemens in 1974. And further developed between 1976 and 1978 by Eliyahou Harari at Hughes Aircraft Company and George Perlegos and others at Intel. This led to Masuoka's invention of flash memory at Toshiba in 1980. The improvement between EEPROM and flash being that flash
5000-438: The FG is charged. The binary value of the cell is sensed by determining whether there is current flowing through the transistor when V I is asserted on the CG. In a multi-level cell device, which stores more than one bit per cell, the amount of current flow is sensed (rather than simply its presence or absence), in order to determine more precisely the level of charge on the FG. Floating gate MOSFETs are so named because there
5100-540: The I/O interface of NAND flash does not provide a random-access external address bus. Rather, data must be read on a block-wise basis, with typical block sizes of hundreds to thousands of bits. This makes NAND flash unsuitable as a drop-in replacement for program ROM, since most microprocessors and microcontrollers require byte-level random access. In this regard, NAND flash is similar to other secondary data storage devices , such as hard disks and optical media , and
SECTION 50
#17327756933265200-555: The SSD to use a portion of the system’s DRAM instead of relying on a built-in DRAM cache, reducing costs while maintaining a high level of performance. In certain high-end consumer and enterprise SSDs, larger amounts of DRAM are included to cache both file table mappings and written data, reducing write amplification and enhances overall performance. Higher-performing SSDs may include a capacitor or battery, which helps preserve data integrity in
5300-619: The SSD. Some SSD controllers, like those from SandForce, achieve high performance without using an external DRAM cache. These designs rely on other mechanisms, such as on-chip SRAM, to manage data and minimize power consumption. Additionally, some SSDs use an SLC cache mechanism to temporarily store data in single-level cell (SLC) mode, even on multi-level cell (MLC) or triple-level cell (TLC) SSDs. This improves write performance by allowing data to be written to faster SLC storage before being moved to slower, higher-capacity MLC or TLC storage. On NVMe SSDs, Host Memory Buffer (HMB) technology allows
5400-642: The amount of data written to the flash memory, potentially increasing both performance and endurance. Wear leveling is a technique used in SSDs to ensure that write and erase operations are distributed evenly across all blocks of the flash memory. Without this, specific blocks could wear out prematurely due to repeated use, reducing the overall lifespan of the SSD. The process moves data that is infrequently changed (cold data) from heavily used blocks, so that data that changes more frequently (hot data) can be written to those blocks. This helps distribute wear more evenly across
5500-417: The bits of a deleted file. The JEDEC Solid State Technology Association (JEDEC) has established standards for SSD reliability metrics, which include: In a distributed computing environment, SSDs can be used as a distributed cache layer that temporarily absorbs the large volume of user requests to slower HDD-based backend storage systems. This layer provides much higher bandwidth and lower latency than
5600-466: The cell block. Older memories used source erase, in which a high voltage was applied to the source and then electrons from the FG were moved to the source. Modern NOR flash memory chips are divided into erase segments (often called blocks or sectors). The erase operation can be performed only on a block-wise basis; all the cells in an erase segment must be erased together. Programming of NOR cells, however, generally can be performed one byte or word at
5700-502: The cell by increasing the MOSFET's threshold voltage. This, in turn, changes the drain-source current that flows through the transistor for a given gate voltage, which is ultimately used to encode a binary value. The Fowler-Nordheim tunneling effect is reversible, so electrons can be added to or removed from the floating gate, processes traditionally known as writing and erasing. Despite the need for relatively high programming and erasing voltages, virtually all flash chips today require only
5800-402: The cells are logically set to 1. Data can only be programmed in one pass to a page in a block that was erased. The programming process is set one or more cells from 1 to 0. Any cells that have been set to 0 by programming can only be reset to 1 by erasing the entire block. This means that before new data can be programmed into a page that already contains data, the current contents of the page plus
5900-422: The complete loss of the drive. Most of the advantages of solid-state drives over traditional hard drives are due to their ability to access data completely electronically instead of electromechanically, resulting in superior transfer speeds and mechanical ruggedness. On the other hand, hard disk drives offer significantly higher capacity for their price. In traditional HDDs, a rewritten file will generally occupy
6000-689: The computer like hard drives. In contrast, memory cards (such as Secure Digital (SD), CompactFlash (CF), and many others) were originally designed for digital cameras and later found their way into cell phones, gaming devices, GPS units, etc. Most memory cards are physically smaller than SSDs, and designed to be inserted and removed repeatedly. SSDs have different failure modes from traditional magnetic hard drives. Because solid-state drives contain no moving parts, they are generally not subject to mechanical failures. However, other types of failures can occur. For example, incomplete or failed writes due to sudden power loss may be more problematic than with HDDs, and
6100-589: The computer user, or by the computer's operating system software. Examples of this type of system are bcache and dm-cache on Linux , and Apple's Fusion Drive . The primary components of an SSD are the controller and the memory used to store data. Traditionally, early SSDs used volatile DRAM for storage, but since 2009, most SSDs utilize non-volatile NAND flash memory, which retains data even when powered off. Flash memory SSDs store data in metal–oxide–semiconductor (MOS) integrated circuit chips, using non-volatile floating-gate memory cells. Every SSD includes
SECTION 60
#17327756933266200-739: The context of this article. EEPROM and flash memory media have individually erasable segments, each of which can be put through a limited number of erase cycles before becoming unreliable. This is usually around 3,000/5,000 cycles but many flash devices have one block with a specially extended life of 100,000+ cycles that can be used by the Flash memory controller to track wear and movement of data across segments. Erasable optical media such as CD-RW and DVD-RW are rated at up to 1,000 cycles (100,000 cycles for DVD-RAM media). Wear leveling attempts to work around these limitations by arranging data so that erasures and re-writes are distributed evenly across
6300-584: The control or periphery circuitry. This increases the number of IO operations per flash chip or die, but it also introduces challenges when building capacitors for charge pumps used to write to the flash memory. Some flash dies have as many as 6 planes. As of August 2017, microSD cards with a capacity up to 400 GB (400 billion bytes) are available. The same year, Samsung combined 3D IC chip stacking with its 3D V-NAND and TLC technologies to manufacture its 512 GB KLUFG8R1EM flash memory chip with eight stacked 64-layer V-NAND chips. In 2019, Samsung produced
6400-404: The core of the removable USB storage devices known as USB flash drives , as well as most memory card formats and solid-state drives available today. The hierarchical structure of NAND flash starts at a cell level which establishes strings, then pages, blocks, planes and ultimately a die. A string is a series of connected NAND cells in which the source of one cell is connected to the drain of
6500-576: The dominant memory type wherever a system required a significant amount of non-volatile solid-state storage . EEPROMs, however, are still used in applications that require only small amounts of storage, e.g. in SPD implementations on computer memory modules. Flash memory packages can use die stacking with through-silicon vias and several dozen layers of 3D TLC NAND cells (per die) simultaneously to achieve capacities of up to 1 tebibyte per package using 16 stacked dies and an integrated flash controller as
6600-524: The entire SSD. However, this process introduces additional writes, known as write amplification, which must be managed to balance performance and durability. Most SSDs use non-volatile NAND flash memory for data storage, primarily due to its cost-effectiveness and ability to retain data without a constant power supply. NAND flash-based SSDs store data in semiconductor cells, with the specific architecture influencing performance, endurance, and cost. There are various types of NAND flash memory, categorized by
6700-575: The entire device. NOR flash memory allows a single machine word to be written – to an erased location – or read independently. A flash memory device typically consists of one or more flash memory chips (each holding many flash memory cells), along with a separate flash memory controller chip. The NAND type is found mainly in memory cards , USB flash drives , solid-state drives (those produced since 2009), feature phones , smartphones , and similar products, for general storage and transfer of data. NAND or NOR flash memory
6800-533: The event of an unexpected power loss. The capacitor or battery provides enough power to allow the data in the cache to be written to the non-volatile memory, ensuring no data is lost. In some SSDs that use multi-level cell (MLC) flash memory, a potential issue known as "lower page corruption" can occur if power is lost while programming an upper page. This can result in previously written data becoming corrupted. To address this, some high-end SSDs incorporate supercapacitors to ensure all data can be safely written during
6900-463: The failure of a single chip may result in the loss of all data stored on it. Nonetheless, studies indicate that SSDs are generally reliable, often exceed their manufacturer-stated lifespan and having lower failure rates than HDDs. However, studies also note that SSDs experience higher rates of uncorrectable errors, which can lead to data loss, compared to HDDs. The endurance of an SSD is typically listed on its datasheet in one of two forms: For example,
7000-497: The first commercial NOR type flash chip in 1988. NOR-based flash has long erase and write times, but provides full address and data buses , allowing random access to any memory location . This makes it a suitable replacement for older read-only memory (ROM) chips, which are used to store program code that rarely needs to be updated, such as a computer's BIOS or the firmware of set-top boxes . Its endurance may be from as little as 100 erase cycles for an on-chip flash memory, to
7100-416: The flash memory together―in a single pool. It ensures that all the cells in all the chips within the product are worn out evenly. The following table compares static and dynamic wear leveling: There are several techniques for extending the media life: On Secure Digital cards and USB flash drives , techniques are implemented in hardware by a built-in microcontroller . On such devices, wear leveling
7200-462: The flash storage device (such as SSD ), the data actually written to the flash memory may be 0011 1100. Vertical NAND (V-NAND) or 3D NAND memory stacks memory cells vertically and uses a charge trap flash architecture. The vertical layers allow larger areal bit densities without requiring smaller individual cells. It is also sold under the trademark BiCS Flash , which is a trademark of Kioxia Corporation (formerly Toshiba Memory Corporation). 3D NAND
7300-415: The flat (planar) NAND structure, many SSDs now use 3D NAND (or V-NAND), where memory cells are stacked vertically, increasing storage density while improving performance and reducing costs. Some SSDs use volatile DRAM instead of NAND flash, offering very high-speed data access but requiring a constant power supply to retain data. DRAM-based SSDs are typically used in specialized applications where performance
7400-418: The floating gate. This is why data retention goes down and the risk of data loss increases with increasing degradation. The silicon oxide in a cell degrades with every erase operation. The degradation increases the amount of negative charge in the cell over time due to trapped electrons in the oxide and negates some of the control gate voltage, this over time also makes erasing the cell slower, so to maintain
7500-435: The high Vpp voltage for all flash chips in an SSD with a single shared external boost converter. In spacecraft and other high-radiation environments, the on-chip charge pump is the first part of the flash chip to fail, although flash memories will continue to work – in read-only mode – at much higher radiation levels. In NOR flash, each cell has one end connected directly to ground, and
7600-415: The higher charged FG threshold voltage (V T2 ) by changing the FG charge. In order to read a value from the cell, an intermediate voltage (V I ) between V T1 and V T2 is applied to the CG. If the channel conducts at V I , the FG must be uncharged (if it were charged, there would not be conduction because V I is less than V T2 ). If the channel does not conduct at the V I , it indicates that
7700-409: The local level. This simply means that in a multi-chip product, every chip is managed as a single resource. The number of defective blocks in different chips within a NAND flash memory varies: a given chip could have all its data blocks worn out while another chip in the same device could have all its blocks still active. Global wear leveling addresses this problem by managing all blocks from all chips in
7800-513: The medium. In this way, no single erase block prematurely fails due to a high concentration of write cycles. In flash memory, a single block on the chip is designed for longer life than the others so that the memory controller can store operational data with less chance of its corruption. Conventional file systems such as FAT , UFS , HFS / HFS+ , EXT , and NTFS were originally designed for magnetic disks and as such rewrite many of their data structures (such as their directories) repeatedly to
7900-659: The microSD card has an area of just over 1.5 cm , with a thickness of less than 1 mm. NAND flash has achieved significant levels of memory density as a result of several major technologies that were commercialized during the late 2000s to early 2010s. NOR flash was the most common type of Flash memory sold until 2005, when NAND flash overtook NOR flash in sales. Multi-level cell (MLC) technology stores more than one bit in each memory cell . NEC demonstrated multi-level cell (MLC) technology in 1998, with an 80 Mb flash memory chip storing 2 bits per cell. STMicroelectronics also demonstrated MLC in 2000, with
8000-422: The new data must be copied to a new, erased page. If a suitable erased page is available, the data can be written to it immediately. If no erased page is available, a block must be erased before copying the data to a page in that block. The old page is then marked as invalid and is available for erasing and reuse. This is different from operating system LBA view, for example, if operating system writes 1100 0011 to
8100-414: The next one. Depending on the NAND technology, a string typically consists of 32 to 128 NAND cells. Strings are organised into pages which are then organised into blocks in which each string is connected to a separate line called a bitline. All cells with the same position in the string are connected through the control gates by a wordline. A plane contains a certain number of blocks that are connected through
8200-474: The nitride, leading to degradation. Leakage is exacerbated at high temperatures since electrons become more excited with increasing temperatures. CTF technology however still uses a tunneling oxide and blocking layer which are the weak points of the technology, since they can still be damaged in the usual ways (the tunnel oxide can be degraded due to extremely high electric fields and the blocking layer due to Anode Hot Hole Injection (AHHI). Degradation or wear of
8300-413: The number of bits increases, the number of possible states also increases and thus the cell is less tolerant of adjustments to programming voltages, because there is less space between the voltage levels that define each state in a cell. The process of moving electrons from the control gate and into the floating gate is called Fowler–Nordheim tunneling , and it fundamentally changes the characteristics of
8400-431: The number of bits stored in each cell: Over time, SSD controllers have improved the efficiency of NAND flash, incorporating techniques such as interleaved memory , advanced error correction, and wear leveling to optimize performance and extend the lifespan of the drive. Lower-end SSDs often use QLC or TLC memory, while higher-end drives for enterprise or performance-critical applications may use MLC or SLC. In addition to
8500-516: The other end connected directly to a bit line. This arrangement is called "NOR flash" because it acts like a NOR gate: when one of the word lines (connected to the cell's CG) is brought high, the corresponding storage transistor acts to pull the output bit line low. NOR flash continues to be the technology of choice for embedded applications requiring a discrete non-volatile memory device. The low read latencies characteristic of NOR devices allow for both direct code execution and data storage in
8600-435: The oxides is the reason why flash memory has limited endurance, and data retention goes down (the potential for data loss increases) with increasing degradation, since the oxides lose their electrically insulating characteristics as they degrade. The oxides must insulate against electrons to prevent them from leaking which would cause data loss. In 1991, NEC researchers including N. Kodama, K. Oyama and Hiroki Shirai described
8700-413: The performance and reliability of the NAND chip, the cell must be retired from use. Endurance also decreases with the number of bits in a cell. With more bits in a cell, the number of possible states (each represented by a different voltage level) in a cell increases and is more sensitive to the voltages used for programming. Voltages may be adjusted to compensate for degradation of the silicon oxide, and as
8800-737: The performance characteristics such as rotational latency and seek time . As SSDs do not need to spin or seek to locate data, they are vastly superior to HDDs in such tests. However, SSDs have challenges with mixed reads and writes, and their performance may degrade over time. Therefore, SSD testing typically looks at when the full drive is first used, as the new and empty drive may have much better write performance than it would show after only weeks of use. The reliability of both HDDs and SSDs varies greatly among models. Some field failure rates indicate that SSDs are significantly more reliable than HDDs. However, SSDs are sensitive to sudden power interruption, sometimes resulting in aborted writes or even cases of
8900-546: The performance of frequently-accessed data. Traditional interfaces (e.g. SATA and SAS ) and standard HDD form factors allow such SSDs to be used as drop-in replacements for HDDs in computers and other devices. Newer form factors such as mSATA , M.2 , U.2 , NF1 / M.3 / NGSFF , XFM Express ( Crossover Flash Memory , form factor XT2) and EDSFF and higher speed interfaces such as NVM Express (NVMe) over PCI Express (PCIe) can further increase performance over HDD performance. Traditional HDD benchmarks tend to focus on
9000-544: The relationship between the bit line and the word lines resembles a NAND gate; in NOR flash, it resembles a NOR gate. Flash memory, a type of floating-gate memory, was invented by Fujio Masuoka at Toshiba in 1980 and is based on EEPROM technology. Toshiba began marketing flash memory in 1987. EPROMs had to be erased completely before they could be rewritten. NAND flash memory, however, may be erased, written, and read in blocks (or pages), which generally are much smaller than
9100-459: The relatively thin oxide, gradually degrading its electrically insulating properties and allowing electrons to be trapped in and pass through freely (leak) from the floating gate into the oxide, increasing the likelihood of data loss since the electrons (the quantity of which is used to represent different charge levels, each assigned to a different combination of bits in MLC Flash) are normally in
9200-432: The same area. When these systems are used on flash memory media, this becomes a problem. The problem is aggravated by the fact that some file systems track last-access times, which can lead to file metadata being constantly rewritten in-place. There are three basic types of wear leveling mechanisms used in flash memory storage devices: A flash memory storage system with no wear leveling will not last very long if data
9300-410: The same bitline. A flash die consists of one or more planes, and the peripheral circuitry that is needed to perform all the read, write, and erase operations. The architecture of NAND flash means that data can be read and programmed (written) in pages, typically between 4 KiB and 16 KiB in size, but can only be erased at the level of entire blocks consisting of multiple pages. When a block is erased, all
9400-540: The same location on the disk surface as the original file, whereas in SSDs the new copy will often be written to different NAND cells for the purpose of wear leveling . The wear-leveling algorithms are complex and difficult to test exhaustively. As a result, one major cause of data loss in SSDs is firmware bugs. While both memory cards and most SSDs use flash memory, they have very different characteristics, including power consumption, performance, size, and reliability. Originally, solid state drives were shaped and mounted in
9500-407: The same silicon nitride material. An individual memory cell is made up of one planar polysilicon layer containing a hole filled by multiple concentric vertical cylinders. The hole's polysilicon surface acts as the gate electrode. The outermost silicon dioxide cylinder acts as the gate dielectric, enclosing a silicon nitride cylinder that stores charge, in turn enclosing a silicon dioxide cylinder as
9600-607: The serial-linked groups in which conventional NAND flash memory is configured. There is also string stacking, which builds several 3D NAND memory arrays or "plugs" separately, but stacked together to create a product with a higher number of 3D NAND layers on a single die. Often, two or 3 arrays are stacked. The misalignment between plugs is in the order of 30 to 10nm. Growth of a group of V-NAND cells begins with an alternating stack of conducting (doped) polysilicon layers and insulating silicon dioxide layers. Wear leveling Wear leveling (also written as wear levelling )
9700-442: The signaling methods used to communicate between the SSD and the host system. This interface is managed by the SSD's controller and is often similar to those found in traditional hard disk drives (HDDs). Common interfaces include: SSDs may support various logical interfaces, which define the command sets used by operating systems to communicate with the SSD. Two common logical interfaces include: NAND flash Flash memory
9800-637: The storage system would, and can be managed in a number of forms, such as a distributed key-value database and a distributed file system . On supercomputers, this layer is typically referred to as burst buffer . Flash-based solid-state drives can be used to create network appliances from general-purpose personal computer hardware. A write protected flash drive containing the operating system and application software can substitute for larger, less reliable disk drives or CD-ROMs. Appliances built this way can provide an inexpensive alternative to expensive router and firewall hardware. SSDs based on an SD card with
9900-418: The tunnel dielectric that surrounds a central rod of conducting polysilicon which acts as the conducting channel. Memory cells in different vertical layers do not interfere with each other, as the charges cannot move vertically through the silicon nitride storage medium, and the electric fields associated with the gates are closely confined within each layer. The vertical collection is electrically identical to
10000-417: Was first announced by Toshiba in 2007. V-NAND was first commercially manufactured by Samsung Electronics in 2013. V-NAND uses a charge trap flash geometry (which was commercially introduced in 2002 by AMD and Fujitsu ) that stores charge on an embedded silicon nitride film. Such a film is more robust against point defects and can be made thicker to hold larger numbers of electrons. V-NAND wraps
#325674