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71-553: Peripheral Component Interconnect ( PCI ) is a local computer bus for attaching hardware devices in a computer and is part of the PCI Local Bus standard. The PCI bus supports the functions found on a processor bus but in a standardized format that is independent of any given processor 's native bus. Devices connected to the PCI bus appear to a bus master to be connected directly to its own bus and are assigned addresses in

142-454: A 100-pin stacking connector, while Type III uses a 124-pin edge connector, i.e. the connector for Types I and II differs from that for Type III, where the connector is on the edge of a card, like with a SO-DIMM . The additional 24 pins provide the extra signals required to route I/O back through the system connector (audio, AC-Link , LAN , phone-line interface). Type II cards have RJ11 and RJ45 mounted connectors. These cards must be located at

213-538: A 32-bit bus, but the system also supported a 16-bit mode designed to lower the cost of connectors and logic in Intel -based machines like the IBM PS/2 . The situation was never that simple, however, as both the 32-bit and 16-bit versions initially had a number of additional optional connectors for memory cards which resulted in a huge number of physically incompatible cards for bus attached memory. In time, memory moved to

284-495: A computer is first turned on, all PCI devices respond only to their configuration space accesses. The computer's BIOS scans for devices and assigns Memory and I/O address ranges to them. If an address is not claimed by any device, the transaction initiator's address phase will time out causing the initiator to abort the operation. In case of reads, it is customary to supply all-ones for the read data value (0xFFFFFFFF) in this case. PCI devices therefore generally attempt to avoid using

355-538: A customized floppy disk (that came with the PC) to blend the new card into the original hardware automatically, rather than bringing in an expensively trained technician who could manually make all the needed changes. All choices for interrupts (an often perplexing problem) and other changes were accomplished automatically by the PC reading the old configuration from the floppy disk, which made necessary changes in software, then wrote

426-403: A dedicated bus controller that utilized burst mode transfers, meant that effective throughput was up to five times higher than ISA. For faster transfers the address bus could be reused for data, further increasing the effective width of the bus. While the 10 MHz rate allowed 40 MB/s of throughput at 32-bit width, later models of RS/6000 machines increased the data rate to 20 MHz, and

497-420: A device signals its need for service by performing a memory write, rather than by asserting a dedicated line. This alleviates the problem of scarcity of interrupt lines. Even if interrupt vectors are still shared, it does not suffer the sharing problems of level-triggered interrupts. It also resolves the routing problem, because the memory write is not unpredictably modified between device and host. Finally, because

568-657: A few years of its arrival in 1992, PCI had largely superseded Micro Channel, EISA, and VLB. In response to the rise of EISA, IBM and thirteen Micro Channel card and peripheral manufacturers formed the Micro Channel Developers Association . This was a consortium that sought to consider and prioritize steps in the maturation of Micro Channel, as well as to explore better approaches to disseminating technical information about Micro Channel to third parties. In 1992, it reached 92 members, including IBM. Even after IBM discontinued MCA systems in 1995,

639-443: A master to use a burst-mode . Micro Channel cards had complete control for up to 12 milliseconds . This was long enough to permit the maximum number of other devices on the bus to buffer inbound data from over-runnable devices like tape and communications. Multiple bus-master support and improved arbitration mean that several such devices could coexist and share the system bus. Micro Channel bus-master-capable devices can even use

710-457: A number of technical design limitations, including: In addition, it suffered from other problems: These limitations became more serious as the range of tasks and peripherals, and the number of manufacturers for IBM PC-compatibles , grew. IBM was already investigating the use of RISC processors in desktop machines, and could, in theory, save considerable money if a single well-documented bus could be used across their entire computer lineup. It

781-473: A prisoner of its standards as its competitors are. Once enough IBM machines have been bought, IBM cannot make sudden changes in their basic design; what might be useful for shedding competitors would shake off even more customers. Micro Channel architecture was publicly introduced at the launch of the PS/2 range in 1987, with three out of four of the new machines featuring it. IBM had actually discreetly introduced

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852-497: A protocol so that the interrupt-request (IRQ) lines can be shared. The PCI bus includes four interrupt lines, INTA# through INTD#, all of which are available to each device. Up to eight PCI devices share the same IRQ line (INTINA# through INTINH#) in APIC -enabled x86 systems. Interrupt lines are not wired in parallel as are the other PCI bus lines. The positions of the interrupt lines rotate between slots, so what appears to one device as

923-418: A regular basis. A fairly complete list of known IDs is available (see External links section). To accompany these reference disks were ADF files which were read by setup which in turn provided configuration information for the card. The ADF was a simple text file, containing information about the card's memory addressing and interrupts. Although MCA cards cost nearly double the price of comparable non-MCA cards,

994-532: A single system board connector for graphics that could be upgraded. Micro Channel cards also featured a unique, 16-bit software-readable ID, which formed the basis of an early plug and play system. The BIOS and/or OS can read IDs, compare against a list of known cards, and perform automatic system configuration to suit. This led to boot failures whereby an older BIOS would not recognize a newer card, causing an error at startup. In turn, this required IBM to release updated Reference Disks (The CMOS Setup Utility) on

1065-564: A superset of PCI, before giving way to PCI Express. The first version of PCI found in retail desktop computers was a 32-bit bus using a 33  MHz bus clock and 5  V signaling, although the PCI 1.0 standard provided for a 64-bit variant as well. These have one locating notch in the card. Version 2.0 of the PCI standard introduced 3.3 V slots, physically distinguished by a flipped physical connector to prevent accidental insertion of 5 V cards. Universal cards, which can operate on either voltage, have two notches. Version 2.1 of

1136-488: A write must affect only the enabled bytes in the target PCI device. They are of little importance for memory reads, but I/O reads might have side effects. The PCI standard explicitly allows a data phase with no bytes enabled, which must behave as a no-op. PCI has three address spaces: memory, I/O address, and configuration. Memory addresses are 32 bits (optionally 64 bits) in size, support caching and can be burst transactions. I/O addresses are for compatibility with

1207-473: Is installed into a PCI-X bus capable of 133 MHz, the entire bus backplane will be limited to 66 MHz. To get around this limitation, many motherboards have two or more PCI/PCI-X buses, with one bus intended for use with high-speed PCI-X peripherals, and the other bus intended for general-purpose peripherals. Many 64-bit PCI-X cards are designed to work in 32-bit mode if inserted in shorter 32-bit connectors, with some loss of performance. An example of this

1278-450: Is meant to know this, and set the "interrupt line" field in each device's configuration space indicating which IRQ it is connected to. PCI interrupt lines are level-triggered . This was chosen over edge-triggering to gain an advantage when servicing a shared interrupt line, and for robustness: edge-triggered interrupts are easy to miss. Later revisions of the PCI specification add support for message-signaled interrupts . In this system,

1349-491: Is required to implement a timer, called the Latency Timer, that limits the time that device can hold the PCI bus. The timer starts when the device gains bus ownership, and counts down at the rate of the PCI clock. When the counter reaches zero, the device is required to release the bus. If no other devices are waiting for bus ownership, it may simply grab the bus again and transfer more data. Devices are required to follow

1420-471: Is taken for granted now, but at the time setup was a huge chore for ISA systems. POS was a simple system that included device IDs in firmware, which the drivers in the computer were supposed to interpret. (This type of software-configuration system is known as plug and play today.) The feature did not really live up to its promise; the automatic configuration was fine when it worked, but it frequently did not - resulting in an unbootable computer - and resolving

1491-617: Is the Adaptec 29160 64-bit SCSI interface card. However, some 64-bit PCI-X cards do not work in standard 32-bit PCI slots. Installing a 64-bit PCI-X card in a 32-bit slot will leave the 64-bit portion of the card edge connector not connected and overhanging. This requires that there be no motherboard components positioned so as to mechanically obstruct the overhanging portion of the card edge connector. PCI brackets heights: PCI Card lengths (Standard Bracket & 3.3 V): PCI Card lengths (Low Profile Bracket & 3.3 V): Mini PCI

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1562-559: The CardBus . The first PCI specification was developed by Intel , but subsequent development of the standard became the responsibility of the PCI Special Interest Group ( PCI-SIG ). PCI and PCI-X sometimes are referred to as either Parallel PCI or Conventional PCI to distinguish them technologically from their more recent successor PCI Express , which adopted a serial , lane-based architecture. PCI's heyday in

1633-961: The IBM 9370 systems - smallest members of the System/370 range. IBM licensed the architecture to other companies for one to five percent of revenue. Tandy Corporation was the first to ship a Micro Channel-based computer, the 5000 MC, but company head John Roach said "I'm surprised anybody at all would want it"; Tandy only sold the computer, he said, because there was some demand for it. NCR Corporation adopted Micro Channel comprehensively - they designed and built high-performance personal computer, workstation and server platforms supporting it, including their own Micro Channel architecture-based logic componentry, including SCSI, graphics, networking, and audio. A small number of other manufacturers, including Apricot , Dell , Research Machines , and Olivetti adopted it, but only for part of their PC range. Despite

1704-530: The Intel Architecture Labs (IAL, also Architecture Development Lab) c.  1990 . A team of primarily IAL engineers defined the architecture and developed a proof of concept chipset and platform (Saturn) partnering with teams in the company's desktop PC systems and core logic product organizations. PCI was immediately put to use in servers, replacing Micro Channel architecture (MCA) and Extended Industry Standard Architecture (EISA) as

1775-428: The 'component side': if the card is held with the connector pointing down, a view of side A will have the backplate on the right, whereas a view of side B will have the backplate on the left. The pinout of B and A sides are as follows, looking down into the motherboard connector (pins A1 and B1 are closest to backplate). 64-bit PCI extends this by an additional 32 contacts on each side which provide AD[63:32], C/BE[7:4]#,

1846-540: The 16-bit AT bus, (embraced and renamed as ISA to avoid IBM's "AT" trademark) and manual configuration, although the VESA Local Bus (VLB) was briefly popular for Intel '486 machines. For servers the technical limitations of the old ISA were too great, and, in late 1988, the " Gang of Nine ", led by Compaq , announced a rival high-performance bus - Extended Industry Standard Architecture (EISA). This offered similar performance benefits to Micro Channel, but with

1917-454: The CPU's local bus , thereby eliminating the problem. On the upside, signal quality was greatly improved as Micro Channel added ground and power pins and arranged the pins to minimize interference; a ground or a supply was thereby located within 3 pins of every signal. Another connector extension was included for graphics cards . This extension was used for analog output from the video card, which

1988-514: The INTA# line is INTB# to the next and INTC# to the one after that. Single-function devices usually use their INTA# for interrupt signaling, so the device load is spread fairly evenly across the four available interrupt lines. This alleviates a common problem with sharing interrupts. The mapping of PCI interrupt lines onto system interrupt lines, through the PCI host bridge, is implementation-dependent. Platform-specific firmware or operating system code

2059-564: The Intel x86 architecture 's I/O port address space. Although the PCI bus specification allows burst transactions in any address space, most devices only support it for memory addresses and not I/O. Finally, PCI configuration space provides access to 256 bytes of special configuration registers per PCI device. Each PCI slot gets its own configuration space address range. The registers are used to configure devices memory and I/O address ranges they should respond to from transaction initiators. When

2130-729: The Micro Channel architecture in October 1986, half a year before the introduction of the IBM PS/2, as part of their "Gearbox" Industrial Computer 7552 series. These computers were rack-mountable, ruggedized, modular industrial PCs . They featured a hybrid 16-bit MCA and ISA bus, with certain ISA signal lines disabled. The use of MCA in IBM spread to the RS/6000 , AS/400 , and eventually to

2201-451: The PAR64 parity signal, and a number of power and ground pins. Most lines are connected to each slot in parallel. The exceptions are: Notes: Most 32-bit PCI cards will function properly in 64-bit PCI-X slots, but the bus clock rate will be limited to the clock frequency of the slowest card, an inherent limitation of PCI's shared bus topology. For example, when a PCI 2.3, 66-MHz peripheral

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2272-410: The PC's cards. After this experience repeated itself thousands of times, business leaders realized their dream scenario for upgrade simplicity did not work in the corporate world, and they sought a better process. The basic data rate of the Micro Channel was increased from ISA's 8 MHz to 10 MHz. This may have been a modest increase in terms of clock rate, but the greater bus width, coupled with

2343-408: The PCI bus. Any number of bus masters can reside on the PCI bus, as well as requests for the bus. One pair of request and grant signals is dedicated to each bus master. Typical PCI cards have either one or two key notches, depending on their signaling voltage. Cards requiring 3.3 volts have a notch 56.21 mm from the card backplate; those requiring 5 volts have a notch 104.41 mm from

2414-415: The PCI standard introduced optional 66 MHz operation. A server-oriented variant of PCI, PCI Extended ( PCI-X ) operated at frequencies up to 133 MHz for PCI-X 1.0 and up to 533 MHz for PCI-X 2.0. An internal connector for laptop cards, called Mini PCI , was introduced in version 2.2 of the PCI specification. The PCI bus was also adopted for an external laptop connector standard –

2485-433: The adaptation of PCI signaling to other form factors. Both PCI-X 1.0b and PCI-X 2.0 are backward compatible with some PCI standards. These revisions were used on server hardware but consumer PC hardware remained nearly all 32-bit, 33 MHz and 5 volt. The PCI-SIG introduced the serial PCI Express in c.  2004 . Since then, motherboard manufacturers have included progressively fewer PCI slots in favor of

2556-449: The all-ones value in important status registers, so that such an error can be easily detected by software. There are 16 possible 4-bit command codes, and 12 of them are assigned. With the exception of the unique dual address cycle, the least significant bit of the command code indicates whether the following data phases are a read (data sent from target to initiator) or a write (data sent from an initiator to target). PCI targets must examine

2627-469: The amount of memory and I/O address space needed by each device. Each device can request up to six areas of memory space or input/output (I/O) port space via its configuration space registers. In a typical system, the firmware (or operating system ) queries all PCI buses at startup time (via PCI Configuration Space ) to find out what devices are present and what system resources (memory space, I/O space, interrupt lines, etc.) each needs. It then allocates

2698-403: The backplate. This allows cards to be fitted only into slots with a voltage they support. "Universal cards" accepting either voltage have both key notches. The PCI connector is defined as having 62 contacts on each side of the edge connector , but two or four of them are replaced by key notches, so a card has 60 or 58 contacts on each side. Side A refers to the 'solder side' and side B refers to

2769-522: The bus configuration. It has subsequently been adopted for other computer types. Typical PCI cards used in PCs include: network cards , sound cards , modems , extra ports such as Universal Serial Bus ( USB ) or serial , TV tuner cards and hard disk drive host adapters . PCI video cards replaced ISA and VLB cards until rising bandwidth needs outgrew the abilities of PCI. The preferred interface for video cards then became Accelerated Graphics Port (AGP),

2840-458: The bus to talk directly to each other ( peer-to-peer ) at speeds faster than the system CPU, without any other system intervention. In theory, Micro Channel architecture systems could be expanded, like mainframes , with only the addition of intelligent masters, without periodic need to upgrade the central processor. Arbitration enhancement ensures better system throughput since control is passed more efficiently. Advanced interrupt handling refers to

2911-547: The command code as well as the address and not respond to address phases that specify an unsupported command code. The commands that refer to cache lines depend on the PCI configuration space cache line size register being set up properly; they may not be used until that has been done. Local bus Too Many Requests If you report this error to the Wikimedia System Administrators, please include

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2982-408: The consortium still held meetings and maintained a catalog of MCA devices online. A number of non-PS/2 computers were manufactured between the late 1980s and early 1990s. Such third-party computers were also referred to as PS/2 clones or MCA clones . The first third-party Micro Channel–based computer was Tandy Corporation 's 5000 MC in 1988. Despite expensive research and development costs on

3053-434: The consumer Performa product line (replacing LC Processor Direct Slot (PDS)) in mid-1996. Outside the server market, the 64-bit version of plain PCI remained rare in practice though, although it was used for example by all (post-iMac) G3 and G4 Power Macintosh computers . Later revisions of PCI added new features and performance improvements, including a 66  MHz 3.3  V standard and 133 MHz PCI-X , and

3124-429: The data phases must be in the same direction. Either party may pause or halt the data phases at any point. (One common example is a low-performance PCI device that does not support burst transactions , and always halts a transaction after the first data phase.) Any PCI device may initiate a transaction. First, it must request permission from a PCI bus arbiter on the motherboard. The arbiter grants permission to one of

3195-753: The desktop computer market was approximately 1995 to 2005. PCI and PCI-X have become obsolete for most purposes and has largely disappeared from many other modern motherboards since 2013; however they are still common on some modern desktops as of 2020 for the purposes of backward compatibility and the relative low cost to produce. Another common modern application of parallel PCI is in industrial PCs , where many specialized expansion cards, used here, never transitioned to PCI Express, just as with some ISA cards. Many kinds of devices formerly available on PCI expansion cards are now commonly integrated onto motherboards or available in USB and PCI Express versions. Work on PCI began at

3266-495: The details below. Request from 172.68.168.133 via cp1102 cp1102, Varnish XID 548584561 Upstream caches: cp1102 int Error: 429, Too Many Requests at Thu, 28 Nov 2024 05:45:29 GMT Micro Channel architecture The development of Micro Channel was driven by both technical and business pressures. The IBM AT bus, which later became known as the Industry Standard Architecture (ISA) bus, had

3337-549: The edge of the computer or docking station so that the RJ11 and RJ45 ports can be mounted for external access. Mini PCI is distinct from 144-pin Micro PCI. PCI bus traffic consists of a series of PCI bus transactions. Each transaction consists of an address phase followed by one or more data phases . The direction of the data phases may be from initiator to target (write transaction) or vice versa (read transaction), but all of

3408-506: The fact that MCA was a huge technical improvement over ISA, it soon became clear that its introduction and marketing by IBM was poorly handled. IBM had strong patents on Micro Channel architecture system features, and required Micro Channel system manufacturers to pay a licence fee - and actively pursued patents to block third parties from selling unlicensed implementations of it. The PC clone market did not want to pay royalties to IBM in order to use this new technology, and stayed largely with

3479-489: The initiator transmits the high 32 address bits, plus the real command code. The transaction operates identically from that point on. To ensure compatibility with 32-bit PCI devices, it is forbidden to use a dual address cycle if not necessary, i.e. if the high-order address bits are all zero. While the PCI bus transfers 32 bits per data phase, the initiator transmits 4 active-low byte enable signals indicating which 8-bit bytes are to be considered significant. In particular,

3550-406: The kinds of functions a Mini PCI card can perform. Many Mini PCI devices were developed such as Wi-Fi , Fast Ethernet , Bluetooth , modems (often Winmodems ), sound cards , cryptographic accelerators , SCSI , IDE – ATA , SATA controllers and combination cards. Mini PCI cards can be used with regular PCI-equipped hardware, using Mini PCI-to-PCI converters . Mini PCI has been superseded by

3621-468: The marketing stressed that it was simple for any user to upgrade or add more cards to their PC, thus saving the considerable expense of a technician. In this critical area, Micro Channel architecture's biggest advantage was also its greatest disadvantage, and one of the major reasons for its demise. To add a new card (video, printer, memory, network, modem, etc.) the user simply plugged in the MCA card and inserted

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3692-450: The marketplace. The overall reception was tepid and the impact of Micro Channel in the worldwide PC market was minor. The Micro Channel architecture was designed by engineer Chet Heath. A lot of the Micro Channel cards that were developed used the Chips and Technologies P82C612 MCA interface controller; allowing MCA implementations to become a lot easier. The Micro Channel was primarily

3763-621: The message signaling is in-band , it resolves some synchronization problems that can occur with posted writes and out-of-band interrupt lines. PCI Express does not have physical interrupt lines at all. It uses message-signaled interrupts exclusively. These specifications represent the most common version of PCI used in normal PCs: The PCI specification also provides options for 3.3 V signaling, 64-bit bus width, and 66 MHz clocking, but these are not commonly encountered outside of PCI-X support on server motherboards. The PCI bus arbiter performs bus arbitration among multiple masters on

3834-503: The much narrower PCI Express Mini Card Mini PCI cards have a 2 W maximum power consumption, which limits the functionality that can be implemented in this form factor. They also are required to support the CLKRUN# PCI signal used to start and stop the PCI clock for power management purposes. There are three card form factors : Type I, Type II, and Type III cards. The card connector used for each type include: Type I and II use

3905-541: The new IRQ for a new device—if a suitable one was available—for ISA was no fun at all, and beyond many users... it is obvious why the attempt was made to move to software-arbitrated configuration, and why this was to later succeed in the form of PnP .) In November 1983 The Economist stated that the IBM PC standard's dominance of the personal computer market was not a problem because "it can help competition to flourish". The magazine predicted that IBM will soon be as much

3976-446: The new configuration to the floppy disk. In practice, however, this meant that the user must keep that same floppy disk matched to that PC . For a small company with a few PCs, this was annoying, but practical. But for large organizations with hundreds or even thousands of PCs, permanently matching each PC with its own floppy disk was logistically unlikely or impossible. Without the original, updated floppy disk, no changes could be made to

4047-498: The new standard. Many new motherboards do not provide PCI slots at all, as of late 2013. PCI provides separate memory and memory-mapped I/O port address spaces for the x86 processor family, 64 and 32 bits , respectively. Addresses in these address spaces are assigned by software. A third address space, called the PCI Configuration Space , which uses a fixed addressing scheme, allows software to determine

4118-433: The operating system. In addition, there are PCI Latency Timers that are a mechanism for PCI Bus-Mastering devices to share the PCI bus fairly. "Fair" in this case means that devices will not use such a large portion of the available PCI bus bandwidth that other devices are not able to get needed work done. Note, this does not apply to PCI Express. How this works is that each PCI device that can operate in bus-master mode

4189-411: The part of third-party manufacturers of Micro Channel computers—in part due to the expensive licensing fees incurred by IBM in order to allow legal use of the Micro Channel technology—by 1990 most MCA clones were not fully compatible with the Micro Channel architecture or expansion cards based on Micro Channel. By the time IBM was winding down the PS/2 line of personal computers (which in 1987 acted as

4260-441: The problem by manual intervention was much more difficult than configuring an ISA system, not least because the documentation for the MCA device would tend to assume that the automatic configuration would work and so did not provide the necessary information to set it up by hand, unlike ISA device documentation which by necessity provided full details (however having to physically remove and check all IRQ settings, then find and set

4331-549: The processor's address space . It is a parallel bus, synchronous to a single bus clock . Attached devices can take either the form of an integrated circuit fitted onto the motherboard (called a planar device in the PCI specification) or an expansion card that fits into a slot. The PCI Local Bus was first implemented in IBM PC compatibles , where it displaced the combination of several slow Industry Standard Architecture (ISA) slots and one fast VESA Local Bus (VLB) slot as

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4402-527: The requesting devices. The initiator begins the address phase by broadcasting a 32-bit address plus a 4-bit command code, then waits for a target to respond. All other devices examine this address and one of them responds a few cycles later. 64-bit addressing is done using a two-stage address phase. The initiator broadcasts the low 32 address bits, accompanied by a special "dual address cycle" command code. Devices that do not support 64-bit addressing can simply not respond to that command code. The next cycle,

4473-549: The resources and tells each device what its allocation is. The PCI configuration space also contains a small amount of device type information, which helps an operating system choose device drivers for it, or at least to have a dialogue with a user about the system configuration. Devices may have an on-board read-only memory (ROM) containing executable code for x86 or PA-RISC processors, an Open Firmware driver, or an Option ROM . These are typically needed for devices used during system startup, before device drivers are loaded by

4544-460: The server expansion bus of choice. In mainstream PCs, PCI was slower to replace VLB , and did not gain significant market penetration until late 1994 in second-generation Pentium PCs. By 1996, VLB was all but extinct, and manufacturers had adopted PCI even for Intel 80486 (486) computers. EISA continued to be used alongside PCI through 2000. Apple Computer adopted PCI for professional Power Macintosh computers (replacing NuBus ) in mid-1995, and

4615-542: The system's CPU. Likewise, bus master request and grant signals were public, such that bus attached devices could monitor latency to control internal buffering for I/O processors. These features were not adopted for PCI, requiring all I/O support to come uniquely from the system board processor. The final major Micro Channel architecture improvement was POS , the Programmable Option Select , which allowed all setup to take place in software. This feature

4686-550: The throughput to 80 MB/s. Some higher throughput functions of the Micro Channel bus were available to RS/6000 platform only, and were not initially supported on cards operating on an Intel platform. With bus mastering , each card could talk to another directly. This allowed performance that was independent of the CPU. One potential drawback of multi-master design was the possible collisions when more than one card would try to bus master, but Micro Channel included an arbitration feature to correct for these situations, and also allowed

4757-415: The twin advantage of being able to accept older ISA boards and being free from IBM's control. For several years EISA and Micro Channel battled it out in the server arena, but, in 1996, IBM effectively conceded defeat, when they themselves produced some EISA-bus servers. In 2001 IBM executive Robert Moffat said that of the company's mistakes in the PC market, "the most obvious one is Micro Channel". Within

4828-510: The use of level-sensitive interrupts to handle system requests. Rather than a dedicated interrupt line, several lines can be shared to provide more possible interrupts, addressing the ISA-bus interrupt line conflict problems. All interrupt request signals were "public" on Micro Channel architecture permitting any card on the bus to function as an I/O processor for direct service of I/O device interrupts. ISA had limited all such processing to just

4899-449: Was added to PCI version 2.2 for use in laptops and some routers; it uses a 32-bit, 33 MHz bus with powered connections (3.3 V only; 5 V is limited to 100 mA) and support for bus mastering and DMA . The standard size for Mini PCI cards is approximately a quarter of their full-sized counterparts. There is no access to the card from outside the case, unlike desktop PCI cards with brackets carrying connectors. This limits

4970-426: Was then routed through the system board to the system's own monitor output. The advantage of this was that Micro Channel system boards could have a basic VGA or MCGA graphics system on board, and higher-level graphics ( XGA or other accelerator cards) could then share the same port. The add-on cards were then able to be free of ' legacy ' VGA modes, making use of the on-board graphics system when needed, and allowing

5041-417: Was thought that by creating a new standard, IBM would regain control of standards via the required licensing. As patents can take three years or more to be granted, however, only those relating to ISA could be licensed when Micro Channel was announced. Patents on important Micro Channel features, such as Plug and Play automatic configuration, were not granted to IBM until after PCI had replaced Micro Channel in

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