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32-462: The Q-bus is a less expensive version of Unibus using multiplexing so that address and data signals share the same wires. This allows both a physically smaller and less-expensive implementation of essentially the same functionality. Over time, the physical address range of the Q-bus was expanded from 16 to 18 and then 22 bits. Block transfer modes were also added to the Q-bus. The Q-bus is arranged as

64-750: A backplane. The edge connectors on the modules are split into individual "fingers," similarly to Unibus modules, but are limited to four connectors, compared to the six of Unibus. Modules are available in either double-height (two connectors) or quad-height (four connectors) sizes. This nomenclature is somewhat non-intuitive, as the difference between the two is actually the width of the PCB. Quad-height modules tend to be used for CPUs, memory, video processors, and other high-bandwidth components, whereas double-height modules tend to be used for interface cards, connector breakout boards, real-time clocks, ROM/microcode, and other relatively low-bandwidth components. Some exceptions are

96-468: A lesser extent, international programmers. The history of this CPU stems from the early 1970s, when the group of engineers in Zelenograd 's Special Computing Center, led by D.I. Yuditsky, developed their first 16-bit minicomputer , called Elektronika NC-1. This machine, intended to directly compete with SM EVM series, was first released in 1973 and used the bit slice 4-bit 587 CPU, sometimes called

128-458: A microcontroller, so it was decided to simplify the chip, removing unnecessary devices from the die . But by that time its parent organization, the SCC, has already lost in the power games that plagued Soviet industry. By its nature, Soviet industry was an extremely bureaucratic structure, so decision making process was often driven not by technical or economical considerations, but by the results of

160-556: A series of modules installed in one or more backplanes . Like the Unibus before it, the Q-bus uses: Memory-mapped I/O means that data cycles between any two devices, whether CPU, memory, or I/O devices, use the same protocols. On the Unibus, a range of physical addresses are dedicated for I/O devices. The Q-bus simplifies this design by providing a specific signal (originally called BBS7 , Bus Bank Select 7 but later generalized to be called BBSIO , Bus Bank Select I/O ) that selects

192-738: Is placed in the master devices. Similarly, the complexities of handling interrupt transactions are concentrated into the single Interrupt-Fielding Processor (the PDP-11 or VAX-11 computer) in the system. The design of the Q-bus was very closely related to the design of the Unibus both in spirit and in detailed implementation. Adapters were available from Digital and from third parties that allow Q-bus devices to be connected to Unibus-based computers and vice versa. A number of I/O devices were available in either Unibus or Q-bus flavors; some of these devices have minor differences while many others were essentially identical. In Soviet systems (see 1801 series CPU ),

224-670: The Interrupt Fielding Processor at any of four interrupt priority levels . Within a given level, the cards closer to the IFP (at the front of the bus) take priority over cards further back on the bus. Interrupts are vectored : a card requesting an interrupt has its interrupt vector read by the IFP. In this way, the interrupts from all I/O cards in the system can be distinguished with no ambiguity. Q-bus modules are configured as printed-circuit boards with gold-plated card-edge connectors which mate with corresponding slots on

256-451: The Master of the Q-bus. This master device can initiate data transactions which can then be responded to by a maximum of one selected slave device . (This had no effect on whether a given bus cycle is reading or writing data; the bus master can command either type of transaction.) At the end of the bus cycle, a bus arbitration protocol then selects the next device to be given mastery of

288-426: The central processing unit to communicate with main memory , as well as a peripheral bus , allowing peripherals to send and receive data. Unifying these formerly separate busses allowed external devices to easily perform direct memory access (DMA) and made the construction of device drivers easier as control and data exchange was all handled through memory-mapped I/O . Unibus was physically large, which led to

320-606: The Electronica NC instruction set . Others have an updated microcode implementing the LSI-11 architecture. Various models differed in clock speed, instruction set (the first models lacked the MUL and DIV commands, for example), package and address bus width (the latest models supported 22-bit addressing). In terms of raw processing power, it is roughly comparable to US-made Intel 286 . It has two different address spaces and

352-468: The Q-Bus architecture is called МПИ ( Магистральный Параллельный Интерфейс , or parallel bus interface). Its main difference is that it supports up to four processors on the same bus. Otherwise it is completely binary and electrically compatible with the standard Q-Bus, except for the physical layout of connectors. The Q-Bus supports 6 basic transaction types: A wide range of module types are available for

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384-416: The Q-Bus. Generally, they can be categorized as: A wide range of interface cards are available for the Q-Bus. Various Q-bus modules can be dual-width (two sets of fingers, half the total width of the mounting), or quad-width (four sets of fingers, the full width of the mounting), indicating that the module occupies one-half of or all of the Q-bus mounting slot, respectively. Unibus The Unibus

416-443: The Q-bus contains 16, 18, or 22 BDAL ( Bus Data/Address Line ) lines. 16, 18, or 22 BDAL lines are used for the physical address portion of each bus cycle. Eight or 16 DBAL lines are then re-used for the data portion(s) of each bus cycle. Newer generations of the bus allow block mode transfer where a single bus address can be followed by more than one data cycle (with the transfers taking place at consecutive bus addresses). Because

448-717: The SCC was essentially disbanded, its technical base passing to the Angstrem plant while some of its research labs were joined to the Research Institute of Precision Technology (which didn't really need them), and others forming a research arm of the newly formed NPO Scientific Center. This sudden reorganization resulted in the abandonment of the Elektronika NC architecture (it continued only in CNCs based on an NC-1 machine, some of which are used up to this day) and

480-408: The address portion of each bus cycle can not transfer data, the use of block mode means fewer address cycles and more time for data cycles, allowing increased bus data transfer bandwidth . Bus mastery is awarded based on an I/O card's topological proximity to the bus arbitrator (at the logical front of the bus); closer cards are granted priority over further cards. Interrupts can be delivered to

512-586: The adoption of the PDP-11 compatibility as a MEI standard, a process sometimes called PDP revolt in Russian literature. Thus, the microcode for the new simplified CPU was redesigned and made compatible with LSI-11 instruction set . The new processor was released in 1982, designated K1801VM1 . It was supplemented by the 600-gate KR1801VP1 ( Russian : КР1801ВП1 ) gate array , which was used to implement various support circuitry, 64 Kib KR1801RE2 ROM chip, and 64 Kib K573RF3 EPROM . Together they constituted

544-464: The bus, typically on a terminator card. Type 2 lines are selectively propagated by each card to the next slot – if the card wants to keep the request grant it will assert the SACK line and not propagate the request to the next slot. If a slot is empty, it is necessary to install a "grant continuity card" in the slot to propagate the four type 2 signals to the next card. Type 3 signals are generated by

576-446: The bus. Asynchronous signaling means that the bus has no fixed cycle time; the duration of any particular data transfer cycle on the bus is determined solely by the master and slave devices participating in the current data cycle. These devices use handshake signals to control the timing of the data cycle. Timeout logic within the master device limits the maximum allowed length of any given bus cycle. Depending on its generation,

608-458: The complex logic required to implement asynchronous data transfers is forced into the relatively few master devices. For interrupts, only the interrupt-fielding processor needs to contain the complex timing logic. The result is that most I/O controllers can be implemented with simple logic, and most of the critical logic is implemented as a custom MSI IC . Type 1 lines are a normal multi-sender wired-OR bus with pull-up resistors at each end of

640-439: The current bus master is still performing data transfers. The 18 address lines allow the addressing of a maximum of 256 KB. Typically, the top 8 KB is reserved for the registers of the memory-mapped I/O devices used in the PDP-11 architecture. The design deliberately minimizes the amount of redundant logic required in the system. For example, a system always contains more slave devices than master devices so most of

672-464: The double-height LSI-11/2, KDF11-A, and KDJ11-A CPUs, and many early small-capacity memory modules. As with the Unibus, the signaling was carefully optimized so that the minimum amount of logic is required across the entire bus system. Asynchronous signaling is used but de-skewing of addresses and data is the responsibility of the current bus master, minimizing the complexity of the bus slave devices. The responsibility for timing-out failed bus cycles also

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704-414: The first Soviet microprocessor ever. Its descendants proved popular and were widely used in various control systems and telecom equipment. However, the bit-slice nature of their CPUs made these machines somewhat unwieldy, especially in military applications, and the need for a single-chip microprocessor was identified. In 1980 the first 1801 CPU intended to fill this niche, K1801VE1 , entered production. It

736-518: The first widely used generation of 1801 family. The KR18101VP1 gate array was later manufactured by a number of second sources: Exiton Pavlovsky Posad , SEMZ Solnechnogorsk , and Intermos in Hungary. All CPUs in the family were single-chip 16-bit microprocessors based on Elektronika NC  [ ru ] microarchitecture , however only the first one, the K1801VE1 microcontroller , used

768-496: The games of influence between various organizations and officials. SCC, despite its technical successes and popularity of its designs, was not without its opponents and even enemies. While its staff had an aversion to copying and reverse engineering Western technology, many groups within the Ministry of Electronic Industry argued for it as a quicker and more secure way to meet the needs. These groups eventually prevailed, and in 1976

800-531: The indigenous Elektronika NC  [ ru ] microarchitecture cores, but binary compatible with DEC's PDP-11 machines. First released in 1980, various models and variants of the series were among the most popular Soviet microprocessors and dominated embedded systems and military applications of the 1980s. They were also used in widely different areas such as graphing calculators ( Elektronika MK-85  [ ru ] ) and industrial CNCs (Elektronika NC series), but arguably their most well-known use

832-467: The introduction of Q-bus , which multiplexed some signals to reduce pin count. Higher performance PDP systems used Fastbus, essentially two Unibusses in one. The system was later supplanted by Massbus , a dedicated I/O bus introduced on the VAX and late-model PDP-11s. The Unibus consists of 72 signals, usually connected via two 36-way edge connectors on each printed circuit board . When not counting

864-423: The power and ground lines, it is usually referred to as a 56-line bus. It can exist within a backplane or on a cable. Up to 20 nodes (devices) can be connected to a single Unibus segment; additional segments can be connected via a bus repeater . The bus is completely asynchronous , allowing a mixture of fast and slow devices. It allows the overlapping of arbitration (selection of the next bus master ) while

896-427: The power supply and have only a single sender. They warn the devices on the bus when the power is about to fail, so those devices can execute an orderly shutdown, and disable operations to prevent spurious writes. The two control lines (C0 and C1) allowed the selection of four different data transfer cycles: 1801 series CPU The 1801 series CPUs were a family of 16-bit Soviet microprocessors based on

928-514: The range of addresses used by the I/O devices. Byte addressing means that the physical address passed on the Unibus is interpreted as the address of a byte-sized quantity of data. Because the bus actually contains a data path that is two bytes wide, address bit [0] is subject to special interpretation and data on the bus has to travel in the correct byte lanes . A strict Master-Slave relationship means that at any point in time, only one device can be

960-415: Was essentially a microcontroller with 256 bytes of on-chip RAM , 2K ROM and other peripheral circuitry, still based on Elektronika NC instruction set , but compatible with a Soviet clone of DEC's Q-Bus that was already adopted as an industry standard — a first sign of things to come. Its peripheral circuits were underutilized by the industry, as it was mostly used as a general-purpose CPU, rather than

992-627: Was in several Soviet general-purpose mini- and microcomputer designs like the SM EVM , DVK , UKNC , and BK families. Due to being the CPU of the popular Elektronika BK home computer , used in its late years as a demo machine , as well as the DVK micros that often offered a first glimpse into the UNIX world, this processor achieved something of a cult status among Soviet and then Russian programmers, and to

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1024-504: Was the earliest of several computer bus and backplane designs used with PDP-11 and early VAX systems manufactured by the Digital Equipment Corporation (DEC) of Maynard , Massachusetts . The Unibus was developed around 1969 by Gordon Bell and student Harold McFarland while at Carnegie Mellon University . The name refers to the unified nature of the bus; Unibus was used both as a system bus allowing

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