TLCS is a prefix applied to microcontrollers made by Toshiba . The product line includes multiple families of CISC and RISC architectures. Individual components generally have a part number beginning with "TMP". E.g. the TMP8048AP is a member of the TLCS-48 family.
26-628: The TLCS-12 was a 12-bit microprocessor and central processing unit manufactured by Toshiba. It began development in 1971, and was completed in 1973. It was a 32 mm MOS integrated circuit chip with about 2,800 silicon gates , fabricated on a 6 μm process with NMOS logic . It was used in the Ford EEC engine control unit system, which began production in 1974 and went into mass production in 1975. The system memory included 512-bit RAM , 2 kb ROM and 2 kb EPROM . The TLCS-12A [ jp ] , an improved version of
52-402: A 12-bit resolution. Some PIC microcontrollers use a 12-bit word size. 12 binary digits, or 3 nibbles (a 'tribble'), have 4096 (10000 octal , 1000 hexadecimal ) distinct combinations. Hence, a microprocessor with 12-bit memory addresses can directly access 4096 words (4 kW) of word-addressable memory. IBM System/360 instruction formats use a 12-bit displacement field which, added to
78-822: Is available for free. The free Small Device C Compiler supports the TLCS-90. There is a project for porting GNU assembler to the TLCS-900 family. Alfred Arnold's The Macroassembler AS [1] is a free assembler supporting the TLCS-47, TLCS-870, TLCS-90, TLCS-900 and TLCS-9000 families. 12-bit computing In computer architecture , 12-bit integers , memory addresses , or other data units are those that are 12 bits (1.5 octets) wide. Also, 12-bit central processing unit (CPU) and arithmetic logic unit (ALU) architectures are those that are based on registers , address buses , or data buses of that size. Before
104-426: Is execute a usually linear sequence of instructions. Such a PC is central to the von Neumann architecture . Thus programmers write a sequential control flow even for algorithms that do not have to be sequential. The resulting “ von Neumann bottleneck ” led to research into parallel computing , including non-von Neumann or dataflow models that did not use a PC; for example, rather than specifying sequential steps,
130-452: Is unusual in that the prefix specifies one operand of the extended instruction, and unlike the single-byte prefixes used by the Z80 or x86 architecture, may itself be followed by operand bytes. After the prefix bytes, the second opcode byte specifies the operation and second operand. For example, the instruction ADD (IX+127),5 is encoded as F4 7F 68 05 , where the first two bytes specify
156-544: The Z80 . These are no longer advertised on the Toshiba website. The TLCS-90 inherits most Z80 features, such as: There are, however, significant differences. It omits the separate I/O address space of the Z80, but adds more flexibility to operand combinations, some new operations (notably multiply and divide), and several additional addressing modes : Most of the functionality of 8-bit accumulator A has also been implemented for
182-529: The instruction address register ( IAR ), the instruction counter , or just part of the instruction sequencer, is a processor register that indicates where a computer is in its program sequence. Usually, the PC is incremented after fetching an instruction , and holds the memory address of (" points to") the next instruction that would be executed. Processors usually fetch instructions sequentially from memory, but control transfer instructions change
208-500: The 16-bit HL register pair, such as the missing SUB and CP instructions, and the AND , XOR , and OR bitwise instructions. The ADD HL,rr flag quirk from the Z80 is implemented. Furthermore, the DJNZ BC,addr instruction was added to ease 16-bit loop counting. TLCS-90 SoC packages include the 4-bit BX and BY registers, which get concatenated with effective addresses based on
234-469: The 16-bit register SR) has an alternate register called F'. Executing EX AF,AF' from the TLCS-90 requires executing both EX A,A' and EX F,F' . The TLCS-900 also includes 4 "microDMA" transfer channels, each of which have programmable source and destination addresses, transfer counts, data sizes (byte, word, and longword), and various transfer modes. These are triggered the same way as normal interrupts, and interrupt program execution upon
260-456: The CPU may compute some other value and load it into the PC by a pulse to its LOAD input. To identify the current instruction, the PC may be combined with other registers that identify a segment or page . This approach permits a PC with fewer bits by assuming that most memory units of interest are within the current vicinity. Use of a PC that normally increments assumes that what a computer does
286-453: The CPU places the value of the PC on the address bus to send it to the memory. The memory responds by sending the contents of that memory location on the data bus . (This is the stored-program computer model, in which a single memory space contains both executable instructions and ordinary data. ) Following the fetch, the CPU proceeds to execution , taking some action based on the memory contents that it obtained. At some point in this cycle,
SECTION 10
#1732794381348312-623: The IX or IY register, allowing the processor to address up to one megabyte of memory. The processor includes the INCX ($ FF00+n) and DECX ($ FF00+n) instructions, which are useful for performing 20-bit pointer arithmetic using the IX and BX registers or the IY and BY registers. Instructions are divided into one-byte basic and two-byte extended instructions. Opcodes E0 16 through FE 16 are prefixes which begin an extended instruction. The instruction encoding
338-412: The PC somewhere. A return retrieves the saved contents of the PC and places it back in the PC, resuming sequential execution with the instruction following the subroutine call. In a simple central processing unit (CPU), the PC is a digital counter (which is the origin of the term "program counter") that may be one of several hardware registers . The instruction cycle begins with a fetch , in which
364-413: The PC will be modified so that the next instruction executed is a different one (typically, incremented so that the next instruction is the one starting at the memory address immediately following the last memory location of the current instruction). Like other processor registers, the PC may be a bank of binary latches, each one representing one bit of the value of the PC. The number of bits (the width of
390-463: The PC) relates to the processor architecture. For instance, a “32-bit” CPU may use 32 bits to be able to address 2 units of memory. On some processors, the width of the program counter instead depends on the addressable memory; for example, some AVR microcontrollers have a PC which wraps around after 12 bits. If the PC is a binary counter, it may increment when a pulse is applied to its COUNT UP input, or
416-514: The TLCS-12, was announced in 1975. The microcontrollers in the TLCS-47 category are 4-bit systems. These are no longer advertised on the Toshiba website. The TLCS-48 family were clones of the Intel MCS-48 (8048) microcontroller. These were a series of Zilog Z80 compatible microcontrollers. The microcontrollers in the TLCS-90 family use a 8-bit / 16-bit architecture reminiscent of
442-597: The TLCS-90 architecture, and includes 32-bit registers and a 24-bit address bus. Most implementations (TLCS-900, TLCS-900/L, TLCS-900/H and TLCS-900/L1 series) have 16-bit internal data paths, like the MC68000 , while the TLCS-900/H1 series is 32 bits wide internally (like the MC68020 ). The instruction set is mostly upward-compatible with the TLCS-90, although the binary encoding differs. The same scheme of encoding
468-456: The addressing mode before the instruction's opcode and additional operands is implemented. The early models supported both a "minimum mode" where the banked registers and program counter were 16 bits wide, and a "maximum mode" which had all 32-bit general purpose registers. Later models omitted the minimum mode. In maximum mode, there are 4 banks of four 32-bit registers, each of which can be split into two 16-bit halves or four 8-bit quarters. In
494-454: The contents of a base register, can address 4096 bytes of memory in a region that begins at the address in the base register. This computer hardware article is a stub . You can help Misplaced Pages by expanding it . Program counter The program counter ( PC ), commonly called the instruction pointer ( IP ) in Intel x86 and Itanium microprocessors , and sometimes called
520-516: The destination address, the third byte specifies the operation, and the fourth byte provides the source operand. The microcontrollers in the TLCS-870 family (TLCS-870, TLCS-870/X, TLCS-870/C and TLCS-870/C1 series) use a 8-bit / 16-bit architecture inspired by the TLCS-90, but less like the Z80. The TLCS-870 is the original, with a 16-bit address space, which was extended in two different directions: The TLCS-900 family inherits most features from
546-415: The high-level programmer might specify desired function and the low-level programmer might specify this using combinatory logic . This research also led to ways to making conventional, PC-based, CPUs run faster, including: Modern high-level programming languages still follow the sequential-execution model and, indeed, a common way of identifying programming errors is with a “procedure execution” in which
SECTION 20
#1732794381348572-478: The minimum mode of early models, there are 8 banks of four 16-bit registers, which can be split into 8-bit halves. The processor can use the current bank (pointed to by the RFP field in the 16-bit status register SR), the previous bank to be compatible with the alternate register scheme of the TLCS-90, or any arbitrary bank number from 0 to 7. There is also a fixed set of four 32-bit registers, with one of them dedicated as
598-423: The sequence by placing a new value in the PC. These include branches (sometimes called jumps), subroutine calls, and returns . A transfer that is conditional on the truth of some assertion lets the computer follow a different sequence under different conditions. A branch provides that the next instruction is fetched from elsewhere in memory. A subroutine call not only branches but saves the preceding contents of
624-428: The stack pointer. Early models had two separate stack pointers for user and system modes. Normally, only a set of 8 registers can be addressed from a 3-bit code; addressing all registers requires an additional 6/8-bit code byte that can only be inserted in the prefixed addressing mode operand, restricting which combinations of registers can be used for the source and destination operands. The F register (low 8-bit half of
650-567: The transferring process. The TLCS-900/H model was most prominently used in the Neo Geo Pocket and Neo Geo Pocket Color . Current TLCS processors offer some or all of the following features: As demand for these features differs widely depending on the requirements for a specific project (low energy consumption; high number of I/O ports; etc.), customers can choose from a wide range of different versions. Toshiba offers an ANSI C compatible C compiler and an assembler . Neither tool
676-569: The widespread adoption of ASCII in the late 1960s, six-bit character codes were common and a 12-bit word, which could hold two characters, was a convenient size. This also made it useful for storing a single decimal digit along with a sign. Possibly the best-known 12-bit CPU is the PDP-8 and its relatives, such as the Intersil 6100 microprocessor produced in various forms from August 1963 to mid-1990. Many analog to digital converters (ADCs) have
#347652