The Data General Nova is a series of 16-bit minicomputers released by the American company Data General . The Nova family was very popular in the 1970s and ultimately sold tens of thousands of units.
81-457: The first model, known simply as "Nova", was released in 1969. The Nova was packaged into a single 3U rack-mount case and had enough computing power to handle most simple tasks. The Nova became popular in science laboratories around the world. It was followed the next year by the SuperNOVA , which ran roughly four times as fast, making it the fastest mini for several years. Introduced during
162-473: A Serial Peripheral Interface in daisy chain configuration , which allows any number of binary devices to be accessed using only two to four pins, though more slowly than parallel I/O. For more outputs, SIPO shift registers are used. The parallel outputs of the shift register and the desired state for all those devices can be sent out of the microcontroller using a single serial connection. For more inputs, PISO shift registers are used. Each binary input (such as
243-423: A button or more complicated circuitry) is attached to a parallel input of the shift register, then the data is sent back serially to the microcontroller. Shift registers can also be used as pulse extenders. Compared to monostable multivibrators , the timing does not depend on component values, but it requires an external clock, and the timing accuracy is limited by the granularity of this clock. An example of such
324-871: A " bit array ". Data was stored into the array and read back out in parallel, often as a computer word , while each bit was stored serially in the shift registers. There is an inherent trade-off in the design of bit arrays; putting more flip-flops in a row allows a single shifter to store more bits, but requires more clock cycles to push the data through all of the shifters before the data can be read back out again. Shift registers can have both parallel and serial inputs and outputs. These are often configured as "serial-in, parallel-out" (SIPO) or as "parallel-in, serial-out" (PISO) . There are also types that have both serial and parallel input and types with serial and parallel output. There are also "bidirectional" shift registers, which allow shifting in both directions: L → R or R → L. The serial input and last output of
405-463: A "prefetcher" to increase performance by fetching up to 11 instructions from memory before they were needed. Data General also produced a series of microNOVA single-chip implementations of the Nova processor. To allow it to fit into a 40-pin dual in-line package (DIP) chip, the address bus and data bus shared a set of 16 pins. This meant that reads and writes to memory required two cycles, and that
486-404: A centrally located "board-on-a-board", 5.25" wide by 6.125" high, and was covered by a protective plate. It was surrounded by the necessary support driver read-write-rewrite circuitry. All of the core and the corresponding support electronics fit onto a single standard 15 x 15-inch (380 mm) board. Up to 32K of such core RAM could be supported in one external expansion box. Semiconductor ROM
567-452: A consortium of venture capital funds from the Boston area, who agreed to provide an initial US$ 400,000 investment with a second US$ 400,000 available for production ramp-up. de Castro, Burkhart and Sogge quit DEC and started Data General (DG) on 15 April 1968. Green did not join them, considering the venture too risky, and Richman did not join until the product was up and running later in
648-479: A demonstration of the power of their Micromatrix gate array technology, in 1968 Fairchild prototyped the 4711, a single-chip 4-bit ALU. The design was never intended for mass production and was quite expensive to produce. The introduction of the Signetics 8260 in 1969 forced their hand; both Texas Instruments and Fairchild introduced 4-bit ALUs of their own in 1970, the 74181 and 9341, respectively. In contrast to
729-531: A divisional manager; Richard Sogge, another hardware engineer; and Henry Burkhardt III, a software engineer. In contrast to the PDP-X, the new effort focused on a single machine that could be brought to market quickly, as de Castro felt the PDP-X concept was far too ambitious for a small startup company . Discussing it with the others at DEC, the initial concept led to an 8-bit machine which would be less costly to implement. The group began talking with Herbert Richman,
810-457: A matching high-performance version. Gruner's low-cost model launched in 1970 as the Nova 1200 , the 1200 referring to the use of the original Nova's 1,200 ns core memory. It featured a 4-bit ALU based on a single 74181 chip, and was thus essentially a repackaged Nova. Seligman's repackaged four-ALU SuperNOVA was released in 1971 as the Nova 800 , resulting in the somewhat confusing naming where
891-493: A measurement of the overall height of 19-inch and 23-inch rack frames , as well as the height of equipment that mounts in these frames, whereby the height of the frame or equipment is expressed as multiples of rack units. For example, a typical full-size rack cage is 42U high, while equipment is typically 1U, 2U, 3U, or 4U high. The rack unit size is based on a standard rack specification as defined in EIA -310. The Eurocard specifies
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#1732772404664972-642: A microprocessor version of the Nova in 1977, the Fairchild 9440 , but it also saw limited use in the market. The Nova line was succeeded by the Data General Eclipse , which was similar in most ways but added virtual memory support and other features required by modern operating systems . A 32-bit upgrade of the Eclipse resulted in the Eclipse MV series of the 1980s. Edson de Castro was
1053-418: A period of rapid progress in integrated circuit (or "microchip") design, the line went through several upgrades over the next five years, introducing the 800 and 1200, the Nova 2, Nova 3, and ultimately the Nova 4. A single-chip implementation was also introduced as the microNOVA in 1977, but did not see widespread use as the market moved to new microprocessor designs. Fairchild Semiconductor also introduced
1134-490: A pulse extender is the Ronja Twister , wherein five 74164 shift registers create the core of the timing logic this way ( schematic ). In early computers, shift registers were used to handle data processing: two numbers to be added were stored in two shift registers and clocked out into an arithmetic and logic unit (ALU) with the result being fed back to the input of one of the shift registers (the accumulator), which
1215-465: A salesman for Fairchild Semiconductor who knew the others through his contacts with DEC. At the time, Fairchild was battling with Texas Instruments and Signetics in the rapidly growing TTL market and were introducing new fabs that allowed more complex designs. Fairchild's latest 9300 series allowed up to 96 gates per chip, and they had used this to implement a number of 4-bit chips like binary counters and shift registers . Using these ICs reduced
1296-406: A separate slot. An additional option allowed for memory mapping, allowing programs to access up to 128 kwords of memory using bank switching . Unlike the earlier machines, the Nova 4 did not include a front panel console and instead included a ROM containing machine code that allows a terminal to emulate a console when needed. There were three different versions of the Nova 4, the Nova 4/C,
1377-472: A set of output registers. In general, the practical application of the serial-in/parallel-out shift register is to convert data from serial format on a single wire to parallel format on multiple wires. This configuration has the data input on lines D1 through D4 in parallel format, D1 being the most significant bit. To write the data to the register, the Write/Shift control line must be held LOW. To shift
1458-436: A shift register can also be connected to create a "circular shift register". A PIPO register (parallel in, parallel out) is simply a D-type register and is not a shift register, but is very fast – an output is given within a single clock pulse. A "universal" shift register provides bidirectional serial-in and serial-out, as well as parallel-in and parallel-out. These are the simplest kind of shift registers. The data string
1539-430: A standard rack unit as the unit of height; it also defines a similar unit, horizontal pitch (HP), used to measure the width of rack-mounted equipment. The standard was adopted worldwide as IEC 60297 Mechanical structures for electronic equipment – Dimensions of mechanical structures of the 482.6 mm (19 in) series , and defines the sizes for rack, subrack (a shelf-like chassis in which cards can be inserted), and
1620-414: Is a 4-bit register. To give an idea of the shifting pattern, imagine that the register holds 0000 (so all storage slots are empty). As "data in" presents 1,0,1,1,0,0,0,0 (in that order, with a pulse at "data advance" each time—this is called clocking or strobing) to the register, this is the result. The right hand column corresponds to the right-most flip-flop's output pin, and so on. So the serial output of
1701-507: Is a diverse but ardent group of people worldwide who restore and preserve original 16-bit Data General systems. The Nova, unlike the PDP-8 , was a load–store architecture . It had four 16-bit accumulator registers, two of which (2 and 3) could be used as index registers . There was a 15-bit program counter and a single-bit carry register. As with the PDP-8, current + zero page addressing
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#17327724046641782-473: Is also a "half rack width" size being used in IT applications where a device conforms to a smaller than 9.5-inch width so that these "half rack width" appliances may be used in a chassis system that fits the traditional 19-inch rack space, but allows for these 8.4-inch-wide "half rack width" appliances to be inserted and removed easily without tools or the need to remove adjacent hardware. This "half rack width" concept
1863-514: Is lost once it has been shifted out of the right-most bit. This configuration allows conversion from serial to parallel format. Data input is serial, as described in the SISO section above. Once the data has been clocked in, it may be either read off at each output simultaneously, or it can be shifted out. In this configuration, each flip-flop is edge triggered . All flip-flops operate at the given clock frequency. Each input bit makes its way down to
1944-554: Is no formal specification for "half rack", the term half-rack can have different separate meanings: It can describe equipment that fits in a certain number of rack units, but occupy only half the width of a 19-inch rack (9.5 inches (241.30 mm)). These are commonly used when a piece of equipment does not require full rack width, but may require more than 1U of height. For example, a "4U half-rack" DVCAM deck occupies 4U (7 in) height × 9.5 in width, and in theory, two 4U half-rack decks could be mounted side by side and occupy
2025-407: Is popular in applications where IT equipment is being used by military who are unable to use traditional 1U full-depth IT appliances due to their large size. Shift register A shift register is a type of digital circuit using a cascade of flip-flops where the output of one flip-flop is connected to the input of the next. They share a single clock signal , which causes the data stored in
2106-409: Is presented at "data in" and is shifted right one stage each time "data advance" is brought high . At each advance, the bit on the far left (i.e. "data in") is shifted into the first flip-flop 's output. The bit on the far right (i.e. "data out") is shifted out and lost. The data is stored after each flip-flop on the "Q" output, so there are four storage "slots" available in this arrangement, hence it
2187-453: The PDP-11 , a much more complex design that was as different from the PDP-X as the Nova was. The two designs competed heavily in the market. Rumors of the new system from DEC reached DG shortly after the Nova began shipping. In spring 1970 they hired a new designer, Larry Seligman, to leapfrog any possible machine in the making. Two major changes had taken place since the Nova was designed; one
2268-486: The input/output circuitry and a complete system typically included another board with 4 kB of random-access memory . A complete four-card system fit in a single rackmount chassis. The boards were designed so they could be connected together using a printed circuit backplane , with minimal manual wiring, allowing all the boards to be built in an automated fashion. This greatly reduced costs over 8/I, which consisted of many smaller boards that had to be wired together at
2349-460: The "program load" switch was flipped. Versions were available with four ("2/4"), seven and ten ("2/10") slots. The Nova 3 of 1975 added two more registers, used to control access to a built-in stack. The processor was also re-implemented using TTL components, further increasing the performance of the system. The Nova 3 was offered in four-slot (the Nova 3/4) and twelve-slot (the Nova 3/12) versions. It appears that Data General originally intended
2430-420: The 4U space. It can also describe a unit that is 1U high and half the depth of a 4-post rack (such as a network switch , router , KVM switch , or server ), such that two units can be mounted in 1U of space (one mounted at the front of the rack and one at the rear). When used to describe the rack enclosure itself, the term "half-rack" typically means a rack enclosure that is half the height (22U tall). There
2511-553: The 8260, the new designs offered all common logic functions and further reduced the chip count. This led DG to consider the design of a new CPU using these more integrated ICs. At a minimum, this would reduce the CPU to a single card for either the basic Nova or the SuperNOVA. A new concept emerged where a single chassis would be able to host either machine simply by swapping out the CPU circuit board. This would allow customers to purchase
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2592-475: The Nova 3 to be the last of its line, planning to replace the Nova with the later Eclipse machines. However, continued demand led to a Nova 4 machine introduced in 1978, this time based on four AMD Am2901 bit-slice ALUs . This machine was designed from the start to be both the Nova 4 and the Eclipse S/140, with different microcode for each. A floating-point co-processor was also available, taking up
2673-413: The Nova 4/S and the Nova 4/X. The Nova 4/C was a single-board implementation that included all of the memory (16 or 32 kwords). The Nova 4/S and 4/X used separate memory boards. The Nova 4/X had the on-board memory management unit (MMU) enabled to allow up to 128 kwords of memory to be used. The MMU was also installed in the Nova 4/S, but was disabled by firmware. Both the 4/S and the 4/X included
2754-436: The Nova computers, running under a range of consistent operating systems. FORTRAN IV , ALGOL , Extended BASIC, Data General Business Basic , Interactive COBOL , and several assemblers were available from Data General. Third-party vendors and the user community expanded the offerings with Forth , Lisp , BCPL , C , ALGOL , and other proprietary versions of COBOL and BASIC . The machine instructions implemented below are
2835-456: The Nova simple compared to competing machines. In addition to its dedicated I/O bus structure, the Nova backplane had wire wrap pins that could be used for non-standard connectors or other special purposes. The instruction format could be broadly categorized into one of three functions: 1) register-to-register manipulation, 2) memory reference, and 3) input/output. Each instruction was contained in one word. The register-to-register manipulation
2916-457: The Nth output after N clock cycles, leading to parallel output. In cases where the parallel outputs should not change during the serial loading process, it's desirable to use a latched or buffered output. In a latched shift register (such as the 74595 ) the serial data is first loaded into an internal buffer register, then upon receipt of a load signal the state of the buffer register is copied into
2997-536: The Product Manager of the pioneering Digital Equipment Corporation (DEC) PDP-8 , a 12-bit computer widely referred to as the first true minicomputer. He also led the design of the upgraded PDP-8/I, which used early integrated circuits in place of individual transistors. During the PDP-8/I process, de Castro had been visiting circuit board manufacturers who were making rapid advances in the complexity of
3078-515: The SuperNova. Future versions of the system added a stack unit and hardware multiply/divide. The Nova 4 / Eclipse S/140 was based on four AMD 2901 bit-slice ALUs, with microcode in read-only memory , and was the first Nova designed for DRAM main memory only, without provision for magnetic-core memory . The first models were available with 8 K words of magnetic-core memory as an option, one that practically everyone had to buy, bringing
3159-465: The backplane, which was itself connected together using wire wrap . The larger-board construction also made the Nova more reliable, which made it especially attractive for industrial or lab settings. The new design used a simple load–store architecture which would reemerge in the RISC designs in the 1980s. Because the complexity of a flip-flop was being rapidly reduced as they were implemented in chips,
3240-481: The boards they could assemble. de Castro concluded that the 8/I could be produced using fully automated assembly on large boards, which would have been impossible only a year earlier. Others within DEC had become used to the smaller boards used in earlier machines and were concerned about tracking down problems when there were many components on a single board. For the 8/I, the decision was made to stay with small boards, using
3321-458: The common set implemented by all of the Nova series processors. Specific models often implemented additional instructions, and some instructions were provided by optional hardware. All arithmetic instructions operated between accumulators. For operations requiring two operands, one was taken from the source accumulator, and one from the destination accumulator, and the result was deposited in the destination accumulator. For single-operand operations,
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3402-418: The company had annual sales of US$ 100 million . Ken Olsen had publicly predicted that DG would fail, but with the release of the Nova it was clear that was not going to happen. By this time, a number of other companies were talking about introducing 16-bit designs as well. Olsen decided these presented a threat to their 18-bit line as well as 12-bit, and began a new 16-bit design effort. This emerged in 1970 as
3483-408: The core with read-only memory ; lacking core's read–write cycle, this could be accessed in 300 ns for a dramatic performance boost. The resulting machine, known as the SuperNOVA , was released in 1970. Although the initial models still used core, the entire design was based on the premise that faster semiconductor memories would become available and the platform could make full use of them. This
3564-570: The data, the W/S control line is brought HIGH and the registers are clocked. The arrangement now acts as a PISO shift register, with D1 as the Data Input. However, as long as the number of clock cycles is not more than the length of the data-string, the Data Output, Q, will be the parallel data read off in order. The animation below shows the write/shift sequence, including the internal state of
3645-623: The design of both the Xerox Alto (1973) and Apple I (1976) computers, and its architecture was the basis for the Computervision CGP (Computervision Graphics Processor) series. Its external design has been reported to be the direct inspiration for the front panel of the MITS Altair (1975) microcomputer. Data General followed up on the success of the original Nova with a series of faster designs. The Eclipse family of systems
3726-470: The design offset the lack of addressing modes of the load–store design by adding four general-purpose accumulators , instead of the single register that would be found in similar low-cost offerings like the PDP series. Late in 1967, Richman introduced the group to New York-based lawyer Fred Adler, who began canvassing various funding sources for seed capital. By 1968, Adler had arranged a major funding deal with
3807-559: The earlier delay-line memory in some devices built in the early 1970s. Shift registers don't need many pins or address decoding logic, so was much cheaper than random-access memory back then. Such shift register memory was sometimes called circulating memory . Datapoint 3300 , for example, stored its terminal display of 25 rows of 72 columns of 6-bit upper-case characters using 54 200-bit shift registers (arranged in 6 tracks of 9 packs), providing storage for 1800 characters. The shift register design meant that scrolling
3888-522: The entire chipset to a single VLSI . This was offered in two machines, the microNOVA MP/100 and larger microNOVA MP/200 . The microNOVA was later re-packaged with a monitor in a PC-style case with two floppy disks as the Enterprise . Enterprise shipped in 1981, running RDOS , but the introduction of the IBM PC the same year made most other machines disappear under the radar. The Nova influenced
3969-413: The entire register is 00010110. It can be seen that if data were to be continued to input, it would get exactly what was put in (10110000), but offset by four "data advance" cycles. This arrangement is the hardware equivalent of a queue . Also, at any time, the whole register can be set to zero by bringing the reset (R) pins high. This arrangement performs destructive readout – each datum
4050-459: The full number of rack units would imply. Thus, a 1U front panel would be 1 23 ⁄ 32 inches (1.71875 in or 43.66 mm) tall. If n is number of rack units, the ideal formula for panel height is h = (1.75 n − 0.031) for calculating in inches, and h = (44.45 n − 0.794) for calculating in millimetres. Manufacturing allows for dimensions with less precision. The 19-inch rack format with rack units of 1.75 inches (44.45 mm)
4131-407: The lower-cost system and then upgrade at any time. While Seligman was working on the SuperNOVA, the company received a letter from Ron Gruner stating "I've read about your product, I've read your ads, and I'm going to work for you. And I'm going to be at your offices in a week to talk to you about that." He was hired on the spot. Gruner was put in charge of the low-cost machine while Seligman designed
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#17327724046644212-508: The lower-numbered model has higher performance. Both models were offered in a variety of cases, the 1200 with seven slots, the 1210 with four and the 1220 with fourteen. By this time, the PDP-11 was finally shipping. It offered a much richer instruction set architecture than the deliberately simple one in the Nova. Continuing improvement in IC designs, and especially their price–performance ratio ,
4293-399: The machine ran about half the speed of the original Nova as a result. The first chip in the series was the mN601 , of 1977. This was sold both as a CPU for other users, a complete chipset for those wanting to implement a computer, a complete computer on a single board with 4 kB of RAM, and as a complete low-end model of the Nova. An upgraded version of the design, 1979's mN602 , reduced
4374-458: The midst of a strike in the airline industry and the machine never arrived. They sent a second example, which arrived promptly as the strike had ended by that point, and in May the original one was finally delivered as well. The system was successful from the start, with the 100th being sold after six months, and the 500th after 15 months. Sales accelerated as newer versions were introduced, and by 1975
4455-445: The new " flip-chip " packaging for a modest improvement in density. During the period when the PDP-8 was being developed, the introduction of ASCII and its major update in 1967 led to a new generation of designs with word lengths that were multiples of 8 bits rather than multiples of 6 bits as in most previous designs. This led to mid-range designs working at 16-bit word lengths instead of DEC's current 12- and 18-bit lineups. de Castro
4536-510: The new ICs allowed the ALU to be expanded to full 16-bit width on the same two cards, allowing it to carry out math and logic operations in a single cycle and thereby making the new design four times as fast as the original. In addition, new smaller core memory was used that improved the cycle time from the original's 1,200 ns to 800 ns, offering a further 1 / 3 improvement. Performance could be further improved by replacing
4617-420: The operand was taken from the source register and the result replaced the destination register. For all single-operand opcodes, it was permissible for the source and destination accumulators to be the same, and the operation functioned as expected. Rack unit A rack unit (abbreviated U or RU ) is a unit of measure defined as 1 + 3 ⁄ 4 inches (44.45 mm). It is most frequently used as
4698-447: The pitch of printed circuit boards /cards providing physical compatibility of technological equipment, typically in telecommunications. While a rack unit is defined as 1 + 3 ⁄ 4 inches (44.45 mm), a front panel or filler panel in a rack is not an exact multiple of this height. To allow space between adjacent rack-mounted components, a panel is 1 ⁄ 32 inches (0.03125 in or 0.794 mm) less in height than
4779-399: The right) differs for 19-inch racks and 23-inch racks: 19-inch racks use uneven spacings (as shown to the right) while 23-inch racks use evenly spaced mounting holes. Although it is called a 19-inch rack unit, the actual mounting dimensions of a 19-inch rack unit are 18 5 ⁄ 16 inches (18.3125 in or 465.1 mm) wide, center to center. Rack units are universally the same, but
4860-475: The shift register. One of the most common uses of a shift register is to convert between serial and parallel interfaces. Serial-in serial-out shift registers can be used as simple delay circuits. Several bidirectional shift registers can also be connected in parallel for a hardware implementation of a stack . Shift registers are commonly attached to microcontrollers when more general-purpose input/output pins are required than are available, sometimes over
4941-450: The system cost up to $ 7,995. This core memory board was organized in planar fashion as four groups of four banks, each bank carrying two sets of core in a 64 by 64 matrix; thus there were 64 x 64 = 4096 bits per set, x 2 sets giving 8,192 bits, x 4 banks giving 32,768 bits, x 4 groups giving a total of 131,072 bits, and this divided by the machine word size of 16 bits gave 8,192 words of memory. The core on this 8K word memory board occupied
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#17327724046645022-403: The system to shift from one location to the next. By connecting the last flip-flop back to the first, the data can cycle within the shifters for extended periods, and in this configuration they were used as computer memory , displacing delay-line memory systems in the late 1960s and early 1970s. In most cases, several parallel shift registers would be used to build a larger memory pool known as
5103-606: The terminal display could be accomplished by simply pausing the display output to skip one line of characters. A similar design was used for the Apple I 's terminal. One of the first known examples of a shift register was in the Mark 2 Colossus , a code-breaking machine built in 1944. It was a six-stage device built of vacuum tubes and thyratrons . A shift register was also used in the IAS machine , built by John von Neumann and others at
5184-459: The total IC count needed to implement a complete arithmetic logic unit (ALU), the core mathematical component of a CPU, allowing the expansion from an 8-bit design to 16-bit. This did require the expansion of the CPU from a single 15 by 15 inches (38 cm × 38 cm) printed circuit board to two, but such a design would still be significantly cheaper to produce than the 8/I while still being more powerful and ASCII-based. A third board held
5265-436: The type of thread can vary depending on the rack. Mounting rails can be No. 10-32 tapped ( Unified Thread Standard ), No. 12-24 tapped, metric M6 threaded or universal square holes. Universal square holes are becoming the most common as these allow the insertion of replaceable cage nuts for the type of thread needed. This prevents stripping of the threading on the rails and allows for more flexibility. Whereas there
5346-510: The world." The basic model was not very useful out of the box, and adding 8 kW ( 16 kB ) RAM in the form of core memory typically brought the price up to US$ 7,995 . In contrast, an 8/I with 4 kW ( 6 kB ) was priced at US$ 12,800 . The first sale was to a university in Texas, with the team hand-building an example which shipped out in February. However, this was in
5427-562: The year. Work on the first system took about nine months, and the first sales efforts started that November. They had a bit of luck because the Fall Joint Computer Conference had been delayed until December that year, so they were able to bring a working unit to San Francisco where they ran a version of Spacewar! . DG officially released the Nova in 1969 at a base price of US$ 3,995 (equivalent to $ 33,193 in 2023), advertising it as "the best small computer in
5508-443: Was almost RISC -like in its bit-efficiency; and an instruction that manipulated register data could also perform tests, shifts and even elect to discard the result. Hardware options included an integer multiply and divide unit, a floating-point unit (single and double precision), and memory management . The earliest Nova came with a BASIC interpreter on punched tape . As the product grew, Data General developed many languages for
5589-440: Was already available at the time, and RAM-less systems (i.e. with ROM only) became popular in many industrial settings. The original Nova machines ran at approximately 200 kHz , but its SuperNova was designed to run at up to 3 MHz when used with special semiconductor main memory. The standardized backplane and I/O signals created a simple, efficient I/O design that made interfacing programmed I/O and Data Channel devices to
5670-407: Was central. There was no stack register , but later Eclipse designs would utilize a dedicated hardware memory address for this function. The earliest models of the Nova processed math serially in 4-bit packets, using a single 74181 bitslice ALU . A year after its introduction, this design was improved to include a full 16-bit parallel math unit using four 74181s, this design being referred to as
5751-434: Was convinced that it was possible to improve upon the PDP-8 by building a 16-bit minicomputer CPU on a single 15-inch square board. In 1967, de Castro began a new design effort known as "PDP-X" which included several advanced features. Among these was a single underlying design that could be used to build 8-, 16-, and 32-bit platforms. This progressed to the point of producing several detailed architecture documents. Ken Olsen
5832-421: Was eroding the value of the original simplified instructions. Seligman was put in charge of designing a new machine that would be compatible with the Nova while offering a much richer environment for those who wanted it. This concept shipped as the Data General Eclipse series, which offered the ability to add additional circuitry to tailor the instruction set for scientific or data processing workloads. The Eclipse
5913-404: Was established as a standard by AT&T around 1922 in order to reduce the space required for repeater and termination equipment in a telephone company central office . A typical full-size rack is 42U, which means it holds just over 6 feet (180 cm) of equipment, and a typical "half-height" rack is 18–22U, which is around 3 feet (91 cm) high. The mounting-hole distance (as shown to
5994-483: Was introduced later the same year as the SuperNOVA SC , featuring semiconductor (SC) memory. The much higher performance memory allowed the CPU, which was synchronous with memory, to be further increased in speed to run at a 300 ns cycle time (3.3 MHz). This made it the fastest available minicomputer for many years. Initially the new memory was also very expensive and ran hot, so it was not widely used. As
6075-620: Was later introduced with an extended upwardly compatible instruction set, and the MV-series further extended the Eclipse into a 32-bit architecture to compete with the DEC VAX . The development of the MV-series was documented in Tracy Kidder 's popular 1981 book, The Soul of a New Machine . Data General itself would later evolve into a vendor of Intel processor-based servers and storage arrays, eventually being purchased by EMC . There
6156-407: Was not supportive of this project, feeling it did not offer sufficient advantages over the 12-bit PDP-8 and the 18-bit PDP-9 . It was eventually canceled in the spring of 1968. Cancelation of the PDP-X prompted de Castro to consider leaving DEC to build a system on his own. He was not alone; in late 1967 a group of like-minded engineers formed to consider such a machine. The group included Pat Green,
6237-415: Was one bit longer, since binary addition can only result in an answer that has the same size or is one bit longer. Many computer languages include bitwise operations to "shift right" and "shift left" the data in a register, effectively dividing by two or multiplying by two for each place shifted. Very large serial-in serial-out shift registers (thousands of bits in size) were used in a similar manner to
6318-621: Was successful in competing with the PDP-11 at the higher end of the market. Around the same time, rumors of a new 32-bit machine from DEC began to surface. DG decided they had to have a similar product, and Gruner was put in charge of what became the Fountainhead Project. Given the scope of the project, they agreed that the entire effort should be handled off-site, and Gruner selected a location at Research Triangle Park in North Carolina . This design became very complex and
6399-444: Was that Signetics had introduced the 8260, a 4-bit IC that combined an adder, XNOR and AND, meaning the number of chips needed to implement the basic logic was reduced by about three times. Another was that Intel was aggressively talking up semiconductor-based memories, promising 1024 bits on a single chip and running at much higher speeds than core memory. Seligman's new design took advantage of both of these improvements. To start,
6480-406: Was the Nova 2 , with the first versions shipping in 1973. The Nova 2 was essentially a simplified version of the earlier machines as increasing chip densities allowed the CPU to be reduced in size. While the SuperNOVA used three 15×15" boards to implement the CPU and its memory, the Nova 2 fitted all of this onto a single board. ROM was used to store the boot code, which was then copied into core when
6561-419: Was ultimately canceled years later. While these efforts were underway, work on the Nova line continued. The 840, first offered in 1973, also included a new paged memory system allowing for addresses of up to 17-bits. An index offset the base address into the larger 128 kword memory. Actually installing this much memory required considerable space; the 840 shipped in a large 14-slot case. The next version
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