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51-415: The earliest PDP-8 model, informally known as a "Straight-8", was introduced on 22 March 1965 priced at $ 18,500 (equivalent to about $ 178,900 in 2023). It uses diode–transistor logic packaged on flip chip cards in a machine about the size of a small household refrigerator . It was the first computer to be sold for under $ 20,000, making it the best-selling computer in history at that time. The Straight-8

102-584: A light pen , analog-to-digital converters , digital-to-analog converters , tape drives , and disk drives . To save money, the design uses inexpensive main memory for many purposes that are served by more expensive flip-flop registers in other computers, such as auxiliary counters and subroutine linkage. Basic models use software to do multiplication and division. For faster math, the Extended Arithmetic Element (EAE) provides multiply and divide instructions with an additional register,

153-414: A program counter (PC), and a carry flag called the "link register" (L). Additional registers not visible to the programmer are a memory-buffer register and a memory-address register . To save money, these serve multiple purposes at different points in the operating cycle. For example, the memory buffer register provides arithmetic operands, is part of the instruction register, and stores data to rewrite

204-493: A JMP. The OPR instruction was said to be "microcoded." This did not mean what the word means today (that a lower-level program fetched and interpreted the OPR instruction), but meant that each bit of the instruction word specifies a certain action, and the programmer could achieve several actions in a single instruction cycle by setting multiple bits. In use, a programmer can write several instruction mnemonics alongside one another, and

255-565: A Kaypro 386 (an 80386-based computer) and was written in the C computer language (before the ANSI-C standard was finalized) and assembler by David Beecher of Denver, Colorado. It replaced a failing PDP-8/S computer that operated the fuel handling machine at Reactor #85, the Platteville, Colorado Nuclear Fuel powered Electric Generating Station, Ft. St. Vrain. It was reviewed by Rockwell International and performed flawlessly for 2.5 years during

306-480: A PDP-8 are available on the Internet, as well as open-source hardware re-implementations. The best of these correctly execute DEC's operating systems and diagnostic software. The software simulations often simulate late-model PDP-8s with all possible peripherals. Even these use only a tiny fraction of the capacity of a modern personal computer. One of the first commercial versions of a PDP-8/S virtual machine ran on

357-500: A bank of 12 toggle switches. Typically, these instructions were a bootstrap loader to read a program from the paper tape reader. Program development could then proceed, using paper tape input and output. Paper-tape versions of a number of programming languages became available, including DEC's FOCAL interpreter and a 4K FORTRAN compiler and runtime. Toward the end of the PDP-8 era, operating systems such as OS/8 and COS-310 allowed

408-401: A faster, fully parallel implementation but use much less costly transistor–transistor logic (TTL) MSI logic. Most surviving PDP-8s are from this era. The PDP-8/E is common, and well-regarded because many types of I/O devices were available for it. The last commercial PDP-8 models introduced in 1979 are called "CMOS-8s", based on CMOS microprocessors. They were not priced competitively, and

459-542: A large cabinet. In the later 8/S model, introduced in August 1966, two different logic voltages increased the fan-out of the inexpensive diode–transistor logic . The 8/S also reduced the number of logic gates by using a serial, single-bit-wide data path to do arithmetic. The CPU of the PDP-8/S has only about 519 logic gates . In comparison, small microcontrollers (as of 2008) usually have 15,000 or more. The reductions in

510-477: A memory word, except if indirection is specified, but has the same bit fields. This use of the instruction word divides the 4,096-word memory into 128-word pages ; bit 4 of the instruction selects either the current page or page 0 (addresses 0000–0177 in octal ). Memory in page 0 is at a premium, since variables placed here can be addressed directly from any page. (Moreover, address 0000 is where any interrupt service routine must start, and addresses 0010–0017 have

561-488: A six-bit teleprinter code called the teletypesetting or TTS code was in widespread use by the news wire services, and an early application for the PDP-8 was typesetting using this code. PDP-8 instructions have a three-bit opcode, so there are only eight instructions. The programmer can use many additional instruction mnemonics, which the assembler translates to specific OPR or IOT instructions. The PDP-8 has only three programmer-visible registers : A 12-bit accumulator (AC),

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612-474: A speed of 0.333 MIPS . The 1974 Pocket Reference Card for the PDP-8/E gives a basic instruction time of 1.2 microseconds, or 2.6 microseconds for instructions that reference memory. The PDP-8 was designed in part to handle contemporary telecommunications and text. Six-bit character codes were in widespread use at the time, and the PDP-8's twelve-bit words can efficiently store two such characters. In addition,

663-471: A subroutine produces defects that are difficult to trace to the subroutine in question. As design advances reduced the costs of logic and memory, the programmer's time became relatively more important. Subsequent computer designs emphasized ease of programming, typically using larger and more intuitive instruction sets. Eventually, most machine code was generated by compilers and report generators. The reduced instruction set computer returned full-circle to

714-489: A traditional line mode editor and command-line compiler development system using languages such as PAL-III assembly language, FORTRAN, BASIC , and DIBOL . Fairly modern and advanced real-time operating system (RTOS) and preemptive multitasking multi-user systems were available: a real-time system (RTS-8) was available as were multiuser commercial systems (COS-300 and COS-310) and a dedicated single-user word-processing system (WPS-8). A time-sharing system, TSS-8 ,

765-402: Is also 12 bits, so the PDP-8's basic configuration has a main memory of 4,096 (2) twelve-bit words, or 6  KiB in modern terms. An optional memory-expansion unit can switch banks of memories using an IOT instruction. The memory is magnetic-core memory with a cycle time of 1.5 microseconds (0.667 MHz ), so that a typical two-cycle (Fetch, Execute) memory-reference instruction runs at

816-564: Is named for Richard H. Baker, who described it in his 1956 technical report "Maximum Efficiency Switching Circuits". In 1964, James R. Biard filed a patent for the Schottky transistor . In his patent the Schottky diode prevented the transistor from saturating by minimizing the forward bias on the collector–base transistor junction, thus reducing the minority carrier injection to a negligible amount. The diode could also be integrated on

867-405: Is performed by a transistor (in contrast with resistor–transistor logic (RTL) and transistor–transistor logic (TTL). The DTL circuit shown in the first picture consists of three stages: an input diode logic stage (D1, D2 and R1), an intermediate level shifting stage (R3 and R4), and an output common-emitter amplifier stage (Q1 and R2). If both inputs A and B are high (logic 1; near V+), then

918-400: Is set. More complicated devices, such as disk drives, use these 3 bits in device-specific fashions. Typically, a device decodes the 3 bits to give 8 possible function codes. Many operations are achieved using OPR, including most of the conditionals. OPR does not address a memory location; conditional execution is achieved by conditionally skipping the following instruction, which is typically

969-457: Is the same in all groups is bit 4, CLA. If set, the accumulator is cleared. In most cases, the operations are sequenced so that they can be combined in the most useful ways. For example, combining CLA (CLear Accumulator), CLL (CLear Link), and IAC (Increment ACcumulator) first clears the AC and Link, then increments the accumulator, leaving it set to 1. Adding RAL to the mix (so CLA CLL IAC RAL) causes

1020-401: The core memory , which is erased when read. For input and output, the PDP-8 has a single interrupt shared by all devices, an I/O bus accessed by I/O instructions and a direct memory access (DMA) channel. The programmed I/O bus typically runs low to medium-speed peripherals, such as printers , teletypes , paper tape punches and readers, while DMA is used for cathode-ray tube screens with

1071-450: The 930-series DTμL micrologic family that had a better noise immunity, smaller die, and lower cost. It was the most commercially successful DTL family and copied by other IC manufacturers. The DTL propagation delay is relatively large. When the transistor goes into saturation from all inputs being high, charge is stored in the base region. When it comes out of saturation (one input goes low) this charge has to be removed and will dominate

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1122-518: The DTL gate, R3 is replaced by two level-shifting diodes connected in series. Also the bottom of R4 is connected to ground to provide bias current for the diodes and a discharge path for the transistor base. The resulting integrated circuit runs off a single power supply voltage. In 1962, Signetics introduced the SE100-series family, the first high-volume DTL chips. In 1964, Fairchild released

1173-543: The Digital Equipment Corporation User Society, and often came with full source listings and documentation. The three high-order bits of the 12-bit instruction word (labelled bits 0 through 2) are the operation code. For the six operations that refer to memory, bits 5 through 11 provide a seven-bit address. Bit 4, if set, says to complete the address using the five high-order bits of the program counter (PC) register, meaning that

1224-529: The Multiplier/Quotient (MQ) register. The EAE was an option on the original PDP-8, the 8/I, and the 8/E, but it is an integral part of the Intersil 6100 microprocessor. The PDP-8 is optimized for simplicity of design . Compared to more complex machines, unnecessary features were removed and logic is shared when possible. Instructions use autoincrement, autoclear, and indirect access to increase

1275-655: The PDP-8's emphasis on a simple instruction set and achieving multiple actions in a single instruction cycle, in order to maximize execution speed, although the newer computers have much longer instruction words. The PDP-8 used ideas from several 12-bit predecessors such as the LINC designed by W.A. Clark and C.E. Molnar , who were inspired by Seymour Cray 's CDC 160 minicomputer. The PDP-8 uses 12 bits for its word size and arithmetic (on unsigned integers from 0 to 4095 or signed integers from −2048 to +2047). However, software can do multiple-precision arithmetic . An interpreter

1326-532: The accumulator to be cleared, incremented, then rotated left, leaving it set to 2. In this way, small integer constants were placed in the accumulator with a single instruction. Diode%E2%80%93transistor logic Diode–transistor logic ( DTL ) is a class of digital circuits that is the direct ancestor of transistor–transistor logic . It is called so because the logic gating functions AND and OR are performed by diode logic , while logical inversion (NOT) and amplification (providing signal restoration)

1377-474: The addressed location was within the same 128 words as the instruction. If bit 4 is clear, zeroes are used, so the addressed location is within the first 128 words of memory. Bit 3 specifies indirection; if set, the address obtained as described so far points to a 12-bit value in memory that gives the actual effective address for the instruction; this way, operands can be anywhere in memory at the expense of an additional word. The JMP instruction does not operate on

1428-569: The assembler combines them with OR to devise the actual instruction word. Many I/O devices support "microcoded" IOT instructions. Microcoded actions take place in a well-defined sequence designed to maximize the utility of many combinations. The OPR instructions come in Groups. Bits 3, 8 and 11 identify the Group of an OPR instruction, so it is impossible to combine the microcoded actions from different groups. One action (and corresponding bit) which

1479-455: The core memory. However, the I/O devices need more electronic logic to manage their own word count and transfer address registers. By the time the PDP-8/E was introduced, electronic logic had become less expensive and "one-cycle data break" became more popular. Early PDP-8 systems were shipped with no pre-installed software; each time the PDP-8 was powered up, the user hand-entered instructions using

1530-610: The current page require an extra word. Consequently, much time was spent cleverly conserving one or several words. Programmers deliberately placed code at the end of a page to achieve a free transition to the next page as PC was incremented. The PDP-8 processor defined few of the IOT instructions, but simply provided a framework. Most IOT instructions were defined by the individual I/O devices. Bits 3 through 8 of an IOT instruction select an I/O device. Some of these device addresses are standardized by convention: Instructions for device 0 affect

1581-476: The diodes D1 and D2 are reverse biased. Resistors R1 and R3 will then supply enough current to turn on Q1 (drive Q1 into saturation) and also supply the current needed by R4. There will be a small positive voltage on the base of Q1 (V BE , about 0.3 V for germanium and 0.6 V for silicon). The turned on transistor's collector current will then pull the output Q low (logic 0; V CE(sat) , usually less than 1 volt). If either or both inputs are low, then at least one of

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1632-456: The electronics permitted a much smaller case, about the size of a bread-box. The 8/S was designed by Saul Dinman. The even later PDP-8/E is a larger, more capable computer, but further reengineered for better value. It employs faster transistor–transistor logic , in integrated circuits. The core memory was redesigned. It allows expansion with less expense because it uses the OMNIBUS in place of

1683-522: The end of the PDP-8 era, floppy disks and moving-head cartridge disk drives were popular I/O devices. Modern enthusiasts have created standard PC style IDE hard disk adapters for real and simulated PDP-8 computers. Several types of I/O are supported: A simplified, inexpensive form of DMA called "three-cycle data break" is supported; this requires the assistance of the processor. The "data break" method moves some of common logic needed to implement DMA I/O from each I/O device into one common copy of

1734-517: The input diodes conducts and pulls the voltage at the anodes to a value less than about 2 volts. R3 and R4 then act as a voltage divider that makes Q1's base voltage negative and consequently turns off Q1. Q1's collector current will be essentially zero, so R2 will pull the output voltage Q high (logic 1; near V+). Up until 1952, IBM manufactured transistors by modifying off-the-shelf germanium diodes , after which they had their own alloy-junction transistor manufacturing plant at Poughkeepsie . In

1785-465: The logic within the processor. "Data break" places the processor in charge of maintaining the DMA address and word count registers. In three successive memory cycles, the processor updates the word count, updates the transfer address, and stores or retrieves the actual I/O data word. One-cycle data break effectively triples the DMA transfer rate because only the target data needed to be transferred to and from

1836-494: The mid 1950s, diode logic was used in the IBM 608 which was the first all-transistorized computer in the world. A single card would hold four two-way circuits or three three-way or one eight-way. All input and output signals were compatible. The circuits were capable of reliably switching pulses as narrow as one microsecond. The designers of the 1962 D-17B guidance computer used diode-resistor logic as much as possible, to minimize

1887-463: The number of transistors used. The IBM 1401 (announced in 1959 ) used DTL circuits similar to the circuit shown in the first picture. IBM called the logic "complemented transistor diode logic" (CTDL). CTDL avoided the level shifting stage (R3 and R4) by alternating NPN and PNP based gates operating on different power supply voltages. NPN based circuits used +6V and -6V and the transistor switched at close to -6V, PNP based circuits used 0V and -12V and

1938-487: The offering failed. Intersil sold the integrated circuits commercially through 1982 as the Intersil 6100 family. By virtue of their CMOS technology they had low power requirements and were used in some embedded military systems. The chief engineer who designed the initial version of the PDP-8 was Edson de Castro , who later founded Data General . The PDP-8 combines low cost, simplicity, expandability, and careful engineering for value. The greatest historical significance

1989-613: The operation of the Fuel Handling Machine while it was used to remove fuel from the reactor core and decommission the plant. It included a simulated paper tape loader and front panel. The I/O systems underwent huge changes during the PDP-8 era. Early PDP-8 models use a front panel interface, a paper-tape reader and a teletype printer with an optional paper-tape punch. Over time, I/O systems such as magnetic tape , RS-232 and current loop dumb terminals , punched card readers, and fixed-head disks were added. Toward

2040-420: The processor as a whole. For example, ION (6001) enables interrupt processing, and IOFF (6002) disables it. Bits 9 through 11 of an IOT instruction select the function(s) the device performs. Simple devices (such as the paper tape reader and punch and the console keyboard and printer) use the bits in standard ways: These operations take place in a well-defined order that gives useful results if more than one bit

2091-407: The propagation time. One way to speed up DTL is to add a small "speed-up" capacitor across R3. The capacitor helps to turn off the transistor by removing the stored base charge; the capacitor also helps to turn on the transistor by increasing the initial base drive. Another way to speed up DTL is to avoid saturating the switching transistor. That can be done with a Baker clamp . The Baker clamp

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2142-463: The required mechanics, as opposed to setting out the algorithm. For example, subtracting a number involves computing its two's complement then adding it; writing a conditional jump involves writing a conditional skip around the jump, the skip coding the condition negative to the one desired. Some ambitious programming projects failed to fit in memory or developed design defects that could not be solved. For example, as noted below , inadvertent recursion of

2193-515: The same die, had a compact layout, no minority-carrier charge storage, and was faster than a conventional junction diode. His patent also showed how the Schottky transistor could be used in DTL circuits and improve the switching speed of other saturated logic designs, such as Schottky-TTL, at a low cost. A major advantage over the earlier resistor–transistor logic is increased fan-in . Additionally, to increase fan-out, an additional transistor and diode may be used. IBM System IBM System -

2244-436: The software's speed, reduce memory use, and substitute inexpensive memory for expensive registers. Because of their simplicity, early PDP-8 models were less expensive than most other commercially available computers. However, they used costly production methods often used for prototypes. They used thousands of very small, standardized logic-modules, with gold connectors, integrated by a costly, complex wire-wrapped backplane in

2295-418: The special property of auto-incrementing preceding any indirect reference through them.) The standard assembler places constant values for arithmetic in the current page. Likewise, cross-page jumps and subroutine calls use an indirect address in the current page. It was important to write routines to fit within 128-word pages, or to arrange routines to minimize page transitions, as references and jumps outside

2346-598: The transistor switched at close to 0V. Thus for example a NPN gate driven by a PNP gate would see the threshold voltage of -6V in the middle of the range of 0V to -12V. Similarly for the PNP gate switching at 0V driven by a range of 6V to -6V. The 1401 used germanium transistors and diodes in its basic gates. The 1401 also added an inductor in series with R2. The physical packaging used the IBM Standard Modular System . In an integrated circuit version of

2397-554: The wire-wrapped backplane on earlier models. (A personal account of the development of the PDP-8/E can be read on the Engineering and Technology History Wiki.) The total sales figure for the PDP-8 family has been estimated at over 300,000 machines. The following models were manufactured: The PDP-8 is readily emulated , as its instruction set is much simpler than modern architectures. Enthusiasts have created entire PDP-8s using single FPGA devices. Several software simulations of

2448-400: Was also available. TSS-8 allows multiple users to log into the system via 110-baud terminals, and edit, compile and debug programs. Languages include a special version of BASIC, a FORTRAN subset similar to FORTRAN-1 (no user-written subroutines or functions), an ALGOL subset, FOCAL, and an assembler called PAL-D. A fair amount of user-donated software for the PDP-8 was available from DECUS ,

2499-530: Was available for floating point operations, for example, that uses a 36-bit floating point representation with a two-word (24-bit) significand (mantissa) and one-word exponent. Subject to speed and memory limitations, the PDP-8 can perform calculations similar to more expensive contemporary electronic computers, such as the IBM 1130 and various models of the IBM System/360 , while being easier to interface with external devices. The memory address space

2550-522: Was supplanted in 1966 by the PDP-8/S, which was available in desktop and rack-mount models. Using a one-bit serial arithmetic logic unit (ALU) allowed the PDP-8/S to be smaller and less expensive, although slower than the original PDP-8. A basic 8/S sold for under $ 10,000, the first machine to reach that milestone. Later systems (the PDP-8/I and /L, the PDP-8/E, /F, and /M, and the PDP-8/A) returned to

2601-399: Was that the PDP-8's low cost and high volume made a computer available to many new customers for many new uses. Its continuing significance is as a historical example of value-engineered computer design. The low complexity brought other costs. It made programming cumbersome, as is seen in the examples in this article and from the discussion of "pages" and "fields". Much of one's code performed

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