Misplaced Pages

#891108

33-524: DIMMs (Dual In-line Memory Module) were a 1990s upgrade for SIMMs (Single In-line Memory Modules) as Intel P5 -based Pentium processors began to gain market share. The Pentium had a 64-bit bus width, which would require SIMMs installed in matched pairs in order to populate the data bus. The processor would then access the two SIMMs in parallel. DIMMs were introduced to eliminate this disadvantage. The contacts on SIMMs on both sides are redundant, while DIMMs have separate electrical contacts on each side of

66-410: A PCI-E based "DIMM.2", which has a similar socket to DDR3 DIMMs and is used to put in a module to connect up to two M.2 NVMe solid-state drives. However, it cannot use common DDR type ram and does not have much support other than Asus. Regular DIMMs are generally 133.35 mm in length, while SO-DIMMs are generally 67.6 mm in length. SIMM A SIMM ( single in-line memory module )

99-531: A 64-bit-wide data bus (72 bits wide on DIMMs that support ECC ). The number of physical DRAMs depends on their individual widths. For example, a rank of ×8 (8-bit wide) DRAMs would consist of eight physical chips (nine if ECC is supported), but a rank of ×4 (4-bit wide) DRAMs would consist of 16 physical chips (18, if ECC is supported). Multiple ranks can coexist on a single DIMM. Modern DIMMs can for example feature one rank (single rank), two ranks (dual rank), four ranks (quad rank), or eight ranks (octal rank). There

132-479: A decided nomenclature for each of these speeds for each type. DIMMs based on Single Data Rate (SDR) DRAM have the same bus frequency for data, address and control lines. DIMMs based on Double Data Rate (DDR) DRAM have data but not the strobe at double the rate of the clock; this is achieved by clocking on both the rising and falling edge of the data strobes. Power consumption and voltage gradually became lower with each generation of DDR-based DIMMs. Another influence

165-540: A memory bank. On 386DX , 486 , and full-spec 68020 through 68060 (e.g. Atari TT, Amiga 4000, Mac II) systems (32 bit data bus), either four 30-pin SIMMs or one 72-pin SIMM are required for one memory bank. On Pentium systems (data bus width of 64 bits), two 72-pin SIMMs are required. However, some Pentium systems have support for a "half bank mode", in which the data bus would be shortened to only 32 bits to allow operation of

198-428: A multiple of 9 instead of a multiple of 8 chips. Sometimes memory modules are designed with two or more independent sets of DRAM chips connected to the same address and data buses; each such set is called a rank . Ranks that share the same slot, only one rank may be accessed at any given time; it is specified by activating the corresponding rank's chip select (CS) signal. The other ranks on the module are deactivated for

231-434: A single SIMM. Conversely, some 386 and 486 systems use what is known as "memory interleaving", which requires twice as many SIMMs and effectively doubles the bandwidth. The earliest SIMM sockets were conventional push-type sockets. These were soon replaced by ZIF sockets in which the SIMM was inserted at an angle, then tilted into an upright position. To remove one, the two metal or plastic clips at each end must be pulled to

264-474: A total of 24 address bits, two ranks of chips, and 32-bit data output, the absolute maximum capacity is 2 = 128 MB. Pins 35, 36, 37 and 38 are not connected on non-parity SIMMs. /RAS1 and /RAS3 are only used on two-rank SIMMS: 2, 8, 32, and 128 MB. These lines are only defined on 3.3 V modules. Presence-detect signals are detailed in JEDEC standard. Several CPU cards from Great Valley Products for

297-512: A total of 24 address bits. With an 8-bit data width, this leads to an absolute maximum capacity of 16 MB for both parity and non-parity modules (the additional redundancy-bit chip usually does not contribute to the usable capacity). Pins 26, 28 and 29 are not connected on non-parity SIMMs. Standard sizes: 1 MB, 2 MB, 4 MB, 8 MB, 16 MB, 32 MB, 64 MB, 128 MB (the standard also defines 3.3 V modules with additional address lines and up to 2 GB) With 12 address lines, which can provide

330-400: Is 72 bits wide, so the memory controller only addresses one side at a time (the two-sided module is dual-ranked). The above example applies to ECC memory that stores 72 bits instead of the more common 64. There would also be one extra chip per group of eight, which is not counted. For various technologies, there are certain bus and device clock frequencies that are standardized; there is also

363-623: Is Column Access Strobe (CAS) latency, or CL, which affects memory access speed. This is the delay time between the READ command and the moment data is available. See main article CAS/CL . Several form factors are commonly used in DIMMs. Single Data Rate Synchronous DRAM (SDR SDRAM) DIMMs were primarily manufactured in 1.5 inches (38 mm) and 1.7 inches (43 mm) heights. When 1U rackmount servers started becoming popular, these form factor registered DIMMs had to plug into angled DIMM sockets to fit in

SECTION 10

#1732797645892

396-598: Is a smaller alternative to a DIMM, being roughly half the physical size of a regular DIMM. The first SODIMMs had 72 pins and were introduced by JEDEC in 1997. Before its introduction, many laptops would use proprietary RAM modules which were expensive and hard to find. SO-DIMMs are often used in computers that have limited space, which include laptops , notebook computers , small-footprint personal computers such as those based on Nano-ITX motherboards , high-end upgradable office printers , and networking hardware such as routers and NAS devices. They are usually available with

429-411: Is a type of memory module used in computers from the early 1980s to the early 2000s. It is a printed circuit board on which has random-access memory attached to one or both sides. It differs from a dual in-line memory module (DIMM), the most predominant form of memory module since the late 1990s, in that the contacts on a SIMM are redundant on both sides of the module. SIMMs were standardised under

462-452: Is only a little difference between a dual rank UDIMM and two single-rank UDIMMs in the same memory channel, other than that the DRAMs reside on different PCBs . The electrical connections between the memory controller and the DRAMs are almost identical (with the possible exception of which chip selects go to which ranks). Increasing the number of ranks per DIMM is mainly intended to increase

495-534: Is the voltage key position, which represents 5.0 V, 3.3 V, and RFU DIMM types (order is the same as above). DDR , DDR2 , DDR3 , DDR4 and DDR5 all have different pin counts and/or different notch positions, and none of them are forward compatible or backward compatible . DDR5 SDRAM is the most recent type of DDR memory and has been in use since 2020. A DIMM's capacity and other operational parameters may be identified with serial presence detect (SPD), an additional chip which contains information about

528-540: The Commodore Amiga used special 64-pin SIMMs (32 bits wide, 1, 4 or 16 MB, 60 ns). Dual-ported 64-pin SIMMs were used in Apple Macintosh IIfx computers to allow overlapping read/write cycles (1, 4, 8, 16 MB, 80 ns). 72-pin SIMMs with non-standard presence detect (PD) connections. Double-sided RAM A memory rank is a set of DRAM chips connected to

561-903: The JEDEC JESD-21C standard. Most early PC motherboards ( 8088 -based PCs, XTs , and early ATs ) used socketed DIP chips for DRAM . As computer memory capacities grew, memory modules were used to save motherboard space and ease memory expansion. Instead of plugging in eight or nine single DIP chips, only one additional memory module was needed to increase the memory of the computer. SIMMs were invented in 1983 by James E. Clayton at Wang Laboratories with subsequent patents granted in 1987. Wang Laboratories litigated both patents against multiple companies . The original memory modules were built upon ceramic substrates with 64K Hitachi "flip chip" parts and had pins, i.e. single in-line package (SIP) packaging . SIMMs using pins are usually called SIP or SIPP memory modules to distinguish them from

594-404: The 1.75 inches (44 mm) high box. To alleviate this issue, the next standards of DDR DIMMs were created with a "low profile" (LP) height of around 1.2 inches (30 mm). These fit into vertical DIMM sockets for a 1U platform. With the advent of blade servers , angled slots have once again become common in order to accommodate LP form factor DIMMs in these space-constrained boxes. This led to

627-461: The DRAM chips in bits. High-capacity DIMMs such as 256 GB DIMMs can have up to 19 chips per side. In the case of "×4" registered DIMMs, the data width per side is 36 bits; therefore, the memory controller (which requires 72 bits) needs to address both sides at the same time to read or write the data it needs. In this case, the two-sided module is single-ranked. For "×8" registered DIMMs, each side

660-985: The development of the Very Low Profile (VLP) form factor DIMM with a height of around 0.72 inches (18 mm). The DDR3 JEDEC standard for VLP DIMM height is around 0.740 inches (18.8 mm). These will fit vertically in ATCA systems. Full-height 240-pin DDR2 and DDR3 DIMMs are all specified at a height of around 1.18 inches (30 mm) by standards set by JEDEC. These form factors include 240-pin DIMM, SO-DIMM, Mini-DIMM and Micro-DIMM. Full-height 288-pin DDR4 DIMMs are slightly taller than their DDR3 counterparts at 1.23 inches (31 mm). Similarly, VLP DDR4 DIMMs are also marginally taller than their DDR3 equivalent at nearly 0.74 inches (19 mm). As of Q2 2017, Asus has had

693-415: The duration of the operation by having their corresponding CS signals deactivated. DIMMs are currently being commonly manufactured with up to four ranks per module. Consumer DIMM vendors have recently begun to distinguish between single and dual ranked DIMMs. After a memory word is fetched, the memory is typically inaccessible for an extended period of time while the sense amplifiers are charged for access of

SECTION 20

#1732797645892

726-661: The early 1990s in later models of the IBM PS/2 , and later in systems based on the 486 , Pentium , Pentium Pro , early Pentium II , and contemporary/competing chips of other brands. By the mid-90s, 72-pin SIMMs had replaced 30-pin SIMMs in new-build computers, and were starting to themselves be replaced by DIMMs . Non-IBM PC computers such as UNIX workstations may use proprietary non-standard SIMMs. The Macintosh IIfx uses proprietary non-standard SIMMs with 64 pins. DRAM technologies used in SIMMs include FPM (Fast Page Mode memory, used in all 30-pin and early 72-pin modules), and

759-441: The higher-performance EDO DRAM (used in later 72-pin modules). Due to the differing data bus widths of the memory modules and some processors, sometimes several modules must be installed in identical pairs or in identical groups of four to fill a memory bank. The rule of thumb is a 286 , 386SX , 68000 or low-end 68020 / 68030 (e.g. Atari Falcon, Mac LC) system (using a 16 bit wide data bus) would require two 30-pin SIMMs for

792-448: The memory density per channel. Too many ranks in the channel can cause excessive loading and decrease the speed of the channel. Also some memory controllers have a maximum supported number of ranks. DRAM load on the command/address (CA) bus can be reduced by using registered memory . Predating the term rank (sometimes also called row ) is the use of single-sided and double-sided modules , especially with SIMMs . While most often

825-576: The module type and timing for the memory controller to be configured correctly. The SPD EEPROM connects to the System Management Bus and may also contain thermal sensors ( TS-on-DIMM ). ECC DIMMs are those that have extra data bits which can be used by the system memory controller to detect and correct errors. There are numerous ECC schemes, but perhaps the most common is Single Error Correct, Double Error Detect ( SECDED ) which uses an extra byte per 64-bit word. ECC modules usually carry

858-589: The module. This allowed them to double the SIMMs 32-bit data path into a 64-bit data path. The name "DIMM" was chosen as an acronym for Dual In-line Memory Module symbolizing the split in the contacts of a SIMM into two independent rows. Many enhancements have occurred to the modules in the intervening years, but the word "DIMM" has remained as one of the generic terms for a computer memory module. There are numerous DIMM variants, employing different pin-counts: A SO-DIMM (pronounced "so-dimm" / ˈ s oʊ d ɪ m / , also spelled " SODIMM ") or small outline DIMM ,

891-589: The more common modules using edge connectors. The first variant of SIMMs has 30 pins and provides 8 bits of data (plus a 9th error-detection bit in parity SIMMs). They were used in AT-compatible ( 286 -based, e.g., Wang APC ), 386 -based, 486 -based, Macintosh Plus , Macintosh II , Quadra , Atari STE microcomputers, Wang VS minicomputers and Roland electronic samplers. The second variant of SIMMs has 72 pins and provides 32 bits of data (36 bits in parity and ECC versions). These appeared first in

924-472: The next cell. By interleaving the memory (e.g. cells 0, 4, 8, etc. are stored together in one rank), sequential memory accesses can be performed more rapidly because sense amplifiers have 3 cycles of idle time for recharging, between accesses. DIMMs are often referred to as "single-sided" or " double-sided " to describe whether the DRAM chips are located on one or both sides of the module's printed circuit board (PCB). However, these terms may cause confusion, as

957-404: The physical layout of the chips does not necessarily relate to how they are logically organized or accessed. JEDEC decided that the terms "dual-sided", "double-sided", or "dual-banked" were not correct when applied to registered DIMMs (RDIMMs). Most DIMMs are built using "×4" ("by four") or "×8" ("by eight") memory chips with up to nine chips per side; "×4" and "×8" refer to the data width of

990-454: The pins that encode the capacity and speed of the SIMM, so that compatible equipment can detect the properties of the SIMM. PD SIMMs can be used in equipment which does not support PD; the information is ignored. Standard SIMMs can easily be converted to support PD by fitting jumpers, if the SIMMs have solder pads to do so, or by soldering wires on. Standard sizes: 256 KB, 1 MB, 4 MB, 16 MB. 30-pin SIMMs have 12 address lines, which can provide

1023-400: The same chip select , which are therefore accessed simultaneously. In practice all DRAM chips share all of the other command and control signals, and only the chip select pins for each rank are separate (the data pins are shared across ranks). The term rank was created and defined by JEDEC , the memory industry standards group. On a DDR , DDR2 , or DDR3 memory module , each rank has

DIMM - Misplaced Pages Continue

1056-436: The same size data path and speed ratings of the regular DIMMs though normally with smaller capacities. On the bottom edge of 168-pin DIMMs there are two notches, and the location of each notch determines a particular feature of the module. The first notch is the DRAM key position, which represents RFU (reserved future use), registered , and unbuffered DIMM types (left, middle and right position, respectively). The second notch

1089-418: The side, then the SIMM must be tilted back and pulled out (low-profile sockets reversed this convention somewhat, like SODIMMs - the modules are inserted at a "high" angle, then pushed down to become more flush with the motherboard). The earlier sockets used plastic retainer clips which were found to break, so steel clips replaced them. Some SIMMs support presence detect (PD). Connections are made to some of

#891108