The Sun Fire 15K (codenamed Starcat ) was an enterprise-class server computer from Sun Microsystems based on the SPARC V9 processor architecture. It was announced on September 25, 2001, in New York City, superseding the Sun Enterprise 10000 . General availability was in January 2002; the last to be shipped was in May 2005.
15-496: The Sun Fire 15K supported up to 106 UltraSPARC III processors (up to 1.2 GHz), or 72 UltraSPARC IVs (up to 1.35 GHz & 288 total threads) across 18 system boards ( Uniboards , containing CPU sockets and RAM slots). With the UltraSPARC III, Sun supported up to 17 dual-socket "MaxCPU" processor cards in place of I/O mezzanine cards, a configuration not supported with UltraSPARC IV. Maximum physical RAM per system
30-537: A 0.55 feature size, before it was used to fabricate the UltraSPARC to avoid a repeat of the fabrication problems encountered with SuperSPARC . The UltraSPARC is packaged in a 521-contact plastic ball grid array (PBGA). Visual Instruction Set Visual Instruction Set , or VIS , is a SIMD instruction set extension for SPARC V9 microprocessors developed by Sun Microsystems . There are five versions of VIS: VIS 1, VIS 2, VIS 2+, VIS 3 and VIS 4. VIS 1
45-415: A capacity of 16 KB. The UltraSPARC required a mandatory external secondary cache. The cache is unified, has a capacity of 512 KB to 4 MB and is direct-mapped. It can return data in a single cycle. The external cache is implemented with synchronous SRAMs clocked at the same frequency as the microprocessor, as ratios were not supported. It is accessed via the data bus. It contained 3.8 million transistors. It
60-476: Is 576 GB. A maximum of 72 PCI I/O slots are available. The system can be divided into a maximum of 18 secure independent domains, each of which is a separate machine with its own filesystems, root password and the ability to run different versions of Solaris . The E15k, along with other enterprise Sun servers, has the Dynamic Reconfiguration feature: administrators could dynamically change
75-469: Is a microprocessor developed by Sun Microsystems and fabricated by Texas Instruments , introduced in mid-1995. It is the first microprocessor from Sun to implement the 64-bit SPARC V9 instruction set architecture (ISA). Marc Tremblay was a co-microarchitect. The UltraSPARC is a four-issue superscalar microprocessor that executes instructions in in-order . It includes a nine-stage integer pipeline . The execution units were simplified relative to
90-491: Is claimed as up to 172.8 GB/s aggregate, up to 115.2 GB/s peak, and up to 43.2 GB/s sustained. For overall I/O bandwidth, up to 35.8-GB/s sustained. Up to 64 GB of RAM per board is possible with a maximum of 1.15 TB of RAM for a single domain. Up to 72 hot swappable PCI-X I/O slots; 54 slots are 90 MHz, 18 slots are 33 MHz. It also supports 10/100 BaseT Ethernet , Gigabit Ethernet , Ultra SCSI (LVD and HVD), ATM, FC-AL, HSI and SCI. UltraSPARC The UltraSPARC
105-658: Is connected via SAN to a separate storage array . The Sun Fire 12K (codenamed Starkitty ), was a reduced configuration version of the 15K, introduced in April 2002. It supported a maximum of 52 processors, and was intended to fill a position in Sun's server product line between the 15K and the Sun Fire 6800 . The Sun Fire E25K (codenamed Amazon 25 ; the "E" denoting "Enterprise") was announced in February 2004. Its base cabinet
120-560: Is identical to the 15K, with the only difference between the two systems being the processor boards installed. It reached end-of-life in January, 2009, and was superseded by the Sun SPARC Enterprise M9000 server. The E25K supports up to 72 dual-core UltraSPARC IV+ processors (up to 1.95 GHz). As with UltraSPARC IV-based 15K systems, the "MaxCPU" option was not offered for E25K systems. Overall system bandwidth
135-507: Is very different from comparable extensions on CISC processors, such as MMX , SSE , SSE2 , SSE3 , SSE4 , 3DNow! . Sometimes, programmers must use several VIS instructions to accomplish an operation that can be done with only one MMX or SSE instruction, but it should be kept in mind that fewer instructions do not automatically result in better performance. VIS re-uses existing SPARC V9 64-bit floating point registers to hold multiple 8, 16, or 32-bit integer values. In this respect, VIS
150-605: The SPARC M7 microprocessor. VIS is not an instruction toolkit like Intel 's MMX and SSE. MMX has only 8 registers shared with the FPU stack, while SPARC processors have 32 registers, also aliased to the double-precision (64-bit) floating point registers. As with the SIMD instruction set extensions on other RISC processors, VIS strictly conforms to the main principle of RISC: keep the instruction set concise and efficient. This design
165-653: The SuperSPARC to achieve higher clock frequencies - an example of a simplification is that the ALUs were not cascaded, unlike the SuperSPARC, to avoid restricting clock frequency. The integer register file has 32 64-bit entries. As the SPARC ISA uses register windows , of which the UltraSPARC has eight, the actual number of registers is 144. The register file has seven read and three write ports. The integer register file provides registers to two arithmetic logic units and
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#1732780820457180-435: The assignment of RAM and processors to the different domains to meet changes in business needs. In addition, the 15K contains two system controllers (duplicated for redundancy), which are embedded SPARC computers running Solaris and used to manage the 15K and perform tasks such as booting and shutting down domains and assigning Uniboards to domains. The 15K contains minimal storage in itself (only system controller boot disks); it
195-733: The load/store unit. The two ALUs can both execute arithmetic, logic and shift instructions but only one can execute multiply and divide instructions. The floating-point unit consists of five functional units. One executes floating point adds and subtracts, one multiplies, one divides and square-roots. Two units are for executing SIMD instructions defined by the Visual Instruction Set (VIS). The floating-point register file contains thirty-two 64-bit registers. It has five read ports and three write ports. The UltraSPARC has two levels of cache, primary and secondary. There are two primary caches, one for instructions and one for data. Both have
210-544: Was fabricated in Texas Instruments' EPIC-3 process, a 0.5 μm complementary metal–oxide–semiconductor (CMOS) process with four levels of metal. The UltraSPARC was not fabricated in a BiCMOS process as Texas Instruments claimed it did not scale well to 0.5 μm processes and offered little performance improvement. The process was perfected on TI's MVP digital signal processor (DSP) with some features missing such as three levels of metal instead of four and
225-517: Was introduced in 1994 and was first implemented by Sun in their UltraSPARC microprocessor (1995) and by Fujitsu in their SPARC64 GP microprocessors (2000). VIS 2 was first implemented by the UltraSPARC III . All subsequent UltraSPARC and SPARC64 microprocessors implement the instruction set. VIS 3 was first implemented in the SPARC T4 microprocessor. VIS 4 was first implemented in
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