PCI IDE ISA Xcelerator ( PIIX ), also known as Intel 82371 , is a family of Intel southbridge microchips employed in some Intel chipsets . x86 virtualization implementations often support emulations of various PIIX-based chipsets.
57-401: The PIIX integrated an IDE controller with two 8237 DMA controllers, the 8254 PIT , and two 8259 PICs and a PCI to ISA bus bridge. It was introduced with the 430FX Triton chipset in 1995. The mobile version was introduced with the 430MX mobile Triton chipset. The following variations existed: The PIIX3 introduced a USB 1.0 controller and support for an external I/O APIC . It
114-772: A host adapter interfacing with the rest of the computer system. The remaining connector(s) plug into storage devices, most commonly hard disk drives or optical drives. Each connector has 39 physical pins arranged into two rows (2.54 mm, 1 ⁄ 10 -inch pitch), with a gap or key at pin 20. Earlier connectors may not have that gap, with all 40 pins available. Thus, later cables with the gap filled in are incompatible with earlier connectors, although earlier cables are compatible with later connectors. Round parallel ATA cables (as opposed to ribbon cables) were eventually made available for ' case modders ' for cosmetic reasons, as well as claims of improved computer cooling and were easier to handle; however, only ribbon cables are supported by
171-426: A cable can perform a read or write operation at one time; therefore, a fast device on the same cable as a slow device under heavy use will find it has to wait for the slow device to complete its task first. However, most modern devices will report write operations as complete once the data is stored in their onboard cache memory, before the data is written to the (slow) magnetic storage. This allows commands to be sent to
228-534: A cable, it should be configured as Device 0 . However, some certain era drives have a special setting called Single for this configuration (Western Digital, in particular). Also, depending on the hardware and software available, a Single drive on a cable will often work reliably even though configured as the Device 1 drive (most often seen where an optical drive is the only device on the secondary ATA interface). The words primary and secondary typically refers to
285-449: A drive to a host with an ATA-5 or earlier interface will limit the usable capacity to the maximum of the interface. Some operating systems, including Windows XP pre-SP1, and Windows 2000 pre-SP3, disable LBA48 by default, requiring the user to take extra steps to use the entire capacity of an ATA drive larger than about 137 gigabytes. Older operating systems, such as Windows 98 , do not support 48-bit LBA at all. However, members of
342-497: A maximum drive capacity of two gigabytes. Later, the first formalized ATA specification used a 28-bit addressing mode through LBA28 , allowing for the addressing of 2 ( 268 435 456 ) sectors (blocks) of 512 bytes each, resulting in a maximum capacity of 128 GiB (137 GB ). ATA-6 introduced 48-bit addressing, increasing the limit to 128 PiB (144 PB ). As a consequence, any ATA drive of capacity larger than about 137 GB must be an ATA-6 or later drive. Connecting such
399-532: A northbridge and southbridge was the PCI bus. As of 2023, the main bridging interfaces used are Direct Media Interface ( Intel ) and PCI Express ( AMD ). The southbridge typically implements the slower capabilities of the motherboard in a northbridge-southbridge chipset computer architecture. In systems with Intel chipsets, the southbridge has been named I/O Controller Hub (ICH) and later replaced by Platform Controller Hub chipsets. In older Intel/AMD architectures
456-673: A problem in MS-DOS limited the number of heads to 255. This totals to 8 422 686 720 bytes (8032.5 MiB ), commonly referred to as the 8.4 gigabyte barrier. This is again a limit imposed by x86 BIOSes, and not a limit imposed by the ATA interface. It was eventually determined that these size limitations could be overridden with a small program loaded at startup from a hard drive's boot sector. Some hard drive manufacturers, such as Western Digital, started including these override utilities with large hard drives to help overcome these problems. However, if
513-483: A result, many near-synonyms for ATA/ATAPI and its previous incarnations are still in common informal use, in particular Extended IDE (EIDE) and Ultra ATA (UATA). After the introduction of SATA in 2003, the original ATA was renamed to Parallel ATA, or PATA for short. Parallel ATA cables have a maximum allowable length of 18 in (457 mm). Because of this limit, the technology normally appears as an internal computer storage interface. For many years, ATA provided
570-527: A set of two chips, and instead have a single chip acting as the 'chipset', for example Intel's Z790 chipset, and a central processing unit. Due to the push for system-on-chip (SoC) processors, modern devices increasingly have the northbridge integrated into the CPU die itself; examples are Intel 's Sandy Bridge and AMD 's Fusion processors, both released in 2011. With the Intel 5 Series chipset in 2008,
627-624: A sound card but ultimately as two physical interfaces embedded in a Southbridge chip on a motherboard. Called the "primary" and "secondary" ATA interfaces, they were assigned to base addresses 0x1F0 and 0x170 on ISA bus systems. They were replaced by SATA interfaces. The first version of what is now called the ATA/ATAPI interface was developed by Western Digital under the name Integrated Drive Electronics (IDE). Together with Compaq (the initial customer), they worked with various disk drive manufacturers to develop and ship early products with
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#1732798619103684-406: A way for the host to determine whether the media is present, and these were not provided in the ATA protocol. ATAPI is a protocol allowing the ATA interface to carry SCSI commands and responses; therefore, all ATAPI devices are actually "speaking SCSI" other than at the electrical interface. The SCSI commands and responses are embedded in "packets" (hence "ATA Packet Interface") for transmission on
741-464: Is a standard interface designed for IBM PC -compatible computers. It was first developed by Western Digital and Compaq in 1986 for compatible hard drives and CD or DVD drives. The connection is used for storage devices such as hard disk drives , floppy disk drives , optical disc drives , and tape drives in computers . The standard is maintained by the X3/ INCITS committee. It uses
798-510: Is a designation that has been primarily used by Western Digital for different speed enhancements to the ATA/ATAPI standards. For example, in 2000 Western Digital published a document describing "Ultra ATA/100", which brought performance improvements for the then-current ATA/ATAPI-5 standard by improving maximum speed of the Parallel ATA interface from 66 to 100 MB/s. Most of Western Digital's changes, along with others, were included in
855-609: Is defined in the MMC SCSI command set. ATAPI was adopted as part of ATA in INCITS 317-1998, AT Attachment with Packet Interface Extension (ATA/ATAPI-4) . The ATA/ATAPI-4 standard also introduced several " Ultra DMA " transfer modes. These initially supported speeds from 16 to 33 MB/s. In later versions, faster Ultra DMA modes were added, requiring new 80-wire cables to reduce crosstalk. The latest versions of Parallel ATA support up to 133 MB/s. Ultra ATA, abbreviated UATA,
912-500: The Zip drive and SuperDisk drive . Some early ATAPI devices were simply SCSI devices with an ATA/ATAPI to SCSI protocol converter added on. The SCSI commands and responses used by each class of ATAPI device (CD-ROM, tape, etc.) are described in other documents or specifications specific to those device classes and are not within ATA/ATAPI or the T13 committee's purview. One commonly used set
969-513: The southbridge is one of the two chips in the core logic chipset , handling many of a computer's input/output functions. The other component of the chipset is the northbridge , which generally handles high speed onboard communications. A southbridge chipset handles functions such as USB, audio, the system firmware, the lower speed PCI/PCIe buses, the IOAPIC interrupt controller, the SATA storage,
1026-434: The ATA cable. This allows any device class for which a SCSI command set has been defined to be interfaced via ATA/ATAPI. ATAPI devices are also "speaking ATA", as the ATA physical interface and protocol are still being used to send the packets. On the other hand, ATA hard drives and solid state drives do not use ATAPI. ATAPI devices include CD-ROM and DVD-ROM drives, tape drives , and large-capacity floppy drives such as
1083-448: The ATA specifications. A 44-pin variant PATA connector is used for 2.5 inch drives inside laptops. The pins are closer together (2.0 mm pitch) and the connector is physically smaller than the 40-pin connector. The extra pins carry power. ATA's cables have had 40 conductors for most of its history (44 conductors for the smaller form-factor version used for 2.5" drives—the extra four for power), but an 80-conductor version appeared with
1140-760: The ATA/ATAPI-6 standard (2002). Initially, the size of an ATA drive was stored in the system x86 BIOS using a type number (1 through 45) that predefined the C/H/S parameters and also often the landing zone, in which the drive heads are parked while not in use. Later, a "user definable" format called C/H/S or cylinders, heads, sectors was made available. These numbers were important for the earlier ST-506 interface, but were generally meaningless for ATA—the CHS parameters for later ATA large drives often specified impossibly high numbers of heads or sectors that did not actually define
1197-537: The PCH, which is directly connected to the CPU via the Direct Media Interface (DMI). Intel low-power processors (Haswell-U and onward) and ultra low-power processors (Haswell-Y and onward) also integrate an on-package PCH. Based on its Chiplet design, AMD Ryzen processors also integrated some southbridge functions, such as some USB and SATA / NVMe interfaces. The name is derived from representing
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#17327986191031254-632: The architecture in the fashion of a map and was first described as such with the introduction of the PCI Local Bus Architecture in 1991. At Intel, the authors of the PCI specification viewed the PCI local bus as being at the very centre of the PC platform architecture (i.e., at the Equator ). The northbridge extends to the north of the PCI bus backbone in support of CPU, memory/ cache , and other performance-critical capabilities. Likewise
1311-497: The bridge was especially simple in case of an ATA connector being located on an ISA interface card. The integrated controller presented the drive to the host computer as an array of 512-byte blocks with a relatively simple command interface. This relieved the mainboard and interface cards in the host computer of the chores of stepping the disk head arm, moving the head arm in and out, and so on, as had to be done with earlier ST-506 and ESDI hard drives. All of these low-level details of
1368-550: The cable. Cable select is controlled by pin 28. The host adapter grounds this pin; if a device sees that the pin is grounded, it becomes the Device 0 (master) device; if it sees that pin 28 is open, the device becomes the Device 1 (slave) device. This setting is usually chosen by a jumper setting on the drive called "cable select", usually marked CS , which is separate from the Device 0/1 setting. If two drives are configured as Device 0 and Device 1 manually, this configuration does not need to correspond to their position on
1425-409: The cable. Pin 28 is only used to let the drives know their position on the cable; it is not used by the host when communicating with the drives. In other words, the manual master/slave setting using jumpers on the drives takes precedence and allows them to be freely placed on either connector of the ribbon cable. With the 40-conductor cable, it was very common to implement cable select by simply cutting
1482-469: The computer was booted in some other manner without loading the special utility, the invalid BIOS settings would be used and the drive could either be inaccessible or appear to the operating system to be damaged. Later, an extension to the x86 BIOS disk services called the " Enhanced Disk Drive " (EDD) was made available, which makes it possible to address drives as large as 2 sectors. The first drive interface used 22-bit addressing mode which resulted in
1539-413: The computer's BIOS and/or operating system . In most personal computers the drives are often designated as "C:" for the Device 0 and "D:" for the Device 1 referring to one active primary partitions on each. The mode that a device must use is often set by a jumper setting on the device itself, which must be manually set to Device 0 ( Master ) or Device 1 ( Slave ). If there is a single device on
1596-402: The connection cable to the drive. On an IBM PC compatible, CP/M machine, or similar, this was typically a card installed on a motherboard . The interface cards used to connect a parallel ATA drive to, for example, an ISA Slot , are not drive controllers: they are merely bridges between the host bus and the ATA interface . Since the original ATA interface is essentially just a 16-bit ISA bus ,
1653-488: The era have a SATA hard disk and an optical drive connected to PATA. As of 2007, some PC chipsets , for example the Intel ICH10, had removed support for PATA. Motherboard vendors still wishing to offer Parallel ATA with those chipsets must include an additional interface chip. In more recent computers, the Parallel ATA interface is rarely used even if present, as four or more Serial ATA connectors are usually provided on
1710-577: The goal of remaining software compatible with the existing IBM PC hard drive interface. The first such drives appeared internally in Compaq PCs in 1986 and were first separately offered by Conner Peripherals as the CP342 in June 1987. The term Integrated Drive Electronics refers to the drive controller being integrated into the drive, as opposed to a separate controller situated at the other side of
1767-476: The hard drive in question is also expected to provide good throughput for other tasks at the same time, it probably should not be on the same cable as the optical drive. A drive mode called cable select was described as optional in ATA-1 and has come into fairly widespread use with ATA-5 and later. A drive set to "cable select" automatically configures itself as Device 0 or Device 1 , according to its position on
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1824-453: The historical PATA storage, the NVMe storage, and low speed buses such as ISA , LPC , SPI , and/or eSPI . Different combinations of southbridge and northbridge chips are possible, but these two kinds of chips are designed to work together. There is no industry-wide standard for interoperability between different core logic chipset designs. In the 1990s and early 2000s, the interface between
1881-414: The internal physical layout of the drive at all. From the start, and up to ATA-2, every user had to specify explicitly how large every attached drive was. From ATA-2 on, an "identify drive" command was implemented that can be sent and which will return all drive parameters. Owing to a lack of foresight by motherboard manufacturers, the system BIOS was often hobbled by artificial C/H/S size limitations due to
1938-570: The introduction of the UDMA/66 mode. All of the additional conductors in the new cable are grounds , interleaved with the signal conductors to reduce the effects of capacitive coupling between neighboring signal conductors, reducing crosstalk . Capacitive coupling is more of a problem at higher transfer rates, and this change was necessary to enable the 66 megabytes per second (MB/s) transfer rate of UDMA4 to work reliably. The faster UDMA5 and UDMA6 modes also require 80-conductor cables. Though
1995-548: The manufacturer assuming certain values would never exceed a particular numerical maximum. The first of these BIOS limits occurred when ATA drives reached sizes in excess of 504 MiB , because some motherboard BIOSes would not allow C/H/S values above 1024 cylinders, 16 heads, and 63 sectors. Multiplied by 512 bytes per sector, this totals 528 482 304 bytes which, divided by 1 048 576 bytes per MiB , equals 504 MiB (528 MB ). The second of these BIOS limitations occurred at 1024 cylinders , 256 heads , and 63 sectors , and
2052-442: The mechanical operation of the drive were now handled by the controller on the drive itself. This also eliminated the need to design a single controller that could handle many different types of drives, since the controller could be unique for the drive. The host need only to ask for a particular sector, or block, to be read or written, and either accept the data from the drive or send the data to it. The interface used by these drives
2109-463: The most common and the least expensive interface for this application. It has largely been replaced by SATA in newer systems. The standard was originally conceived as the "AT Bus Attachment", officially called "AT Attachment" and abbreviated "ATA" because its primary feature was a direct connection to the 16-bit ISA bus introduced with the IBM PC/AT . The original ATA specifications published by
2166-551: The motherboard and SATA devices of all types are common. With Western Digital 's withdrawal from the PATA market, hard disk drives with the PATA interface were no longer in production after December 2013 for other than specialty applications. Parallel ATA cables transfer data 16 bits at a time. The traditional cable uses 40-pin female insulation displacement connectors (IDC) attached to a 40- or 80-conductor ribbon cable . Each cable has two or three connectors, one of which plugs into
2223-753: The number of conductors doubled, the number of connector pins and the pinout remain the same as 40-conductor cables, and the external appearance of the connectors is identical. Internally, the connectors are different; the connectors for the 80-conductor cable connect a larger number of ground conductors to the ground pins, while the connectors for the 40-conductor cable connect ground conductors to ground pins one-to-one. 80-conductor cables usually come with three differently colored connectors (blue, black, and gray for controller, master drive, and slave drive respectively) as opposed to uniformly colored 40-conductor cable's connectors (commonly all gray). The gray connector on 80-conductor cables has pin 28 CSEL not connected, making it
2280-408: The other device on the cable, reducing the impact of the "one operation at a time" limit. The impact of this on a system's performance depends on the application. For example, when copying data from an optical drive to a hard drive (such as during software installation), this effect probably will not matter. Such jobs are necessarily limited by the speed of the optical drive no matter where it is. But if
2337-607: The pin 28 wire between the two device connectors; putting the slave Device 1 device at the end of the cable, and the master Device 0 on the middle connector. This arrangement eventually was standardized in later versions. However, it had one drawback: if there is just one master device on a 2-drive cable, using the middle connector, this results in an unused stub of cable, which is undesirable for physical convenience and electrical reasons. The stub causes signal reflections , particularly at higher transfer rates. Southbridge (computing) On older personal computer motherboards ,
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2394-416: The primary storage device interface for PCs soon after its introduction. In some systems, a third and fourth motherboard interface was provided, allowing up to eight ATA devices to be attached to the motherboard. Often, these additional connectors were implemented by inexpensive RAID controllers. Soon after the introduction of Serial ATA (SATA) in 2003, use of Parallel ATA declined. Some PCs and laptops of
2451-473: The same cable. For all modern ATA host adapters, this is not true, as modern ATA host adapters support independent device timing . This allows each device on the cable to transfer data at its own best speed. Even with earlier adapters without independent timing, this effect applies only to the data transfer phase of a read or write operation. This is caused by the omission of both overlapped and queued feature sets from most parallel ATA products. Only one device on
2508-489: The same time that the ATA-1 standard was adopted, Western Digital introduced drives under a newer name, Enhanced IDE (EIDE). These included most of the features of the forthcoming ATA-2 specification and several additional enhancements. Other manufacturers introduced their own variations of ATA-1 such as "Fast ATA" and "Fast ATA-2". The new version of the ANSI standard, AT Attachment Interface with Extensions ATA-2 (X3.279-1996),
2565-414: The slave position for drives configured cable select. If two devices are attached to a single cable, one must be designated as Device 0 (in the past, commonly designated master ) and the other as Device 1 (in the past, commonly designated as slave ). This distinction is necessary to allow both drives to share the cable without conflict. The Device 0 drive is the drive that usually appears "first" to
2622-566: The southbridge became redundant and was replaced by the Platform Controller Hub (PCH) architecture introduced. AMD did the same with the release of their first APUs in 2011, naming the PCH the fusion controller hub (FCH), which was only used on AMD's APUs until 2017 when it began to be used on AMD's Zen architecture while dropping the FCH name. On Intel platforms, all southbridge features and remaining I/O functions are managed by
2679-490: The southbridge extends to the south of the PCI bus backbone and bridges to less performance-critical I/O capabilities such as the disk interface, audio, etc. The CPU is located at the top of the map at due north. The CPU is connected to the chipset via a fast bridge (the northbridge) located north of other system devices as drawn. The northbridge is connected to the rest of the chipset via a slow bridge (the southbridge) located south of other system devices as drawn. Although
2736-537: The southbridge is usually linked to the northbridge, which in turn connected to the CPU. Circa 2004 and onward Intel architectures started to link southbridge directly to the CPU (e.g. via Direct Media Interface ). Through the use of controller-integrated channel circuitry, the northbridge (or CPU itself) can directly link signals from the I/O units to the CPU for data control and access. As of 2024, most personal computer devices based on Intel or AMD architectures no longer use
2793-480: The standards committees use the name "AT Attachment". The "AT" in the IBM PC/AT referred to "Advanced Technology" so ATA has also been referred to as "Advanced Technology Attachment". When a newer Serial ATA (SATA) was introduced in 2003, the original ATA was renamed to Parallel ATA, or PATA for short. Physical ATA interfaces became a standard component in all PCs, initially on host bus adapters, sometimes on
2850-485: The third-party group MSFN have modified the Windows 98 disk drivers to add unofficial support for 48-bit LBA to Windows 95 OSR2 , Windows 98 , Windows 98 SE and Windows ME . Some 16-bit and 32-bit operating systems supporting LBA48 may still not support disks larger than 2 TiB due to using 32-bit arithmetic only; a limitation also applying to many boot sectors . Parallel ATA (then simply called ATA or IDE) became
2907-402: The two IDE cables, which can have two drives each (primary master, primary slave, secondary master, secondary slave). There are many debates about how much a slow device can impact the performance of a faster device on the same cable. On early ATA host adapters, both devices' data transfers can be constrained to the speed of the slower device, if two devices of different speed capabilities are on
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#17327986191032964-425: The underlying AT Attachment (ATA) and AT Attachment Packet Interface ( ATAPI ) standards. The Parallel ATA standard is the result of a long history of incremental technical development, which began with the original AT Attachment interface, developed for use in early PC AT equipment. The ATA interface itself evolved in several stages from Western Digital 's original Integrated Drive Electronics (IDE) interface. As
3021-432: Was approved in 1996. It included most of the features of the manufacturer-specific variants. ATA-2 also was the first to note that devices other than hard drives could be attached to the interface: 3.1.7 Device: Device is a storage peripheral. Traditionally, a device on the ATA interface has been a hard disk drive, but any form of storage device may be placed on the ATA interface provided it adheres to this standard. ATA
3078-477: Was originally designed for, and worked only with, hard disk drives and devices that could emulate them. The introduction of ATAPI (ATA Packet Interface) by a group called the Small Form Factor committee (SFF) allowed ATA to be used for a variety of other devices that require functions beyond those necessary for hard disk drives. For example, any removable media device needs a "media eject" command, and
3135-511: Was standardized in 1994 as ANSI standard X3.221-1994, AT Attachment Interface for Disk Drives . After later versions of the standard were developed, this became known as "ATA-1". A short-lived, seldom-used implementation of ATA was created for the IBM XT and similar machines that used the 8-bit version of the ISA bus. It has been referred to as "XT-IDE" , "XTA" or "XT Attachment". In 1994, about
3192-564: Was used in 440BX and 440ZX-M chipsets. The following variations existed: This seems to be a reference to the Itanium 460GX I/O and Firmware Bridge (IFB) chipset component which has been referred to as 82372FB (PIIX5), 82468FB, and finally FW82468GX (IFB). This computer hardware article is a stub . You can help Misplaced Pages by expanding it . Advanced Technology Attachment Parallel ATA ( PATA ), originally AT Attachment , also known as Integrated Drive Electronics ( IDE ),
3249-539: Was used with the 430HX and 430VX Triton II and 440FX northbridges . The following variations existed: The PIIX4 introduced ACPI support, an improved IDE controller with Ultra DMA/33 support, and an integrated MC146818 style RTC and CMOS controller. It was used with the 430TX and the 440LX Balboa northbridges . The PIIX4E updated the ACPI support. It was mainly used in 440BX and 440GX chipsets but 440EX, 440ZX, and 450NX chipsets also employed it. The mobile version
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