The Intel QuickPath Interconnect ( QPI ) is a point-to-point processor interconnect developed by Intel which replaced the front-side bus (FSB) in Xeon , Itanium , and certain desktop platforms starting in 2008. It increased the scalability and available bandwidth. Prior to the name's announcement, Intel referred to it as Common System Interface ( CSI ). Earlier incarnations were known as Yet Another Protocol (YAP) and YAP+.
19-573: QPI 1.1 is a significantly revamped version introduced with Sandy Bridge-EP ( Romley platform). QPI was replaced by Intel Ultra Path Interconnect (UPI) in Skylake -SP Xeon processors based on LGA 3647 socket. Although sometimes called a "bus", QPI is a point-to-point interconnect. It was designed to compete with HyperTransport that had been used by Advanced Micro Devices (AMD) since around 2003. Intel developed QPI at its Massachusetts Microprocessor Design Center (MMDC) by members of what had been
38-535: A clock rate of 2.4 GHz, 2.93 GHz, 3.2 GHz, 3.6 GHz, 4.0 GHz or 4.8 GHz (3.6 GHz and 4.0 GHz frequencies were introduced with the Sandy Bridge-E/EP platform and 4.8 GHz with the Haswell-E/EP platform). The clock rate for a particular link depends on the capabilities of the components at each end of the link and the signal characteristics of the signal path on
57-489: A separate clock pair in each direction, for a total of 42 signals. Each signal is a differential pair , so the total number of pins is 84. The 20 data lanes are divided onto four "quadrants" of 5 lanes each. The basic unit of transfer is the 80-bit flit , which has 8 bits for error detection, 8 bits for "link-layer header", and 64 bits for data. One 80-bit flit is transferred in two clock cycles (four 20-bit transfers, two per clock tick.) QPI bandwidths are advertised by computing
76-532: Is computed as follows: QPI is specified as a five-layer architecture , with separate physical, link, routing, transport, and protocol layers. In devices intended only for point-to-point QPI use with no forwarding, such as the Core i7-9xx and Xeon DP processors, the transport layer is not present and the routing layer is minimal. Sandy Bridge-EP Intel Sandy Bridge-based Xeon microprocessors (often referred to as Sandy Bridge-E ) are microprocessors based on
95-539: Is the codename for Intel 's first-generation Core i5 , i3 and Pentium dual-core desktop processors. It is closely related to the mobile Arrandale processor; both use dual-core dies based on the 32 nm Westmere microarchitecture and have integrated Graphics, PCI Express and DMI links built-in. Clarkdale is the successor of the Wolfdale used in desktop Intel Core 2 , Celeron and Pentium Dual-Core processors. Unlike its predecessor, Clarkdale already contains
114-798: The Alpha Development Group, which Intel had acquired from Compaq and HP and in turn originally came from Digital Equipment Corporation (DEC). Its development had been reported as early as 2004. Intel first delivered it for desktop processors in November 2008 on the Intel Core i7-9xx and X58 chipset . It was released in Xeon processors code-named Nehalem in March 2009 and Itanium processors in February 2010 (code named Tukwila). It
133-1425: The Intel 's 32 nm Sandy Bridge architecture for servers, workstations, and high-end desktops. It succeeds the six-core Gulftown /Westmere-EP processor which used the older LGA 1366 package, and uses LGA 2011 , LGA 1356 and LGA 1155 socket depending on the package. There are five different families of Xeon processors that were based on Sandy Bridge architecture: IGPU is absent on most of these processors unless noted otherwise. All models support: MMX , SSE , SSE2 , SSE3 , SSSE3 , SSE4.1 , SSE4.2 , AVX , Enhanced Intel SpeedStep Technology (EIST), Intel 64 , XD bit (an NX bit implementation), TXT , Intel VT-x , Intel EPT , Intel VT-d , Intel VT-c , Intel x8 SDDC , Hyper-threading (except E5-1603, E5-1607, E5-2603, E5-2609 and E5-4617), Turbo Boost (except E5-1603, E5-1607, E5-2603, E5-2609, E5-4603 and E5-4607), AES-NI , Smart Cache. (threads) memory date (USD) Quad Socket E5 DMI 2.0 40× PCIe 3.0 DDR3-1600 (threads) memory date (USD) Dual Socket E5 ( DMI 2.0 40× PCIe 3.0) (threads) memory date (USD) 40× PCIe 2.0 Extreme Edition (threads) memory date (USD) Dual Socket ( DMI 2.0 24× PCI-E 3.0) 24× PCI-E 3.0 (threads) memory date (USD) E3 (threads) (USD) 20× PCIe 2.0 Clarkdale (microprocessor) Clarkdale
152-455: The Lynnfield / Clarksfield and successor families) do not expose QPI externally, because these processors are not intended to participate in multi-socket systems. However, QPI is used internally on these chips to communicate with the " uncore ", which is part of the chip containing memory controllers, CPU-side PCI Express and GPU, if present; the uncore may or may not be on the same die as
171-449: The (former) front-side bus interface via the processor socket. Although the core–uncore QPI link is not present in desktop and mobile Sandy Bridge processors (as it was on Clarkdale, for example), the internal ring interconnect between on-die cores is also based on the principles behind QPI, at least as far as cache coherency is concerned. Being a synchronous circuit the QPI operates at
190-525: The CPU core, for instance it is on a separate die in the Westmere -based Clarkdale / Arrandale . In post-2009 single-socket chips starting with Lynnfield, Clarksfield, Clarkdale and Arrandale, the traditional northbridge functions are integrated into these processors, which therefore communicate externally via the slower DMI and PCI Express interfaces. Thus, there is no need to incur the expense of exposing
209-504: The Core i3, which also does not support Turbo Boost and AES new instructions. In addition, the Pentium and Celeron versions do not have SMT , and they can only use a reduced amount of third-level cache . The Xeon L340x line has a lower clock frequency and thermal design power, and supports unbuffered ECC memory in addition to the features of the Core i5-6xx, but has support for the integrated graphics disabled. Importantly, although
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#1732791737811228-584: The architecture, separate QPI link pairs connect one or more processors and one or more IO hubs or routing hubs in a network on the motherboard, allowing all of the components to access other components via the network. As with HyperTransport, the QuickPath Architecture assumes that the processors will have integrated memory controllers , and enables a non-uniform memory access (NUMA) architecture. Each QPI comprises two 20-lane point-to-point data links, one in each direction ( full duplex ), with
247-543: The clock to a data signal if the clock fails. The initial Nehalem implementation used a full four-quadrant interface to achieve 25.6 GB/s (6.4GT/s × 1 byte × 4), which provides exactly double the theoretical bandwidth of Intel's 1600 MHz FSB used in the X48 chipset. Although some high-end Core i7 processors expose QPI, other "mainstream" Nehalem desktop and mobile processors intended for single-socket boards (e.g. LGA 1156 Core i3, Core i5, and other Core i7 processors from
266-557: The major north bridge components, such as memory controller, PCI Express for external graphics, integrated graphics and the DMI connector, making it possible to build more compact systems without a separate north bridge or discrete graphics like Lynnfield . The Clarkdale processor package contains two dies: the 32 nm processor die with the I/O connections, and the 45 nm graphics and integrated memory controller die. Physical separation of
285-467: The printed circuit board. The non-extreme Core i7 9xx processors are restricted to a 2.4 GHz frequency at stock reference clocks. Bit transfers occur on both the rising and the falling edges of the clock, so the transfer rate is double the clock rate. Intel describes the data throughput (in GB/s) by counting only the 64-bit data payload in each 80-bit flit. However, Intel then doubles the result because
304-450: The processor die and memory controller die resulted in increased memory latency. The CPUID for Clarkdale is family 6, model 37 (2065x). The mobile equivalent of Clarkdale is Arrandale . Clarkdale processors are sold under the Intel Core , Pentium and Celeron brand names, with varying feature sets. The Core i5 versions generally have all features enabled, with the Core i5-661 and Core i5-655K models lacking Intel VT-d and TXT like
323-448: The transfer of 64 bits (8 bytes) of data every two clock cycles in each direction. Although the initial implementations use single four-quadrant links, the QPI specification permits other implementations. Each quadrant can be used independently. On high-reliability servers, a QPI link can operate in a degraded mode. If one or more of the 20+1 signals fails, the interface will operate using 10+1 or even 5+1 remaining signals, even reassigning
342-406: The unidirectional send and receive link pair can be simultaneously active. Thus, Intel describes a 20-lane QPI link pair (send and receive) with a 3.2 GHz clock as having a data rate of 25.6 GB/s. A clock rate of 2.4 GHz yields a data rate of 19.2 GB/s. More generally, by this definition a two-link 20-lane QPI transfers eight bytes per clock cycle, four in each direction. The rate
361-713: Was supplanted by the Intel Ultra Path Interconnect starting in 2017 on the Xeon Skylake-SP platforms. The QPI is an element of a system architecture that Intel calls the QuickPath architecture that implements what Intel calls QuickPath technology . In its simplest form on a single-processor motherboard, a single QPI is used to connect the processor to the IO Hub (e.g., to connect an Intel Core i7 to an X58 ). In more complex instances of
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