Sun Microsystems ' UltraSPARC T2 microprocessor is a multithreading , multi-core CPU . It is a member of the SPARC family, and the successor to the UltraSPARC T1 . The chip is sometimes referred to by its codename, Niagara 2 . Sun started selling servers with the T2 processor in October 2007.
116-511: The T2 is a commodity derivative of the UltraSPARC series of microprocessors, targeting Internet workloads in computers, storage and networking devices. The processor, manufactured in 65 nm , is available with eight CPU cores, and each core is able to handle eight threads concurrently. Thus the processor is capable of processing up to 64 concurrent threads. Other new features include: There are 8 stages for integer operations, instead of 6 in
232-606: A Harvard memory model , where the instruction stream and the data stream are conceptually separated; this means that modifying the memory where code is held might not have any effect on the instructions executed by the processor (because the CPU has a separate instruction and data cache ), at least until a special synchronization instruction is issued; CISC processors that have separate instruction and data caches generally keep them synchronized automatically, for backwards compatibility with older processors. Many early RISC designs also shared
348-478: A register–register architecture ); except for the load/store instructions used to access memory , all instructions operate on the registers, in accordance with the RISC design principles. A SPARC processor includes an integer unit (IU) that performs integer load, store, and arithmetic operations. It may include a floating-point unit (FPU) that performs floating-point operations and, for SPARC V8, may include
464-750: A 24-bit high-speed processor to use as the basis for a digital telephone switch . To reach their goal of switching 1 million calls per hour (300 per second) they calculated that the CPU required performance on the order of 12 million instructions per second (MIPS), compared to their fastest mainframe machine of the time, the 370/168 , which performed at 3.5 MIPS. The design was based on a study of IBM's extensive collection of statistics gathered from their customers. This demonstrated that code in high-performance settings made extensive use of processor registers , and that they often ran out of them. This suggested that additional registers would improve performance. Additionally, they noticed that compilers generally ignored
580-408: A 5-bit number, for 15 bits. If one of these registers is replaced by an immediate, there is still lots of room to encode the two remaining registers and the opcode. Common instructions found in multi-word systems, like INC and DEC , which reduce the number of words that have to be read before performing the instruction, are unnecessary in RISC as they can be accomplished with a single register and
696-411: A 64-bit result, SDIVX , which divides a 64-bit signed dividend by a 64-bit signed divisor and produces a 64-bit signed quotient, and UDIVX , which divides a 64-bit unsigned dividend by a 64-bit unsigned divisor and produces a 64-bit signed quotient; none of those instructions use the Y register. Conditional branches test condition codes in a status register , as seen in many instruction sets such
812-524: A barebones core sufficient for a small embedded processor to supercomputer and cloud computing use with standard and chip designer–defined extensions and coprocessors. It has been tested in silicon design with the ROCKET SoC , which is also available as an open-source processor generator in the CHISEL language. In the early 1980s, significant uncertainties surrounded the RISC concept. One concern involved
928-400: A better balancing of pipeline stages than before, making RISC pipelines significantly more efficient and allowing higher clock frequencies . Yet another impetus of both RISC and other designs came from practical measurements on real-world programs. Andrew Tanenbaum summed up many of these, demonstrating that processors often had oversized immediates. For instance, he showed that 98% of all
1044-415: A co-processor (CP) that performs co-processor-specific operations; the architecture does not specify what functions a co-processor would perform, other than load and store operations. The SPARC architecture has an overlapping register window scheme. At any instant, 32 general-purpose registers are visible. A Current Window Pointer ( CWP ) variable in the hardware points to the current set. The total size of
1160-452: A different opcode. In contrast, a 32-bit machine has ample room to encode an immediate value, and doing so avoids the need to do a second memory read to pick up the value. This is why many RISC processors allow a 12- or 13-bit constant to be encoded directly into the instruction word. Assuming a 13-bit constant area, as is the case in the MIPS and RISC designs, another 19 bits are available for
1276-591: A new specification, Oracle SPARC Architecture 2011 , which besides the overall update of the reference, adds the VIS 3 instruction set extensions and hyperprivileged mode to the 2007 specification. In October 2015, Oracle released SPARC M7, the first processor based on the new Oracle SPARC Architecture 2015 specification. This revision includes VIS 4 instruction set extensions and hardware-assisted encryption and silicon secured memory (SSM). SPARC architecture has provided continuous application binary compatibility from
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#17327810673511392-493: A number of additional points. Among these was the fact that programs spent a significant amount of time performing subroutine calls and returns, and it seemed there was the potential to improve overall performance by speeding these calls. This led the Berkeley design to select a method known as register windows which can significantly improve subroutine performance although at the cost of some complexity. They also noticed that
1508-598: A paper on ways to improve microcoding, but later changed his mind and decided microcode itself was the problem. With funding from the DARPA VLSI Program , Patterson started the Berkeley RISC effort. The Program, practically unknown today, led to a huge number of advances in chip design, fabrication, and even computer graphics. Considering a variety of programs from their BSD Unix variant, the Berkeley team found, as had IBM, that most programs made no use of
1624-484: A particular strategy for implementing some RISC designs, and modern RISC designs generally do away with it (such as PowerPC and more recent versions of SPARC and MIPS). Some aspects attributed to the first RISC- labeled designs around 1975 include the observations that the memory-restricted compilers of the time were often unable to take advantage of features intended to facilitate manual assembly coding, and that complex addressing modes take many cycles to perform due to
1740-413: A pipelined processor and for code generation by an optimizing compiler. A common misunderstanding of the phrase "reduced instruction set computer" is that instructions are simply eliminated, resulting in a smaller set of instructions. In fact, over the years, RISC instruction sets have grown in size, and today many of them have a larger set of instructions than many CISC CPUs. Some RISC processors such as
1856-401: A plus sign separating the operands, instead of using a comma-separated list. Examples: Due to the widespread use of non-32-bit data, such as 16-bit or 8-bit integral data or 8-bit bytes in strings, there are instructions that load and store 16-bit half-words and 8-bit bytes, as well as instructions that load 32-bit words. During a load, those instructions will read only the byte or half-word at
1972-451: A quad-aligned group of four floating-point registers can hold one quad-precision IEEE 754 floating-point number. A SPARC V9 processor with an FPU includes: The registers are organized as a set of 64 32-bit registers, with the first 32 being used as the 32-bit floating-point registers, even–odd pairs of all 64 registers being used as the 64-bit floating-point registers, and quad-aligned groups of four floating-point registers being used as
2088-536: A range of open source applications, including MySQL , PHP , gzip , and ImageMagick . Proper optimization for CoolThreads systems can result in significant gains: when the Sun Studio compiler is used with the recommended optimization settings, MySQL performance improves by 268% compared to using just the -O3 flag. Other UltraSPARC T2 performance related tunings are documented on Oracle engineers' blogs. Peak power consumption can go as high as 123 watts , but
2204-628: A rate of almost one instruction per clock cycle . This made them similar to the MIPS architecture in many ways, including the lack of instructions such as multiply or divide. Another feature of SPARC influenced by this early RISC movement is the branch delay slot . The SPARC processor usually contains as many as 160 general-purpose registers . According to the "Oracle SPARC Architecture 2015" specification an "implementation may contain from 72 to 640 general-purpose 64-bit" registers. At any point, only 32 of them are immediately visible to software — 8 are
2320-469: A reasonably sized constant in a 32-bit instruction word. Since many real-world programs spend most of their time executing simple operations, some researchers decided to focus on making those operations as fast as possible. The clock rate of a CPU is limited by the time it takes to execute the slowest sub-operation of any instruction; decreasing that cycle-time often accelerates the execution of other instructions. The focus on "reduced instructions" led to
2436-423: A register holds the value 10 and then branch to code that handles it, one would: In a conditional branch instruction, the icc or fcc field specifies the condition being tested. The 22-bit displacement field is the address, relative to the current PC, of the target, in words, so that conditional branches can go forward or backward up to 8 megabytes. The ANNUL (A) bit is used to get rid of some delay slots. If it
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#17327810673512552-523: A register or a 13-bit signed integer constant; the other operands are registers. Any of the register operands may point to G0; pointing the result to G0 discards the results, which can be used for tests. Examples include: The list of mathematical instructions is ADD , SUB , AND , OR , XOR , and negated versions ANDN , ORN , and XNOR . One quirk of the SPARC design is that most arithmetic instructions come in pairs, with one version setting
2668-506: A sequence of simpler internal instructions. In the 68k, a full 1 ⁄ 3 of the transistors were used for this microcoding. In 1979, David Patterson was sent on a sabbatical from the University of California, Berkeley to help DEC's west-coast team improve the VAX microcode. Patterson was struck by the complexity of the coding process and concluded it was untenable. He first wrote
2784-503: A sequence of simpler operations doing the same thing. This was in part an effect of the fact that many designs were rushed, with little time to optimize or tune every instruction; only those used most often were optimized, and a sequence of those instructions could be faster than a less-tuned instruction performing an equivalent operation as that sequence. One infamous example was the VAX 's INDEX instruction. The Berkeley work also turned up
2900-498: A set of global registers (one of which, g0 , is hard-wired to zero, so only seven of them are usable as registers) and the other 24 are from the stack of registers. These 24 registers form what is called a register window , and at function call/return, this window is moved up and down the register stack. Each window has eight local registers and shares eight registers with each of the adjacent windows. The shared registers are used for passing function parameters and returning values, and
3016-457: A single complex instruction such as STRING MOVE , but hide those details from the compiler. The internal operations of a RISC processor are "exposed to the compiler", leading to the backronym 'Relegate Interesting Stuff to the Compiler'. Most RISC architectures have fixed-length instructions and a simple encoding, which simplifies fetch, decode, and issue logic considerably. This is among
3132-482: A single data memory cycle—compared to the "complex instructions" of CISC CPUs that may require dozens of data memory cycles in order to execute a single instruction. The term load–store architecture is sometimes preferred. Another way of looking at the RISC/CISC debate is to consider what is exposed to the compiler. In a CISC processor, the hardware may internally use registers and flag bit in order to implement
3248-613: A very small set of instructions—but these designs are very different from classic RISC designs, so they have been given other names such as minimal instruction set computer (MISC) or transport triggered architecture (TTA). RISC architectures have traditionally had few successes in the desktop PC and commodity server markets, where the x86 -based platforms remain the dominant processor architecture. However, this may change, as ARM-based processors are being developed for higher performance systems. Manufacturers including Cavium , AMD, and Qualcomm have released server processors based on
3364-502: A year later for their mainframe and end-of-support in 2034 "to promote customer modernization". The SPARC architecture was heavily influenced by the earlier RISC designs, including the RISC I and II from the University of California, Berkeley and the IBM 801 . These original RISC designs were minimalist, including as few features or op-codes as possible and aiming to execute instructions at
3480-725: Is 0 in a conditional branch, the delay slot is executed as usual. If it is 1, the delay slot is only executed if the branch is taken. If it is not taken, the instruction following the conditional branch is skipped. There are a wide variety of conditional branches: BA (branch always, essentially a jmp), BN (branch never), BE (equals), BNE (not equals), BL (less than), BLE (less or equal), BLEU (less or equal, unsigned), BG (greater), BGE (greater or equal), BGU (greater unsigned), BPOS (positive), BNEG (negative), BCC (carry clear), BCS (carry set), BVC (overflow clear), BVS (overflow set). The FPU and CP have sets of condition codes separate from
3596-821: Is also a BluePrints article on using the Cryptographic Accelerator Units on the T1 and T2 processors. A wide range of applications were optimized on the CoolThreads platform, including Symantec Brightmail AntiSpam, Oracle's Siebel applications, and the Sun Java System Web Proxy Server . Sun also documented its experience in moving its own online store onto a T2000 server cluster, and have published two articles on web consolidation on CoolThreads using Solaris Containers . Sun had an application performance tuning page for
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3712-437: Is created by adding the two address operands to produce an address. The second address operand may be a constant or a register. Loads take the value at the address and place it in the register specified by the third operand, whereas stores take the value in the register specified by the first operand and place it at the address. To make this more obvious, the assembler language indicates address operands using square brackets with
3828-593: Is fully open, non-proprietary and royalty-free. As of 2024, the latest commercial high-end SPARC processors are Fujitsu 's SPARC64 XII (introduced in September 2017 for its SPARC M12 server) and Oracle 's SPARC M8 introduced in September 2017 for its high-end servers. On September 1, 2017, after a round of layoffs that started in Oracle Labs in November 2016, Oracle terminated SPARC design after completing
3944-490: The LD instruction, renamed LDUW , clears the upper 32 bits in the register and loads the 32-bit value into the lower 32 bits, and the ST instruction, renamed STW , discards the upper 32 bits of the register and stores only the lower 32 bits. The new LDSW instruction sets the upper bits in the register to the value of the uppermost bit of the word and loads the 32-bit value into
4060-550: The Adapteva Epiphany , have an optional short, feature-reduced compressed instruction set . Generally, these instructions expose a smaller number of registers and fewer bits for immediate values, and often use a two-operand format to eliminate one register number from instructions. A two-operand format in a system with 16 registers requires 8 bits for register numbers, leaving another 8 for an opcode or other uses. The SH5 also follows this pattern, albeit having evolved in
4176-623: The DEC Alpha , AMD Am29000 , Intel i860 and i960 , Motorola 88000 , IBM POWER , and, slightly later, the IBM/Apple/Motorola PowerPC . Many of these have since disappeared due to them often offering no competitive advantage over others of the same era. Those that remain are often used only in niche markets or as parts of other systems; of the designs from these traditional vendors, only SPARC and POWER have any significant remaining market. The ARM architecture has been
4292-511: The IBM System/360 architecture and successors and the x86 architecture. This means that a test and branch is normally performed with two instructions; the first is an ALU instruction that sets the condition codes, followed by a branch instruction that examines one of those flags. The SPARC does not have specialized test instructions; tests are performed using normal ALU instructions with the destination set to %G0. For instance, to test if
4408-641: The Motorola 68000 series of processors. SPARC V8 added a number of improvements that were part of the SuperSPARC series of processors released in 1992. SPARC V9, released in 1993, introduced a 64-bit architecture and was first released in Sun's UltraSPARC processors in 1995. Later, SPARC processors were used in symmetric multiprocessing (SMP) and non-uniform memory access ( CC-NUMA ) servers produced by Sun, Solbourne , and Fujitsu , among others. The design
4524-529: The RT PC —was less competitive than others, but the success of SPARC renewed interest within IBM, which released new RISC systems by 1990 and by 1995 RISC processors were the foundation of a $ 15 billion server industry. By the later 1980s, the new RISC designs were easily outperforming all traditional designs by a wide margin. At that point, all of the other vendors began RISC efforts of their own. Among these were
4640-691: The UltraSPARC T1 implementation: In 2007, Sun released an updated specification, UltraSPARC Architecture 2007 , to which the UltraSPARC T2 implementation complied. In December 2007, Sun also made the UltraSPARC T2 processor's RTL available via the OpenSPARC project. It was also released under the GNU General public license v2. OpenSPARC T2 is 8 cores, 16 pipelines with 64 threads. In August 2012, Oracle Corporation made available
4756-455: The laser printer , the router , and similar products. In the minicomputer market, companies that included Celerity Computing , Pyramid Technology , and Ridge Computers began offering systems designed according to RISC or RISC-like principles in the early 1980s. Few of these designs began by using RISC microprocessors . The varieties of RISC processor design include the ARC processor,
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4872-409: The load–store approach. The term RISC was coined by David Patterson of the Berkeley RISC project, although somewhat similar concepts had appeared before. The CDC 6600 designed by Seymour Cray in 1964 used a load–store architecture with only two addressing modes (register+register, and register+immediate constant) and 74 operation codes, with the basic clock cycle being 10 times faster than
4988-401: The 128-bit floating-point registers. Floating-point registers are not windowed; they are all global registers. All SPARC instructions occupy a full 32-bit word and start on a word boundary. Four formats are used, distinguished by the first two bits. All arithmetic and logical instructions have 2 source operands and 1 destination operand. RD is the "destination register", where the output of
5104-557: The 1980s as the MIPS and SPARC systems. IBM eventually produced RISC designs based on further work on the 801 concept, the IBM POWER architecture , PowerPC , and Power ISA . As the projects matured, many similar designs, produced in the mid-to-late 1980s and early 1990s, such as ARM , PA-RISC , and Alpha , created central processing units that increased the commercial utility of the Unix workstation and of embedded processors in
5220-707: The ARM architecture. ARM further partnered with Cray in 2017 to produce an ARM-based supercomputer. On the desktop, Microsoft announced that it planned to support the PC version of Windows 10 on Qualcomm Snapdragon -based devices in 2017 as part of its partnership with Qualcomm. These devices will support Windows applications compiled for 32-bit x86 via an x86 processor emulator that translates 32-bit x86 code to ARM64 code . Apple announced they will transition their Mac desktop and laptop computers from Intel processors to internally developed ARM64-based SoCs called Apple silicon ;
5336-545: The Berkeley RISC-II system. The US government Committee on Innovations in Computing and Communications credits the acceptance of the viability of the RISC concept to the success of the SPARC system. By 1989 many RISC CPUs were available; competition lowered their price to $ 10 per MIPS in large quantities, much less expensive than the sole sourced Intel 80386 . The performance of IBM's RISC CPU—only available in
5452-503: The CPU allows RISC computers few simple addressing modes and predictable instruction times that simplify design of the system as a whole. The conceptual developments of the RISC computer architecture began with the IBM 801 project in the late 1970s, but these were not immediately put into use. Designers in California picked up the 801 concepts in two seminal projects, Stanford MIPS and Berkeley RISC . These were commercialized in
5568-486: The CoolThreads platform can require different application development techniques than for traditional server platforms. Using TLP in applications is key to getting good performance. Sun has published a number of Sun BluePrints to assist application programmers in developing and deploying software on T1 or T2-based CoolThreads servers. The main article, Tuning Applications on UltraSPARC T1 Chip Multithreading Systems , addresses issues for general application programmers. There
5684-638: The DEC Alpha, the AMD Am29000 , the ARM architecture, the Atmel AVR , Blackfin , Intel i860 , Intel i960 , LoongArch , Motorola 88000 , the MIPS architecture, PA-RISC, Power ISA, RISC-V , SuperH , and SPARC. RISC processors are used in supercomputers , such as the Fugaku . A number of systems, going back to the 1960s, have been credited as the first RISC architecture, partly based on their use of
5800-448: The ISA, who in partnership with TI, GEC, Sharp, Nokia, Oracle and Digital would develop low-power and embedded RISC designs, and target those market segments, which at the time were niche. With the rise in mobile, automotive, streaming, smart device computing, ARM became the most widely used ISA, the company estimating almost half of all CPUs shipped in history have been ARM. Confusion around
5916-611: The M8. Much of the processor core development group in Austin, Texas, was dismissed, as were the teams in Santa Clara, California, and Burlington, Massachusetts. Fujitsu will also discontinue their SPARC production (has already shifted to producing their own ARM -based CPUs), after two "enhanced" versions of Fujitsu's older SPARC M12 server in 2020–22 (formerly planned for 2021) and again in 2026–27, end-of-sale in 2029, of UNIX servers and
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#17327810673516032-453: The NZVC condition code bits in the status register , and the other not setting them, with the default being not to set the codes. This is so that the compiler has a way to move instructions around when trying to fill delay slots. If one wants the condition codes to be set, this is indicated by adding cc to the instruction: add and sub also have another modifier, X, which indicates whether
6148-592: The PowerPC have instruction sets as large as the CISC IBM System/370 , for example; conversely, the DEC PDP-8 —clearly a CISC CPU because many of its instructions involve multiple memory accesses—has only 8 basic instructions and a few extended instructions. The term "reduced" in that phrase was intended to describe the fact that the amount of work any single instruction accomplishes is reduced—at most
6264-635: The RESTORE instruction (switching back to the call before returning from the procedure). Trap events ( interrupts , exceptions or TRAP instructions) and RETT instructions (returning from traps) also change the CWP . For SPARC V9, CWP register is decremented during a RESTORE instruction, and incremented during a SAVE instruction. This is the opposite of PSR.CWP's behavior in SPARC V8. This change has no effect on nonprivileged instructions. SPARC registers are shown in
6380-422: The RISC computer is that each instruction performs only one function (e.g. copy a value from memory to a register). The RISC computer usually has many (16 or 32) high-speed, general-purpose registers with a load–store architecture in which the code for the register-register instructions (for performing arithmetic and tests) are separate from the instructions that access the main memory of the computer. The design of
6496-580: The T1, the T2 supports the Hyper-Privileged execution mode. The SPARC Hypervisor runs in this mode and can partition a T2 system into 64 Logical Domains , and a two-way SMP T2 Plus system into 128 Logical Domains, each of which can run an independent operating system instance. The UltraSPARC T2 offers a variety of performance improvements over the former UltraSPARC T1 processor Leveraging the massive amount of thread-level parallelism (TLP) available on
6612-542: The T1. The T2 processor can be found in the following products from Sun and Fujitsu Computer Systems : Sun also licensed the T2 processor to Themis Computer , which introduced the first non-Sun T2-based servers in 2008: In April 2008, Sun released servers based on the UltraSPARC T2 Plus processor, an SMP capable version of UltraSPARC T2. Sun released the UltraSPARC T2 Plus processor with
6728-518: The T2 typically consumes 95 watts during nominal system operation. This is up from 72 watts from the T1. Sun explains that this is due to a higher degree of system integration onto the chip. On April 12, 2006, Sun announced the tape-out of the UltraSPARC T2. Sun announced the T2's release on 7 August 2007, billing it as "the world's fastest microprocessor". On April 9, 2008, Sun announced the UltraSPARC T2 Plus. On December 11, 2007, Sun made
6844-528: The UltraSPARC IV by Sun and the SPARC64 VI by Fujitsu. In early 2006, Sun released an extended architecture specification, UltraSPARC Architecture 2005 . This includes not only the non-privileged and most of the privileged portions of SPARC V9, but also all the architectural extensions developed through the processor generations of UltraSPARC III, IV, and IV+, as well as CMT extensions starting with
6960-502: The UltraSPARC T2 processor design publicly available under the GNU General Public License via the OpenSPARC project. The release includes: SPARC SPARC ( Scalable Processor ARChitecture ) is a reduced instruction set computer (RISC) instruction set architecture originally developed by Sun Microsystems . Its design was strongly influenced by the experimental Berkeley RISC system developed in
7076-535: The VAX. They followed this up with the 40,760-transistor, 39-instruction RISC-II in 1983, which ran over three times as fast as RISC-I. As the RISC project began to become known in Silicon Valley , a similar project began at Stanford University in 1981. This MIPS project grew out of a graduate course by John L. Hennessy , produced a functioning system in 1983, and could run simple programs by 1984. The MIPS approach emphasized an aggressive clock cycle and
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#17327810673517192-415: The application instruction ( load–store ) level or at the memory page level (via an MMU setting). The latter is often used for accessing data from inherently little-endian devices, such as those on PCI buses. There have been three major revisions of the architecture. The first published version was the 32-bit SPARC version 7 (V7) in 1986. SPARC version 8 (V8), an enhanced SPARC architecture definition,
7308-451: The bottom two bits of both operands are 0 and reporting overflow if they are not. This can be useful in the implementation of the run time for ML , Lisp , and similar languages that might use a tagged integer format. The endianness of the 32-bit SPARC V8 architecture is purely big-endian. The 64-bit SPARC V9 architecture uses big-endian instructions, but can access data in either big-endian or little-endian byte order, chosen either at
7424-472: The characteristic of having a branch delay slot , an instruction space immediately following a jump or branch. The instruction in this space is executed, whether or not the branch is taken (in other words the effect of the branch is delayed). This instruction keeps the ALU of the CPU busy for the extra time normally needed to perform a branch. Nowadays the branch delay slot is considered an unfortunate side effect of
7540-455: The completion of memory references. For example, all effects of the stores that appear prior to the MEMBAR instruction must be made visible to all processors before any loads following the MEMBAR can be executed. Arithmetic and logical instructions also use a three-operand format, with the first two being the operands and the last being the location to store the result. The middle operand can be
7656-522: The condition codes and versions that do. MULSCC and the multiply instructions use the Y register to hold the upper 32 bits of the product; the divide instructions use it to hold the upper 32 bits of the dividend. The RDY instruction reads the value of the Y register into a general-purpose register; the WRY instruction writes the value of a general-purpose register to the Y register. SPARC V9 added MULX , which multiplies two 64-bit values and produces
7772-441: The constants in a program would fit in 13 bits , yet many CPU designs dedicated 16 or 32 bits to store them. This suggests that, to reduce the number of memory accesses, a fixed length machine could store constants in unused bits of the instruction word itself, so that they would be immediately ready when the CPU needs them (much like immediate addressing in a conventional design). This required small opcodes in order to leave room for
7888-423: The definition of RISC deriving from the formulation of the term, along with the tendency to opportunistically categorize processor architectures with relatively few instructions (or groups of instructions) as RISC architectures, led to attempts to define RISC as a design philosophy. One attempt to do so was expressed as the following: A RISC processor has an instruction set that is designed for efficient execution by
8004-472: The early 1980s, leading, for example, to the iron law of processor performance . Since 2010, a new open standard instruction set architecture (ISA), Berkeley RISC-V , has been under development at the University of California, Berkeley, for research purposes and as a free alternative to proprietary ISAs. As of 2014, version 2 of the user space ISA is fixed. The ISA is designed to be extensible from
8120-439: The early 1980s. First developed in 1986 and released in 1987, SPARC was one of the most successful early commercial RISC systems, and its success led to the introduction of similar RISC designs from many vendors through the 1980s and 1990s. The first implementation of the original 32-bit architecture (SPARC V7) was used in Sun's Sun-4 computer workstation and server systems, replacing their earlier Sun-3 systems based on
8236-410: The figure above. There is also a non-windowed Y register, used by the multiply-step, integer multiply, and integer divide instructions. A SPARC V8 processor with an FPU includes 32 32-bit floating-point registers, each of which can hold one single-precision IEEE 754 floating-point number. An even–odd pair of floating-point registers can hold one double-precision IEEE 754 floating-point number, and
8352-552: The first SPARC V7 implementation in 1987 through the Sun UltraSPARC Architecture implementations. Among various implementations of SPARC, Sun's SuperSPARC and UltraSPARC-I were very popular, and were used as reference systems for SPEC CPU95 and CPU2000 benchmarks. The 296 MHz UltraSPARC-II is the reference system for the SPEC CPU2006 benchmark. SPARC is a load–store architecture (also known as
8468-535: The first such computers, using the Apple M1 processor, were released in November 2020. Macs with Apple silicon can run x86-64 binaries with Rosetta 2 , an x86-64 to ARM64 translator. Outside of the desktop arena, however, the ARM RISC architecture is in widespread use in smartphones, tablets and many forms of embedded devices. While early RISC designs differed significantly from contemporary CISC designs, by 2000
8584-525: The following changes: UltraSPARC T2 Plus processors can be found in the following products from Sun and Fujitsu Computer Systems : Two-way SMP servers: Four-way SMP server: The High Performance Computing Virtual Laboratory in Canada built a compute cluster using 78 Sun SPARC Enterprise T5140 servers. With two 1.2 GHz T2 Plus chips in each T5140 server, the cluster has close to 10,000 compute threads, making it ideal for high-throughput workloads. Like
8700-509: The highest-performing CPUs in the RISC line were almost indistinguishable from the highest-performing CPUs in the CISC line. RISC architectures are now used across a range of platforms, from smartphones and tablet computers to some of the world's fastest supercomputers such as Fugaku , the fastest on the TOP500 list as of November 2020 , and Summit , Sierra , and Sunway TaihuLight ,
8816-413: The immediate value 1. The original RISC-I format remains a canonical example of the concept. It uses 7 bits for the opcode and a 1-bit flag for conditional codes, the following 5 bits for the destination register, and the next five for the first operand. This leaves 14 bits, the first of which indicates whether the following 13 contain an immediate value or uses only five of them to indicate a register for
8932-424: The indicated location and then either fill the rest of the target register with zeros (unsigned load) or with the value of the uppermost bit of the byte or half-word (signed load). During a store, those instructions discard the upper bits in the register and store only the lower bits. There are also instructions for loading double-precision values used for floating-point arithmetic , reading or writing eight bytes from
9048-470: The indicated register and the "next" one, so if the destination of a load is L1, L1 and L2 will be set. The complete list of load and store instructions for the general-purpose registers in 32-bit SPARC is LD , ST , LDUB (unsigned byte), LDSB (signed byte), LDUH (unsigned half-word), LDSH (signed half-word), LDD (load double), STB (store byte), STH (store half-word), STD (store double). In SPARC V9, registers are 64-bit, and
9164-564: The individual instructions given to the computer to accomplish tasks. Compared to the instructions given to a complex instruction set computer (CISC), a RISC computer might require more instructions (more code) in order to accomplish a task because the individual instructions are written in simpler code. The goal is to offset the need to process more instructions by increasing the speed of each instruction, in particular by implementing an instruction pipeline , which may be simpler to achieve given simpler instructions. The key operational concept of
9280-403: The instruction encoding. This leaves ample room to indicate both the opcode and one or two registers. Register-to-register operations, mostly math and logic, require enough bits to encode the two or three registers being used. Most processors use the three-operand format, of the form A = B + C , in which case three registers numbers are needed. If the processor has 32 registers, each one requires
9396-445: The instruction word which could then be used to select among a larger set of registers. The telephone switch program was canceled in 1975, but by then the team had demonstrated that the same design would offer significant performance gains running just about any code. In simulations, they showed that a compiler tuned to use registers wherever possible would run code about three times as fast as traditional designs. Somewhat surprisingly,
9512-495: The integer condition codes and from each other; two additional sets of branch instructions were defined to test those condition codes. Adding an F to the front of the branch instruction in the list above performs the test against the FPU's condition codes, while, in SPARC V8, adding a C tests the flags in the otherwise undefined CP. The CALL (jump to subroutine) instruction uses a 30-bit program counter -relative word offset. As
9628-428: The large variety of instructions in the 68k. Patterson's early work pointed out an important problem with the traditional "more is better" approach; even those instructions that were critical to overall performance were being delayed by their trip through the microcode. If the microcode was removed, the programs would run faster. And since the microcode ultimately took a complex instruction and broke it into steps, there
9744-482: The late 1970s, the 801 had become well-known in the industry. This coincided with new fabrication techniques that were allowing more complex chips to come to market. The Zilog Z80 of 1976 had 8,000 transistors, whereas the 1979 Motorola 68000 (68k) had 68,000. These newer designs generally used their newfound complexity to expand the instruction set to make it more orthogonal. Most, like the 68k, used microcode to do this, reading instructions and re-implementing them as
9860-405: The local registers are used for retaining local values across function calls. The "scalable" in SPARC comes from the fact that the SPARC specification allows implementations to scale from embedded processors up through large server processors, all sharing the same core (non-privileged) instruction set. One of the architectural parameters that can scale is the number of implemented register windows;
9976-722: The lower bits. The new LDX instruction loads a 64-bit value into the register, and the STX instruction stores all 64 bits of the register. The LDF , LDDF , and LDQF instructions load a single-precision, double-precision, or quad-precision value from memory into a floating-point register; the STF , STDF , and STQF instructions store a single-precision, double-precision, or quad-precision floating-point register into memory. The memory barrier instruction, MEMBAR, serves two interrelated purposes: it articulates order constraints among memory references and facilitates explicit control over
10092-494: The main goals of the RISC approach. Some of this is possible only due to the contemporary move to 32-bit formats. For instance, in a typical program, over 30% of all the numeric constants are either 0 or 1, 95% will fit in one byte, and 99% in a 16-bit value. When computers were based on 8- or 16-bit words, it would be difficult to have an immediate combined with the opcode in a single memory word, although certain instructions like increment and decrement did this implicitly by using
10208-422: The majority of mathematical instructions were simple assignments; only 1 ⁄ 3 of them actually performed an operation like addition or subtraction. But when those operations did occur, they tended to be slow. This led to far more emphasis on the underlying arithmetic data unit, as opposed to previous designs where the majority of the chip was dedicated to control and microcode. The resulting Berkeley RISC
10324-512: The memory access time. Partly due to the optimized load–store architecture of the CDC 6600, Jack Dongarra says that it can be considered a forerunner of modern RISC systems, although a number of other technical barriers needed to be overcome for the development of a modern RISC system. Michael J. Flynn views the first RISC system as the IBM 801 design, begun in 1975 by John Cocke and completed in 1980. The 801 developed out of an effort to build
10440-558: The mid-1980s. The Acorn ARM1 appeared in April 1985, MIPS R2000 appeared in January 1986, followed shortly thereafter by Hewlett-Packard 's PA-RISC in some of their computers. In the meantime, the Berkeley effort had become so well known that it eventually became the name for the entire concept. In 1987 Sun Microsystems began shipping systems with the SPARC processor, directly based on
10556-563: The most significant characteristics of RISC processors was that external memory was only accessible by a load or store instruction. All other instructions were limited to internal registers. This simplified many aspects of processor design: allowing instructions to be fixed-length, simplifying pipelines, and isolating the logic for dealing with the delay in completing a memory access (cache miss, etc.) to only two instructions. This led to RISC designs being referred to as load–store architectures. Some CPUs have been specifically designed to have
10672-657: The most widely adopted RISC ISA, initially intended to deliver higher-performance desktop computing, at low cost, and in a restricted thermal package, such as in the Acorn Archimedes , while featuring in the Super Computer League tables , its initial, relatively, lower power and cooling implementation was soon adapted to embedded applications, such as laser printer raster image processing. Acorn, in partnership with Apple Inc, and VLSI, creating ARM Ltd, in 1990, to share R&D costs and find new markets for
10788-540: The opcode was 0 and the last 6 bits contained the actual code; those that used an immediate value used the normal opcode field at the front. One drawback of 32-bit instructions is reduced code density, which is more adverse a characteristic in embedded computing than it is in the workstation and server markets RISC architectures were originally designed to serve. To address this problem, several architectures, such as SuperH (1992), ARM thumb (1994), MIPS16e (2004), Power Variable Length Encoding ISA (2006), RISC-V , and
10904-443: The operation is deposited. The majority of SPARC instructions have at least this register, so it is placed near the "front" of the instruction format. RS1 and RS2 are the "source registers", which may or may not be present, or replaced by a constant. Load and store instructions have a three-operand format, in that they have two operands representing values for the address and one operand for the register to read or write to. The address
11020-530: The operation should set the carry bit: SPARC V7 does not have multiplication or division instructions, but it does have MULSCC , which does one step of a multiplication testing one bit and conditionally adding the multiplicand to the product. This was because MULSCC can complete over one clock cycle in keeping with the RISC philosophy. SPARC V8 added UMUL (unsigned multiply), SMUL (signed multiply), UDIV (unsigned divide), and SDIV (signed divide) instructions, with both versions that do not update
11136-531: The opposite direction, having added longer 32-bit instructions to an original 16-bit encoding. The most characteristic aspect of RISC is executing at least one instruction per cycle . Single-cycle operation is described as "the rapid execution of simple functions that dominate a computer's instruction stream", thus seeking to deliver an average throughput approaching one instruction per cycle for any single instruction stream. Other features of RISC architectures include: RISC designs are also more likely to feature
11252-584: The register file is not part of the architecture, allowing more registers to be added as the technology improves, up to a maximum of 32 windows in SPARC V7 and V8 as CWP is 5 bits and is part of the PSR register. In SPARC V7 and V8 CWP will usually be decremented by the SAVE instruction (used by the SAVE instruction during the procedure call to open a new stack frame and switch the register window), or incremented by
11368-497: The required additional memory accesses. It was argued that such functions would be better performed by sequences of simpler instructions if this could yield implementations small enough to leave room for many registers, reducing the number of slow memory accesses. In these simple designs, most instructions are of uniform length and similar structure, arithmetic operations are restricted to CPU registers and only separate load and store instructions access memory. These properties enable
11484-402: The resulting machine being called a "reduced instruction set computer" (RISC). The goal was to make instructions so simple that they could easily be pipelined, in order to achieve a single clock throughput at high frequencies . This contrasted with CISC designs whose "crucial arithmetic operations and register transfers" were considered difficult to pipeline. Later, it was noted that one of
11600-508: The same code would run about 50% faster even on existing machines due to the improved register use. In practice, their experimental PL/8 compiler, a slightly cut-down version of PL/I , consistently produced code that ran much faster on their existing mainframes. A 32-bit version of the 801 was eventually produced in a single-chip form as the IBM ROMP in 1981, which stood for 'Research OPD [Office Products Division] Micro Processor'. This CPU
11716-475: The second half of the 1980s, and led the designers of the MIPS-X to put it this way in 1987: The goal of any instruction format should be: 1. simple decode, 2. simple decode, and 3. simple decode. Any attempts at improved code density at the expense of CPU performance should be ridiculed at every opportunity. Competition between RISC and conventional CISC approaches was also the subject of theoretical analysis in
11832-408: The second operand. A more complex example is the MIPS encoding, which used only 6 bits for the opcode, followed by two 5-bit registers. The remaining 16 bits could be used in two ways, one as a 16-bit immediate value, or as a 5-bit shift value (used only in shift operations, otherwise zero) and the remaining 6 bits as an extension on the opcode. In the case of register-to-register arithmetic operations,
11948-562: The specification allows from three to 32 windows to be implemented, so the implementation can choose to implement all 32 to provide maximum call stack efficiency, or to implement only three to reduce cost and complexity of the design, or to implement some number between them. Other architectures that include similar register file features include Intel i960 , IA-64 , and AMD 29000 . The architecture has gone through several revisions. It gained hardware multiply and divide functionality in version 8. 64-bit (addressing and data) were added to
12064-434: The target address is specifying the start of a word, not a byte, 30-bits is all that is needed to reach any address in the 4 gigabyte address space. The CALL instruction deposits the return address in register R15, also known as output register O7. Reduced instruction set computer In electronics and computer science , a reduced instruction set computer ( RISC ) is a computer architecture designed to simplify
12180-459: The use of memory; a single instruction from a traditional processor like the Motorola 68k may be written out as perhaps a half dozen of the simpler RISC instructions. In theory, this could slow the system down as it spent more time fetching instructions from memory. But by the mid-1980s, the concepts had matured enough to be seen as commercially viable. Commercial RISC designs began to emerge in
12296-514: The use of the pipeline, making sure it could be run as "full" as possible. The MIPS system was followed by the MIPS-X and in 1984 Hennessy and his colleagues formed MIPS Computer Systems to produce the design commercially. The venture resulted in a new architecture that was also called MIPS and the R2000 microprocessor in 1985. The overall philosophy of the RISC concept was widely understood by
12412-441: The vast majority of the available instructions, especially orthogonal addressing modes. Instead, they selected the fastest version of any given instruction and then constructed small routines using it. This suggested that the majority of instructions could be removed without affecting the resulting code. These two conclusions worked in concert; removing instructions would allow the instruction opcodes to be shorter, freeing up bits in
12528-767: The version 9 SPARC specification published in 1994. In SPARC version 8, the floating-point register file has 16 double-precision registers. Each of them can be used as two single-precision registers, providing a total of 32 single-precision registers. An odd–even number pair of double-precision registers can be used as a quad-precision register, thus allowing 8 quad-precision registers. SPARC Version 9 added 16 more double-precision registers (which can also be accessed as 8 quad-precision registers), but these additional registers can not be accessed as single-precision registers. No SPARC CPU implements quad-precision operations in hardware as of 2024. Tagged add and subtract instructions perform adds and subtracts on values checking that
12644-495: The window "down" by eight, to the set of eight registers used by that procedure, and the return moves the window back. The Berkeley RISC project delivered the RISC-I processor in 1982. Consisting of only 44,420 transistors (compared with averages of about 100,000 in newer CISC designs of the era), RISC-I had only 32 instructions, and yet completely outperformed any other single-chip design, with estimated performance being higher than
12760-498: Was based on gaining performance through the use of pipelining and aggressive use of register windowing. In a traditional CPU, one has a small number of registers, and a program can use any register at any time. In a CPU with register windows, there are a huge number of registers, e.g., 128, but programs can only use a small number of them, e.g., eight, at any one time. A program that limits itself to eight registers per procedure can make very fast procedure calls : The call simply moves
12876-468: Was designed for "mini" tasks, and found use in peripheral interfaces and channel controllers on later IBM computers. It was also used as the CPU in the IBM RT PC in 1986, which turned out to be a commercial failure. Although the 801 did not see widespread use in its original form, it inspired many research projects, including ones at IBM that would eventually lead to the IBM POWER architecture . By
12992-474: Was no reason the compiler couldn't do this instead. These studies suggested that, even with no other changes, one could make a chip with 1 ⁄ 3 fewer transistors that would run faster. In the original RISC-I paper they noted: Skipping this extra level of interpretation appears to enhance performance while reducing chip size. It was also discovered that, on microcoded implementations of certain architectures, complex operations tended to be slower than
13108-629: Was released by Fujitsu and Sun, describing processor functions which were identically implemented in the CPUs of both companies ("Commonality"). The first CPUs conforming to JPS1 were the UltraSPARC III by Sun and the SPARC64 V by Fujitsu. Functionalities which are not covered by JPS1 are documented for each processor in "Implementation Supplements". At the end of 2003, JPS2 was released to support multicore CPUs. The first CPUs conforming to JPS2 were
13224-587: Was released by SPARC International in 1993. It was developed by the SPARC Architecture Committee consisting of Amdahl Corporation , Fujitsu , ICL , LSI Logic , Matsushita , Philips , Ross Technology , Sun Microsystems , and Texas Instruments . Newer specifications always remain compliant with the full SPARC V9 Level 1 specification. In 2002, the SPARC Joint Programming Specification 1 (JPS1)
13340-412: Was released in 1990. The main differences between V7 and V8 were the addition of integer multiply and divide instructions, and an upgrade from 80-bit "extended-precision" floating-point arithmetic to 128-bit " quad-precision " arithmetic. SPARC V8 served as the basis for IEEE Standard 1754-1994, an IEEE standard for a 32-bit microprocessor architecture. SPARC version 9 , the 64-bit SPARC architecture,
13456-694: Was turned over to the SPARC International trade group in 1989, and since then its architecture has been developed by its members. SPARC International is also responsible for licensing and promoting the SPARC architecture, managing SPARC trademarks (including SPARC, which it owns), and providing conformance testing . SPARC International was intended to grow the SPARC architecture to create a larger ecosystem; SPARC has been licensed to several manufacturers, including Atmel , Bipolar Integrated Technology , Cypress Semiconductor , Fujitsu , Matsushita and Texas Instruments . Due to SPARC International, SPARC
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