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73-467: The Zilog Z8000 is a 16-bit microprocessor architecture designed by Zilog and introduced in early 1979. Two chips were initially released, only differing in the width of the address bus: the Z8001 (23-bits) and Z8002 (16-bits). The Z8000 is not Z80 -compatible, but includes a number of design elements from it, such as combining two registers into one with twice the number of bits. Bernard Peuto designed

146-463: A computer 's primary memory into segments or sections . In a computer system using segmentation, a reference to a memory location includes a value that identifies a segment and an offset (memory location) within that segment. Segments or sections are also used in object files of compiled programs when they are linked together into a program image and when the image is loaded into memory. Segments usually correspond to natural divisions of

219-442: A segmentation fault is raised. Segments may also be used to implement virtual memory . In this case each segment has an associated flag indicating whether it is present in main memory or not. If a segment is accessed that is not present in main memory, an exception is raised, and the operating system will read the segment into memory from secondary storage. Segmentation is one method of implementing memory protection . Paging

292-439: A 16-bit external bus and 24-bit addressing of the processor it replaced. In the context of IBM PC compatible and Wintel platforms, a 16-bit application is any software written for MS-DOS , OS/2 1.x or early versions of Microsoft Windows which originally ran on the 16-bit Intel 8088 and Intel 80286 microprocessors . Such applications used a 20- bit or 24-bit segment or selector-offset address representation to extend

365-432: A complete 16-bit data bus and 24-bit address bus, as that would leave only 8 free pins, which is not nearly enough for various other interfacing needs like power, clocks and interrupts. To address this, the Z8001 multiplexed the address and data pins together. The first 16 pins of the 23-pin address bus were used on alternate cycles as a 16-bit data bus. This meant that every memory access took two complete memory cycles: first

438-687: A fixed offset equal to 16 times the segment number; the segment starting address granularity is 16 bytes. Each segment grants read-write access to 64 KiB (65,536 bytes) of address space (this limit is set by the 16-bit PC and SP registers; the processor does no bounds checking). Offset+address exceeding 0xFFFFF wraps around to 0x00000. Each 64 KiB segment overlaps the next 4,095 segments; each physical address can be denoted by 4,096 segment–offset pairs. This scheme can address only 1 MiB (1024 KiB) of physical memory (and memory-mapped i/o). (Optional expanded memory hardware can add bank-switched memory under software control.) Intel retroactively named

511-480: A leading 0 in bit 15, the 7-bit segment number, and then 8 zeros. This requires more memory to store, as each 23-bit address uses up 32 bits of register space, but allows the addresses to be cleanly stored in the 16-bit registers and can be more easily pushed and popped from the stack, which occurs in 16-bit words. The optional 48-pin Z8010 memory management unit (MMU) expands the memory map to 16 MB by translating

584-513: A low-cost option able to access (what was then) large amounts of memory, the Intel designs were competitive and available over a year earlier. For those looking for pure performance, the Z8000 was the fastest CPU available in early 1979. But this was true only for a period of a few months. The 16/32-bit 8 MHz Motorola 68000 came to market later the same year and turns in a time of 0.49 seconds on

657-601: A process, led to questions about the longevity of the Series 8000 products as 32-bit processor architectures from Motorola and National Semiconductor became more widely adopted. Zilog Systems eventually adopted AT&T's 32-bit WE32100 processor, introducing it in a new product, the System 8000/32, alongside 32-bit upgrades to its existing System 8000 Series 2 models. This enabled the introduction of Unix System V on Zilog Systems' products. The adoption by Zilog's Systems Division of

730-461: A program such as individual routines or data tables so segmentation is generally more visible to the programmer than paging alone. Segments may be created for program modules , or for classes of memory usage such as code segments and data segments . Certain segments may be shared between programs. Segmentation was originally invented as a method by which system software could isolate software processes ( tasks ) and data they are using. It

803-448: A segment size of either 64 KiB or 1 MiB and a page size of either 2 KiB or 4 KiB; control register 1 contains a Segment Table Designator (STD), which specifies the length and real address of the segment table. Each segment table entry contains a page table location, a page table length and an invalid bit. IBM later expanded the address size to 31 bits and added two bits to the segment table entries: Each of IBM's DAT implementations includes

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876-477: A slow process like reading a floppy disk is now available and the CPU can read the data into memory. Normally on small machines, an interrupt causes special code to run that examines various status bits and memory locations to decide what device actually called the interrupt and why. In some designs, especially those intended for realtime computing , an area of memory is set aside as a set of pointers, or vectors, to

949-485: A system with direct access to a 23-bit address would need to read three bytes (24 bits) from memory for every address referred to in the code, thus requiring two reads on a 16-bit bus. With segments, the addresses need only a single 16-bit read which is then added to a segment number to produce the complete address. The segment number only needs to be updated when the data crosses the 16-bit/64 KB boundaries. Internally, addresses are all 32 bits: an upper 16-bit word with

1022-586: A translation cache, which IBM called a Translation Lookaside Buffer (TLB). While Principles of Operation discusses the TLB in general terms, the details are not part of the architecture and vary from model to model. Starting with the 3031, 3032, and 3033 processor complexes, IBM offered a feature called Dual-address Space (DAS), which allows a program to switch between the translation tables for two address spaces, referred to as primary address space (CR1) and secondary address space (CR7), and to move data between

1095-643: A version of its architecture is still in use today on the Unisys ClearPath Libra servers. The GE 645 computer, a modification of the GE-635 with segmentation and paging support added, was designed in 1964 to support Multics . The Intel iAPX 432 , begun in 1975, attempted to implement a true segmented architecture with memory protection on a microprocessor. The 960MX version of the Intel i960 processors supported load and store instructions with

1168-451: Is 65,536, a processor with 16-bit memory addresses can directly access 64 KB (65,536 bytes) of byte-addressable memory. If a system uses segmentation with 16-bit segment offsets, more can be accessed. The MIT Whirlwind ( c. 1951) was quite possibly the first-ever 16-bit computer. It was an unusual word size for the era; most systems used six-bit character code and used a word length of some multiple of 6-bits. This changed with

1241-515: Is an index into a table of object descriptors, giving an object type, an object length, and a physical address for the object's data, a page table for the object, or the top-level page table for a two-level page table for the object, depending on the object type. Prime , Stratus , Apollo , IBM System/38 , and IBM AS/400 (including IBM i ) computers use memory segmentation. Words in the B5000, B5500 and B5700 are 48 bits long. Descriptors have

1314-434: Is another, and they can be combined. The size of a memory segment is generally not fixed and may be as small as a single byte . Segmentation has been implemented several ways on various hardware, with or without paging. Intel x86 memory segmentation does not fit either model and is discussed separately below, and also in greater detail in a separate article. Associated with each segment is information that indicates where

1387-418: Is easy to read or write 2 KB blocks to a hard drive , so this pattern more closely matches what will ultimately happen on a segfault . One uncommon feature found on the Z8000, more commonly associated with minicomputers , is direct support for vectored interrupts . Interrupts are used by external devices to notify the processor that some condition has been met; a common use is to indicate that data from

1460-443: Is impressive when compared to the 8-bit designs it replaced, including Zilog's 4 MHz Z80 at 6.8 seconds, and the popular 1 MHz MOS 6502 at 13.9. Even the newer 1 MHz Motorola 6809 was much slower, at 5.1 seconds. It also fares well against the 8 MHz Intel 8086 which turned in a time of 1.9 seconds, or the less expensive 5 MHz Intel 8088 at 4 seconds. While the Intel processors were easily outperformed by

1533-460: Is normally handled by the video display controller or external logic. This was implemented via a separate Refresh Counter (RC) register that held the currently updating page of memory. The feature is turned on by setting the most significant bit of the RC, bit 15, to 1. The following six bits, 14 through 9 are a rate, measured in terms of every 4th clock cycle. With a standard 4 MHz clock, that allows

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1606-458: Is that the Z8015 breaks down the memory into 64 2 KB blocks, whereas the Z8010 broke memory into 64 variable-sized blocks, up to 64 KB each. Additionally, the Z8015 expands the segment number from 7 to 12 bits, and then using those as the most significant bits of the 23-bit overall address, overriding the upper bits of the original 16-bit offset. The advantage to this access scheme is that it

1679-583: The HP BPC . Other notable 16-bit processors include the Intel 8086 , the Intel 80286 , the WDC 65C816 , and the Zilog Z8000 . The Intel 8088 was binary compatible with the Intel 8086, and was 16-bit in that its registers were 16 bits wide, and arithmetic instructions could operate on 16-bit quantities, even though its external bus was 8 bits wide. 16-bit processors have been almost entirely supplanted in

1752-627: The Motorola 68000 of a few months later used 68,000. Several third parties manufactured the Z8000 including AMD , SGS-Ates , Toshiba and Sharp . 16-bit computing A 16-bit register can store 2 different values. The range of integer values that can be stored in 16 bits depends on the integer representation used. With the two most common representations, the range is 0 through 65,535 (2 − 1) for representation as an ( unsigned ) binary number , and −32,768 (−1 × 2 ) through 32,767 (2 − 1) for representation as two's complement . Since 2

1825-471: The personal computer industry, and are used less than 32-bit (or 8-bit) CPUs in embedded applications. The Motorola 68000 is sometimes called 16-bit because of the way it handles basic arithmetic. The instruction set was based on 32-bit numbers and the internal registers were 32 bits wide, so by common definitions, the 68000 is a 32-bit design. Internally, 32-bit arithmetic is performed using two 16-bit operations, and this leads to some descriptions of

1898-475: The 1970s fall into this category; the MOS 6502 , Intel 8080 , Zilog Z80 and most others had 16-bit address space which provided 64 KB of address space. This also meant address manipulation required two instruction cycles. For this reason, most processors had special 8-bit addressing modes, the zero page , improving speed. This sort of difference between internal register size and external address size remained in

1971-488: The 1980s, although often reversed, as memory costs of the era made a machine with 32-bit addressing, 2 or 4 GB, a practical impossibility. For example, the 68000 exposed only 24 bits of addressing on the DIP , limiting it to a still huge (for the era) 16 MB. A similar analysis applies to Intel's 80286 CPU replacement, called the 386SX , which is a 32-bit processor with 32-bit ALU and internal 32-bit data paths with

2044-408: The 23-bit address from the CPU to a 24-bit one. A Z8010 has 64 segment descriptor registers, each of which contains a 16-bit base physical address, an 8-bit limit, and an 8-bit set of attributes. When the CPU attempts to access a particular segment, a 7-bit value, the Z8010 uses the lower 6 bits of the segment number to select a segment descriptor register, checks the 16-bit offset in the segment against

2117-536: The 64 KB versions of the Z8000. In one instance, the Z8001 was used to implement a capability-based architecture, employing the segment number in the addressing model of the Z8001 to indicate a capability register in a virtual processor. Such virtual processors were provided through the augmentation of the Z8001 with an "intelligent memory device", this providing memory management and context switching facilities, with additional capability-related instructions being supported through emulation. The reported inclusion of

2190-633: The B6500, B6700, B7700, B6800, B6900, B5900, the A-series Burroughs and Unisys machines, and the current Clearpath MCP systems (Libra). While there have been a few enhancements over the years, particularly hardware advances, the architecture has changed little. The segmentation scheme has remained the same, see Segmented memory . In the IBM System/370 models with virtual storage (DAT) and 24-bit addresses, control register 0 specifies

2263-774: The S8000 computer although this did not help its long-term success. The S8000 did find some success with the IRS and tax preparers in United States, who used the model for processing of electronically filed tax returns. The Z8000 featured in Steve Ciarcia's Trump Card project for his Circuit Cellar column in Byte magazine , providing an expansion card with the Z8001 processor and 512 KB of RAM suitable for use with an IBM-compatible PC. Compilers for BASIC and C were supplied with

Zilog Z8000 - Misplaced Pages Continue

2336-608: The WE32100 as "the premier UNIX chip". Zilog subsequently announced an agreement to manufacture the WE32100 chipset for a five year period, being the first alternative source of these products. There was a Z8000 version of the Xenix Operating System. In 1982, Digital Research and Zilog announced an agreement to make CP/M available for the Z8000. Namco used the Z8000 series in its Pole Position and Pole Position II arcade games. The machines used two Z8002's,

2409-469: The WE32100, in preference to the continued use of products from Zilog's Component Division, was driven by diverging requirements. Zilog sought to introduce its 32-bit successor to the Z8000, the Z80000, to build on successful adoption of the 16-bit product in military and graphical applications, whereas its Systems Division prioritised Unix support and commercial applications. The conclusion was reached to adopt

2482-448: The Z8000 was first released it contained a number of bugs. This was due to its complex instruction decoder, which, unlike most processors of the era, did not use microcode and was dependent on logic implemented directly in the CPU. This allowed the design to eliminate the microcode storage and the associated decoding logic, which reduced the transistor count to 17,500. In contrast, the contemporary Intel 8088 used 29,000 transistors, while

2555-538: The Z8001 and Z8002, respectively. These versions were designed to provide improved support for virtual memory , adding new status registers to indicate segmentation faults (test and set) and provide an abort capability. There are sixteen 16-bit registers , labeled R0 through R15. The registers can be concatenated into eight 32-bit registers, labeled RR0/RR2/../RR14, or into four 64-bit registers, labeled RQ0/RQ4/RQ8/RQ12. The first eight registers can be also subdivided into sixteen 8-bit registers, labeled RL0 though RL7 for

2628-539: The Z8001, they were packaged in 40-pin DIPs, which made them less expensive to implement than the 48-pin Z8001. The Z8002 also used a 40-pin package, but had a 16-bit address bus that could only access 64 KB of RAM, whereas the Intel processors had a 20-bit bus that could access 1 MB of RAM. Internally, the 23-bit addresses of the Z8000 were also more complex to process than Intel's simpler system using 16-bit base addresses and separate segment registers. For those looking for

2701-494: The Z8002 with 16-bit addressing to allow 64 kilobytes of memory. This allowed the Z8002 to have eight fewer pins, shipping in a smaller 40-pin DIP format that made it less expensive to implement. Zilog stated that the Z8001 and Z8002 were merely differently packaged versions of the same Z8000 chip, "the difference being achieved by a bonding option during manufacture". Even with 48 pins, there were not enough connections to allow for

2774-535: The address spaces subject to protection key. DAS supports a translation table to convert a 16-bit address space number (ASN) to an STD, with privileged instructions to load the STD into CR1 (primary) or CR7 (secondary). Early x86 processors, beginning with the Intel 8086 , provide crude memory segmentation and no memory protection . (Every byte of every segment is always available to any program.) The 16-bit segment registers allow for 65,536 segments; each segment begins at

2847-460: The address would be presented and had to be "latched" using external circuity, and then on the next cycle 16 bit of data would be read or written using the same pins. This means the Z8000 would run roughly half as fast as something like the 68000, which had separate 16 data pins and 24 address pins on a larger 64-pin chip. The series was later expanded to include the Z8003 and Z8004 updated versions of

2920-456: The architecture, while Masatoshi Shima did the logic and physical implementation, assisted by a small group. In contrast to most designs of the era, the Z8000 does not use microcode , which allowed it to be implemented in only 17,500 transistors. Although it saw some use in the early 1980s, it was never as popular as the Z80. It was released after the 16-bit 8086 (April 1978) and the same time as

2993-470: The board, along with an assembler and a Z80 emulator that could run programs written for CP/M-80. It was envisaged that Unix would also be made available for the Trump Card. Despite a somewhat positive reception as "a reasonably fast supermicro with generally good performance for the price", the 16-bit architectural limitations of the Z8000, with segment handling required to access more than 64 KB in

Zilog Z8000 - Misplaced Pages Continue

3066-423: The code handling a particular device. The devices causing the interrupt then set some state, typically via pins on the CPU, to indicate a particular interrupt number, N. When the interrupt is called, the CPU immediately jumps through Nth entry in the table, avoiding any need to decode the interrupt. This can greatly speed up the interrupt servicing by avoiding having to run additional operations, while also simplifying

3139-621: The device within military designs perhaps provides an explanation for the continued survival of the Z8000, in the shape of the Zilog Z16C01/02 CPUs. Also, the Standard Central Air Data Computer (SCADC) was using the Z8002. However, the end of life notice from Zilog was sent in 2012. While the Z8000 did see some use in the early 1980s, it was passed over for other designs relatively quickly. Federico Faggin , then CEO of Zilog, later suggested this

3212-692: The effort to introduce ASCII , which used a 7-bit code and naturally led to the use of an 8-bit multiple which could store a single ASCII character or two binary coded decimal digits. The 16-bit word length thus became more common in the 1960s, especially on minicomputer systems. Early 16-bit computers ( c. 1965–70) include the IBM 1130 , the HP 2100 , the Data General Nova , and the DEC PDP-11 . Early 16-bit microprocessors , often modeled on one of

3285-477: The entire memory to be accessed from 64 segments. If more than 64 segments are needed, multiple Z8010s can be used, with the upper bit of the 7-bit segment number selecting which Z8010 is used. The Z8010 was not available at the time of launch, and was ultimately nine months to a year late. With the release of the Z8003/Z8004, the Z8015 was added to the lineup, adding paged memory support. The main difference

3358-439: The entire segment. Often memory fragmentation results if there is not enough contiguous memory even though there may be enough in total. Instead of a memory location, the segment information includes the address of a page table for the segment. When a program references a memory location the offset is translated to a memory address using the page table. A segment can be extended by allocating another memory page and adding it to

3431-503: The interrupt handling code. In the Z8000, a new register supports vectors, the New Program Status Area Pointer. This was similar to a memory address in a register, consisting of two 16-bit values with the upper 16 bits holding the segment number. The lower 16 bits are then divided in half, the upper 8-bit containing an offset and the lower 8 bits empty. To call a particular vector, the external device presents

3504-447: The less-expensive 8088 , and only months before the 68000 (September 1979) with a 32-bit instruction set architecture and which is roughly twice as fast. The Z80000 was a 32-bit follow-on design, that made it to a test sampling phase in 1986 without ever being released commercially. The Z8000 initially shipped in two versions: the Z8001 with a full 23-bit external address bus to allow it to access up to 8 megabytes of memory, and

3577-475: The limit value in that register and checks the permission bits in the attributes to see whether the access is allowed and, if the access is allowed, adds the base physical address to the segment offsset to generate a physical address. This allows multiple programs to be spread out in physical RAM, each given its own space to work in while believing it is accessing the entire 8 MB of RAM. The segments are variable length, expanding up to 64 KB in order to allow

3650-548: The lower 8 bits (or 9 in some cases) on the address bus, and the complete vector address is constructed from the three values. In the early 1980s, the Zilog Z8000 CPU was popular for desktop-sized Unix machines. These low-cost Unix systems allowed small businesses to run a true multi-user system and share resources (disk, printers) before networking was common. They usually had only RS-232 serial ports (4–16) and parallel printer ports instead of built-in graphics, as

3723-400: The lower byte and RH0 through RH7 for the upper (high) byte. Register R15 is designated as stack pointer . On the Z8001, register R14 is used to include a fixed segment in the stack pointer, and the program counter is expanded to 32 bits to include a similar segment. There is both a user mode ("normal") and a supervisor mode , selected by bit 14 in the flag register. In supervisor mode,

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3796-572: The mini platforms, began to appear in the 1970s. Examples ( c. 1973–76) include the five-chip National Semiconductor IMP-16 (1973), the two-chip NEC μCOM-16 (1974), the three-chip Western Digital MCP-1600 (1975), and the five-chip Toshiba T-3412 (1976). Early single-chip 16-bit microprocessors ( c. 1975–76) include the Panafacom MN1610 (1975), National Semiconductor PACE (1975), General Instrument CP1600 (1975), Texas Instruments TMS9900 (1976), Ferranti F100-L , and

3869-495: The operating system or a DOS extender . If a program does not use the segment registers, or only puts values into them that it receives from the operating system, then identical code can run in real mode or protected mode, but most real-mode software computes new values for the segment registers, breaking this compatibility. The Intel i386 and later processors add "386 protected mode ", which uses 32-bit addressing, retains segmentation, and adds memory paging . In these processors,

3942-446: The range of addressable memory locations beyond what was possible using only 16-bit addresses. Programs containing more than 2 bytes (65,536 bytes ) of instructions and data therefore required special instructions to switch between their 64-kilobyte segments , increasing the complexity of programming 16-bit applications. Segmented memory Memory segmentation is an operating system memory management technique of dividing

4015-426: The reference to that segment and offset is permitted. Each segment has a length and set of permissions (for example, read , write , execute ) associated with it. A process is only allowed to make a reference into a segment if the type of reference is allowed by the permissions, and if the offset within the segment is within the range specified by the length of the segment. Otherwise, a hardware exception such as

4088-430: The refresh to be called every 1 to 64 microseconds. The remaining 8 bits select a row in memory to refresh. The Z8000 has a segmented memory map, with a 7-bit "segment number" and a 16-bit offset. Both numbers are represented by pins on the Z8001, meaning that it can directly address a 23-bit memory, or 8 MB. Instructions can only directly access a 16-bit offset. This allows the instruction format to be smaller;

4161-498: The same Sieve test, over twice as fast as the Z8000. Although it used an even larger 64-pin DIP layout, for those willing to move to more than 40 pins this was a small price to pay for what was by far the fastest processor of its era. Its 32-bit instructions and registers, combined with a 24-bit address bus with flat 16 MB addressing, also made it much more attractive to designers, something Faggin admits to. To add to its problems, when

4234-471: The segment is located in memory— the segment base . When a program references a memory location, the offset is added to the segment base to generate a physical memory address. An implementation of virtual memory on a system using segmentation without paging requires that entire segments be swapped back and forth between main memory and secondary storage. When a segment is swapped in, the operating system has to allocate enough contiguous free memory to hold

4307-465: The segment table, rather than pointing to a page table for the segment, contains the segment address in linear memory . When paging is enabled, addresses in linear memory are then mapped to physical addresses using a separate page table. Most operating systems did not use the segmentation capability, opting to keep the base address in all segment registers equal to 0 at all times and provide per-page memory protection and swapping using only paging. Some use

4380-507: The segment's page table. An implementation of virtual memory on a system using segmentation with paging usually only moves individual pages back and forth between main memory and secondary storage, similar to a paged non-segmented system. Pages of the segment can be located anywhere in main memory and need not be contiguous. This usually results in a reduced amount of input/output between primary and secondary storage and reduced memory fragmentation. The Burroughs Corporation B5000 computer

4453-474: The segmented architecture of the Z8000 was a disadvantage for emerging "graphics-based applications", where systems such as the Apple Macintosh needed to readily access more than 64 KB of memory in a single address space. The longer than anticipated process of bringing the product to market was also acknowledged as having contributed to its lack of adoption, Faggin noting that "being first and having

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4526-671: The sole operating mode of these x86 CPU models " real mode ". The Intel 80286 and later processors add "286 protected mode ", which retains 16-bit addressing, and adds segmentation (without paging) and per-segment memory protection. For backward compatibility, all x86 CPUs start up in "real mode", with the same fixed overlapping 64 KiB segments, no memory protection, only 1 MiB physical address space, and some subtle differences ( high memory area , unreal mode ). In order to use its full 24-bit (16 MiB) physical address space and advanced MMU features, an 80286 or later processor must be switched into "protected mode" by software, usually

4599-408: The source or destination being an "access descriptor" for an object, and an offset into the object, with the access descriptor being in a 32-bit register and with the offset computed from a base offset in the next register and from an additional offset and, optionally, an index register specified in the instruction. An access descriptor contains permission bits and a 26-bit object index; the object index

4672-448: The stack registers point to the system stack and all privileged instructions are available. In user mode, the stack registers point to the normal stack and all privileged instructions will generate a fault. Having separate modes and stacks greatly adds to the performance of context switches between user programs and an operating system . Like the Z80, the Z8000 includes a system to automatically refresh dynamic RAM . In most systems this

4745-498: The strongest marketing and the strongest momentum", as Intel had found itself with the 8086, would have been the only remaining route to success for a product of this kind. An examination of the choices available to designers in the early 1980s suggests there are several prosaic reasons the Z8000 was not more popular: Comparing assembly language versions of the Byte Sieve , one sees that the 5.5 MHz Z8000's 1.1 seconds

4818-470: The system as 16-bit, or "16/32". Such solutions have a long history in the computer field, with various designs performing math even one bit at a time, known as "serial arithmetic", while most designs by the 1970s processed at least a few bits at a time. A common example is the Data General Nova, which was a 16-bit design that performed 16-bit math as a series of four 4-bit operations. 4-bits was

4891-547: The uppermost bit set in the word. They reside in either the Program Reference Table (PRT) or the stack, and contain a presence bit indicating whether the data are present in memory. There are distinct data and program descriptors. Words in the B6500 and its successors have 48 bits of data and 3 tag bits. The tag bits indicate the type of data contained in the word; there are several descriptor types, indicated by different tag bit values. The line includes

4964-537: The word size of a widely available single-chip ALU and thus allowed for inexpensive implementation. Using the definition being applied to the 68000, the Nova would be a 4-bit computer, or 4/16. Not long after the introduction of the Nova, a second version was introduced, the SuperNova, which included four of the 4-bit ALUs running in parallel to perform math 16 bits at a time and therefore offer higher performance. This

5037-401: Was due to Zilog's financing arrangement with Exxon 's venture capital arm, Exxon Enterprises. Enterprises had made a number of investments in the computer field, and by the early 1980s was positioning itself as a competitor to IBM in the large system space. Faggin suggested that IBM thus saw Zilog as a competitor, and refused to consider the Z8000 as a result. However, Faggin did concede that

5110-413: Was intended to increase reliability of the systems running multiple processes simultaneously. In a system using segmentation, computer memory addresses consist of a segment id and an offset within the segment. A hardware memory management unit (MMU) is responsible for translating the segment and offset into a physical address , and for performing checks to make sure the translation can be done and that

5183-408: Was invisible to the user and the programs, which always used 16-bit instructions and data. In a similar fashion, later 68000-family members, starting with the Motorola 68020 , had 32-bit ALUs. One may also see references to systems being, or not being, 16-bit based on some other measure. One common one is when the address space is not the same size of bits as the internal registers. Most 8-bit CPUs of

5256-444: Was one of the first to implement segmentation, and "perhaps the first commercial computer to provide virtual memory" based on segmentation. The B5000 is equipped with a segment information table called the Program Reference Table (PRT) which is used to indicate whether the corresponding segment resides in the main memory, to maintain the base address and the size of the segment. The later B6500 computer also implemented segmentation;

5329-584: Was typical for servers of the time. Z8000-based computer systems included Zilog's own System 8000 series, as well as other manufacturers: The Zilog S8000 computer came out with a version of Unix called ZEUS (Zilog Enhanced Unix System). ZEUS was a port of Unix Version 7 and included what were referred to as 'the Berkeley Enhancements'. ZEUS included a version of COBOL called RM/COBOL (Ryan McFarland COBOL). The availability of RM/COBOL allowed many commercial applications to be quickly ported to

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