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73-593: By the time the project had delivered its first implementation, new processors like the Sun SPARC and Intel 486 had surpassed its performance, and development was abandoned in 1988. The Rekursiv project started as an effort to improve the assembly line controls in Linn's factories in Glasgow , Scotland . Their lines were automated using a suite of VAX-11 systems, but these were slow and very difficult to program with

146-406: A & ( ∼ a + 1 ) {\displaystyle a\And (\sim a+1)} , where & {\displaystyle \And } means bitwise operation AND and ∼ {\displaystyle \sim } means bitwise operation NOT on a {\displaystyle a} . For MSb 1 numbering, the value of an unsigned binary integer

219-478: A register–register architecture ); except for the load/store instructions used to access memory , all instructions operate on the registers, in accordance with the RISC design principles. A SPARC processor includes an integer unit (IU) that performs integer load, store, and arithmetic operations. It may include a floating-point unit (FPU) that performs floating-point operations and, for SPARC V8, may include

292-492: A 40-bit identifier which the Objekt chip hashed and used as a pointer to physical memory. Objekt also handled the mapping of the object memory to hard disk for permanent storage, implementing a virtual memory system. To handle garbage collection , Objekt divided the provided dynamic RAM (main memory) into two halves, using one for new object creation and leaving the other unused. When a new object would require more memory than

365-411: A 64-bit result, SDIVX , which divides a 64-bit signed dividend by a 64-bit signed divisor and produces a 64-bit signed quotient, and UDIVX , which divides a 64-bit unsigned dividend by a 64-bit unsigned divisor and produces a 64-bit signed quotient; none of those instructions use the Y register. Conditional branches test condition codes in a status register , as seen in many instruction sets such

438-685: A Rekursiv computer ended up at the bottom of the Forth and Clyde canal in Glasgow. According to a post by a researcher at the University of Strathclyde, while the Rekursiv system was being developed, a new version of the LINGO language was written for the Sun SPARC system which emerged at about this time. It ran twice as fast as the Rekursiv hardware, rendering the effort pointless. Sometime after that

511-415: A co-processor (CP) that performs co-processor-specific operations; the architecture does not specify what functions a co-processor would perform, other than load and store operations. The SPARC architecture has an overlapping register window scheme. At any instant, 32 general-purpose registers are visible. A Current Window Pointer ( CWP ) variable in the hardware points to the current set. The total size of

584-591: A new specification, Oracle SPARC Architecture 2011 , which besides the overall update of the reference, adds the VIS 3 instruction set extensions and hyperprivileged mode to the 2007 specification. In October 2015, Oracle released SPARC M7, the first processor based on the new Oracle SPARC Architecture 2015 specification. This revision includes VIS 4 instruction set extensions and hardware-assisted encryption and silicon secured memory (SSM). SPARC architecture has provided continuous application binary compatibility from

657-528: A number of improvements that were part of the SuperSPARC series of processors released in 1992. SPARC V9, released in 1993, introduced a 64-bit architecture and was first released in Sun's UltraSPARC processors in 1995. Later, SPARC processors were used in symmetric multiprocessing (SMP) and non-uniform memory access ( CC-NUMA ) servers produced by Sun, Solbourne , and Fujitsu , among others. The design

730-401: A plus sign separating the operands, instead of using a comma-separated list. Examples: Due to the widespread use of non-32-bit data, such as 16-bit or 8-bit integral data or 8-bit bytes in strings, there are instructions that load and store 16-bit half-words and 8-bit bytes, as well as instructions that load 32-bit words. During a load, those instructions will read only the byte or half-word at

803-451: A quad-aligned group of four floating-point registers can hold one quad-precision IEEE 754 floating-point number. A SPARC V9 processor with an FPU includes: The registers are organized as a set of 64 32-bit registers, with the first 32 being used as the 32-bit floating-point registers, even–odd pairs of all 64 registers being used as the 64-bit floating-point registers, and quad-aligned groups of four floating-point registers being used as

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876-628: A rate of almost one instruction per clock cycle . This made them similar to the MIPS architecture in many ways, including the lack of instructions such as multiply or divide. Another feature of SPARC influenced by this early RISC movement is the branch delay slot . The SPARC processor usually contains as many as 160 general-purpose registers . According to the "Oracle SPARC Architecture 2015" specification an "implementation may contain from 72 to 640 general-purpose 64-bit" registers. At any point, only 32 of them are immediately visible to software — 8 are

949-423: A register holds the value 10 and then branch to code that handles it, one would: In a conditional branch instruction, the icc or fcc field specifies the condition being tested. The 22-bit displacement field is the address, relative to the current PC, of the target, in words, so that conditional branches can go forward or backward up to 8 megabytes. The ANNUL (A) bit is used to get rid of some delay slots. If it

1022-523: A register or a 13-bit signed integer constant; the other operands are registers. Any of the register operands may point to G0; pointing the result to G0 discards the results, which can be used for tests. Examples include: The list of mathematical instructions is ADD , SUB , AND , OR , XOR , and negated versions ANDN , ORN , and XNOR . One quirk of the SPARC design is that most arithmetic instructions come in pairs, with one version setting

1095-456: A series of pointers to the memory locations holding the values. In Rekursiv, the addresses are replaced by 40-bit object IDs pointing to a section of memory allocated by Objekt. The most significant bit (MSB) of the 40-bit pointer was set to 1 if the value was an object identifier, or 0 if it was an untyped binary value. The later was used to store large unformatted data, like the data for a digital image, and could only be used within objects. In

1168-498: A set of global registers (one of which, g0 , is hard-wired to zero, so only seven of them are usable as registers) and the other 24 are from the stack of registers. These 24 registers form what is called a register window , and at function call/return, this window is moved up and down the register stack. Each window has eight local registers and shares eight registers with each of the adjacent windows. The shared registers are used for passing function parameters and returning values, and

1241-560: A year later for their mainframe and end-of-support in 2034 "to promote customer modernization". The SPARC architecture was heavily influenced by the earlier RISC designs, including the RISC I and II from the University of California, Berkeley and the IBM 801 . These original RISC designs were minimalist, including as few features or op-codes as possible and aiming to execute instructions at

1314-725: Is 0 in a conditional branch, the delay slot is executed as usual. If it is 1, the delay slot is only executed if the branch is taken. If it is not taken, the instruction following the conditional branch is skipped. There are a wide variety of conditional branches: BA (branch always, essentially a jmp), BN (branch never), BE (equals), BNE (not equals), BL (less than), BLE (less or equal), BLEU (less or equal, unsigned), BG (greater), BGE (greater or equal), BGU (greater unsigned), BPOS (positive), BNEG (negative), BCC (carry clear), BCS (carry set), BVC (overflow clear), BVS (overflow set). The FPU and CP have sets of condition codes separate from

1387-437: Is a property of the numeric value in binary itself. This is often utilized in programming via bit shifting : A value of 1 << n corresponds to the n bit of a binary integer (with a value of 2 ). In digital steganography , sensitive messages may be concealed by manipulating and storing information in the least significant bits of an image or a sound file. The user may later recover this information by extracting

1460-437: Is created by adding the two address operands to produce an address. The second address operand may be a constant or a register. Loads take the value at the address and place it in the register specified by the third operand, whereas stores take the value in the register specified by the first operand and place it at the address. To make this more obvious, the assembler language indicates address operands using square brackets with

1533-593: Is fully open, non-proprietary and royalty-free. As of 2024, the latest commercial high-end SPARC processors are Fujitsu 's SPARC64 XII (introduced in September 2017 for its SPARC M12 server) and Oracle 's SPARC M8 introduced in September 2017 for its high-end servers. On September 1, 2017, after a round of layoffs that started in Oracle Labs in November 2016, Oracle terminated SPARC design after completing

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1606-490: The LD instruction, renamed LDUW , clears the upper 32 bits in the register and loads the 32-bit value into the lower 32 bits, and the ST instruction, renamed STW , discards the upper 32 bits of the register and stores only the lower 32 bits. The new LDSW instruction sets the upper bits in the register to the value of the uppermost bit of the word and loads the 32-bit value into

1679-511: The IBM System/360 architecture and successors and the x86 architecture. This means that a test and branch is normally performed with two instructions; the first is an ALU instruction that sets the condition codes, followed by a branch instruction that examines one of those flags. The SPARC does not have specialized test instructions; tests are performed using normal ALU instructions with the destination set to %G0. For instance, to test if

1752-691: The UltraSPARC T1 implementation: In 2007, Sun released an updated specification, UltraSPARC Architecture 2007 , to which the UltraSPARC T2 implementation complied. In December 2007, Sun also made the UltraSPARC T2 processor's RTL available via the OpenSPARC project. It was also released under the GNU General public license v2. OpenSPARC T2 is 8 cores, 16 pipelines with 64 threads. In August 2012, Oracle Corporation made available

1825-404: The least significant bit ( LSb ) is the bit position in a binary integer representing the binary 1s place of the integer. Similarly, the most significant bit ( MSb ) represents the highest-order place of the binary integer. The LSb is sometimes referred to as the low-order bit or right-most bit , due to the convention in positional notation of writing less significant digits further to

1898-400: The two's complement method. The MSb most significant bit has a negative weight in signed integers, in this case -2 = -128. The other bits have positive weights. The lsb ( least significant bit ) has weight 2 =1. The signed value is in this case -128+2 = -126. The expressions most significant bit first and least significant bit at last are indications on the ordering of the sequence of

1971-401: The 128-bit floating-point registers. Floating-point registers are not windowed; they are all global registers. All SPARC instructions occupy a full 32-bit word and start on a word boundary. Four formats are used, distinguished by the first two bits. All arithmetic and logical instructions have 2 source operands and 1 destination operand. RD is the "destination register", where the output of

2044-611: The M8. Much of the processor core development group in Austin, Texas, was dismissed, as were the teams in Santa Clara, California, and Burlington, Massachusetts. Fujitsu will also discontinue their SPARC production (has already shifted to producing their own ARM -based CPUs), after two "enhanced" versions of Fujitsu's older SPARC M12 server in 2020–22 (formerly planned for 2021) and again in 2026–27, end-of-sale in 2029, of UNIX servers and

2117-650: The NAM. Simulations suggested that Lisp routines written using this style operated about 20 times faster than a Symbolics Lisp machine . The company also produced similar microcode systems for Smalltalk and Prolog, the later reducing Prolog's complex unification operation to a single opcode. The Rekursiv processor consisted of four gate-array chips named Numerik ( 32-bit ALU ), Logik (instruction sequencer), Objekt (object-oriented memory management unit ) and Klock (processor clock and support logic). The original versions were clocked at 10 MHz. Linn intended to sell

2190-453: The NZVC condition code bits in the status register , and the other not setting them, with the default being not to set the codes. This is so that the compiler has a way to move instructions around when trying to fill delay slots. If one wants the condition codes to be set, this is indicated by adding cc to the instruction: add and sub also have another modifier, X, which indicates whether

2263-635: The RESTORE instruction (switching back to the call before returning from the procedure). Trap events ( interrupts , exceptions or TRAP instructions) and RETT instructions (returning from traps) also change the CWP . For SPARC V9, CWP register is decremented during a RESTORE instruction, and incremented during a SAVE instruction. This is the opposite of PSR.CWP's behavior in SPARC V8. This change has no effect on nonprivileged instructions. SPARC registers are shown in

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2336-426: The Rekursiv chip set to vendors, as well as produce their own workstation using it. Initially, the only product was "HADES", the "Hardware Accelerator for Dynamic Expert Systems", which consisted of a VMEbus card that could be plugged into a Sun-3 or Sun-4 workstation. HADES included the four main chips, 2 MB of 45 nanosecond (22 MHz) SRAM and 5 MB of 100 ns (10 MHz) DRAM. Disk access

2409-528: The UltraSPARC IV by Sun and the SPARC64 VI by Fujitsu. In early 2006, Sun released an extended architecture specification, UltraSPARC Architecture 2005 . This includes not only the non-privileged and most of the privileged portions of SPARC V9, but also all the architectural extensions developed through the processor generations of UltraSPARC III, IV, and IV+, as well as CMT extensions starting with

2482-468: The VAX platform. Tiefenbrun concluded the solution to the performance issue was not to improve the language on the VAX but instead produce an entirely new CPU dedicated specifically to running object programs. In 1984, Tiefenbrun formed the wholly owned subsidiary Linn Smart Computing under the direction of University of Strathclyde professor David Harland and the Rekursiv project was born. The first version of

2555-415: The application instruction ( load–store ) level or at the memory page level (via an MMU setting). The latter is often used for accessing data from inherently little-endian devices, such as those on PCI buses. There have been three major revisions of the architecture. The first published version was the 32-bit SPARC version 7 (V7) in 1986. SPARC version 8 (V8), an enhanced SPARC architecture definition,

2628-516: The bit number and a base of 2. The value of an unsigned binary integer is therefore where b i denotes the value of the bit with number i , and N denotes the number of bits in total. When the bit numbering starts at zero for the most significant bit (MSb) the numbering scheme is called MSb 0 . The value of an unsigned binary integer is therefore LSb of a number can be calculated with time complexity of O ( n ) {\displaystyle O(n)} with formula

2701-433: The bits in the bytes sent over a wire in a serial transmission protocol or in a stream (e.g. an audio stream). Most significant bit first means that the most significant bit will arrive first: hence e.g. the hexadecimal number 0x12 , 00010010 in binary representation, will arrive as the sequence 0 0 0 1 0 0 1 0 . Least significant bit first means that the least significant bit will arrive first: hence e.g.

2774-451: The bottom two bits of both operands are 0 and reporting overflow if they are not. This can be useful in the implementation of the run time for ML , Lisp , and similar languages that might use a tagged integer format. The endianness of the 32-bit SPARC V8 architecture is purely big-endian. The 64-bit SPARC V9 architecture uses big-endian instructions, but can access data in either big-endian or little-endian byte order, chosen either at

2847-469: The case of a full object, a further simplification was available to store short fields as values within the pointer itself. This was indicated by setting the second MSB to 0 as well. In this case, the following five bits indicated a type, defined by the program's ISA, which might be "integer" or "string fragment". The actual value of this "compact object" was placed in the lower 32-bits of the pointer. This allowed such simple values to be immediately presented to

2920-467: The company was shut down. The underlying concept of the Rekursiv platform was to provide a hardware-assisted persistent object store, constantly and invisibly writing the memory state to disk without intervention from the operating system or the user's program. One reviewer described it as "an object-database engine for creating and managing persistent objects". To make such a system work with reasonable performance while running complex programs, Rekursiv

2993-455: The completion of memory references. For example, all effects of the stores that appear prior to the MEMBAR instruction must be made visible to all processors before any loads following the MEMBAR can be executed. Arithmetic and logical instructions also use a three-operand format, with the first two being the operands and the last being the location to store the result. The middle operand can be

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3066-522: The condition codes and versions that do. MULSCC and the multiply instructions use the Y register to hold the upper 32 bits of the product; the divide instructions use it to hold the upper 32 bits of the dividend. The RDY instruction reads the value of the Y register into a general-purpose register; the WRY instruction writes the value of a general-purpose register to the Y register. SPARC V9 added MULX , which multiplies two 64-bit values and produces

3139-419: The entire system image was periodically written to disk, during which time all of the pointers were re-numbered to be consecutive. The processor's instruction set was stored in a dedicated area of static RAM known as the "control store". It was accessed via a dedicated 16-bit bus, organized as 16,384 words of 128-bits each. A separate "control store map" section of SRAM holds a numbered table of entry points into

3212-410: The figure above. There is also a non-windowed Y register, used by the multiply-step, integer multiply, and integer divide instructions. A SPARC V8 processor with an FPU includes 32 32-bit floating-point registers, each of which can hold one single-precision IEEE 754 floating-point number. An even–odd pair of floating-point registers can hold one double-precision IEEE 754 floating-point number, and

3285-552: The first SPARC V7 implementation in 1987 through the Sun UltraSPARC Architecture implementations. Among various implementations of SPARC, Sun's SuperSPARC and UltraSPARC-I were very popular, and were used as reference systems for SPEC CPU95 and CPU2000 benchmarks. The 296 MHz UltraSPARC-II is the reference system for the SPEC CPU2006 benchmark. SPARC is a load–store architecture (also known as

3358-461: The flexibility that Linn's founder, Ivor Tiefenbrun , desired. By the early 1980s, Tiefenbrun had become convinced that object-oriented programming would offer solutions to these problems. In 1981, Tiefenbrun hired a number of programmers to write a version of the Smalltalk language for the VAX systems, borrowing some syntax from ALGOL . Known as LINGO, the system worked but ran very slowly on

3431-424: The indicated location and then either fill the rest of the target register with zeros (unsigned load) or with the value of the uppermost bit of the byte or half-word (signed load). During a store, those instructions discard the upper bits in the register and store only the lower bits. There are also instructions for loading double-precision values used for floating-point arithmetic , reading or writing eight bytes from

3504-470: The indicated register and the "next" one, so if the destination of a load is L1, L1 and L2 will be set. The complete list of load and store instructions for the general-purpose registers in 32-bit SPARC is LD , ST , LDUB (unsigned byte), LDSB (signed byte), LDUH (unsigned half-word), LDSH (signed half-word), LDD (load double), STB (store byte), STH (store half-word), STD (store double). In SPARC V9, registers are 64-bit, and

3577-495: The integer condition codes and from each other; two additional sets of branch instructions were defined to test those condition codes. Adding an F to the front of the branch instruction in the list above performs the test against the FPU's condition codes, while, in SPARC V8, adding a C tests the flags in the otherwise undefined CP. The CALL (jump to subroutine) instruction uses a 30-bit program counter -relative word offset. As

3650-450: The last two bits illustrates the least significant bits changed in the binary representation. This table illustrates an example of decimal value of 149 and the location of LSb. In this particular example, the position of unit value (decimal 1 or 0) is located in bit position 0 (n = 0). MSb stands for most significant bit , while LSb stands for least significant bit . This table illustrates an example of an 8 bit signed decimal value using

3723-443: The least significant bits of the manipulated pixels to recover the original message. This allows the storage or transfer of digital information to remain concealed. [REDACTED] A diagram showing how manipulating the least significant bits of a color can have a very subtle and generally unnoticeable affect on the color. In this diagram, green is represented by its RGB value, both in decimal and in binary. The red box surrounding

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3796-405: The local registers are used for retaining local values across function calls. The "scalable" in SPARC comes from the fact that the SPARC specification allows implementations to scale from embedded processors up through large server processors, all sharing the same core (non-privileged) instruction set. One of the architectural parameters that can scale is the number of implemented register windows;

3869-722: The lower bits. The new LDX instruction loads a 64-bit value into the register, and the STX instruction stores all 64 bits of the register. The LDF , LDDF , and LDQF instructions load a single-precision, double-precision, or quad-precision value from memory into a floating-point register; the STF , STDF , and STQF instructions store a single-precision, double-precision, or quad-precision floating-point register into memory. The memory barrier instruction, MEMBAR, serves two interrelated purposes: it articulates order constraints among memory references and facilitates explicit control over

3942-468: The microcoded routines, mapping a 10-bit opcode onto one of 2,048 entities. In a conventional processor, the map would normally be implemented in hardwired logic in the opcode decoder. Opcodes could be parts of objects and stored in the same way that any other data would be using Objekt. For performance reasons, a separate memory bank known as NAM (and NAMARG) reserved 524,288 40-bit words storing 10-bit opcodes and 30-bit arguments. NAM connected directly to

4015-443: The operation is deposited. The majority of SPARC instructions have at least this register, so it is placed near the "front" of the instruction format. RS1 and RS2 are the "source registers", which may or may not be present, or replaced by a constant. Load and store instructions have a three-operand format, in that they have two operands representing values for the address and one operand for the register to read or write to. The address

4088-530: The operation should set the carry bit: SPARC V7 does not have multiplication or division instructions, but it does have MULSCC , which does one step of a multiplication testing one bit and conditionally adding the multiplicand to the product. This was because MULSCC can complete over one clock cycle in keeping with the RISC philosophy. SPARC V8 added UMUL (unsigned multiply), SMUL (signed multiply), UDIV (unsigned divide), and SDIV (signed divide) instructions, with both versions that do not update

4161-409: The processor via its own bus, making it act more like a cache in modern architectures. In practice, the developer of a programming language would first outline the assembler language they desired, which would be the underlying syntax of the language with up to 2,048 instructions. Commonly used routines, like those found in stdlib in C, would then be coded using that assembler language and written to

4234-445: The processor without the need to follow a pointer to the physical location, which saved memory and improved performance. Because the top two bits of the 40-bit pointer were used for status flags, Objekt could only identify 2 objects in total. Since the objects were constantly being garbage collected, many of these values might point to non-existent objects, meaning the system could run out of identifiers in practical use. To address this,

4307-584: The register file is not part of the architecture, allowing more registers to be added as the technology improves, up to a maximum of 32 windows in SPARC V7 and V8 as CWP is 5 bits and is part of the PSR register. In SPARC V7 and V8 CWP will usually be decremented by the SAVE instruction (used by the SAVE instruction during the procedure call to open a new stack frame and switch the register window), or incremented by

4380-477: The right. The MSb is similarly referred to as the high-order bit or left-most bit . In both cases, the LSb and MSb correlate directly to the least significant digit and most significant digit of a decimal integer. Bit indexing correlates to the positional notation of the value in base 2. For this reason, bit index is not affected by how the value is stored on the device, such as the value's byte order . Rather, it

4453-414: The same hexadecimal number 0x12 , again 00010010 in binary representation, will arrive as the (reversed) sequence 0 1 0 0 1 0 0 0 . When the bit numbering starts at zero for the least significant bit (LSb) the numbering scheme is called LSb 0 . This bit numbering method has the advantage that for any unsigned number the value of the number can be calculated by using exponentiation with

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4526-562: The specification allows from three to 32 windows to be implemented, so the implementation can choose to implement all 32 to provide maximum call stack efficiency, or to implement only three to reduce cost and complexity of the design, or to implement some number between them. Other architectures that include similar register file features include Intel i960 , IA-64 , and AMD 29000 . The architecture has gone through several revisions. It gained hardware multiply and divide functionality in version 8. 64-bit (addressing and data) were added to

4599-467: The system emerged in 1988. A small number of prototype VMEbus boards, called Hades , comprising these four chips plus 80 MB of RAM were produced. These were intended for installation in a host system such as a Sun-3 workstation . Although the Rekursiv was never fully developed and was not a commercial success, several Hades boards were used in academic research projects in the UK . The last known copy of

4672-410: The target address is specifying the start of a word, not a byte, 30-bits is all that is needed to reach any address in the 4 gigabyte address space. The CALL instruction deposits the return address in register R15, also known as output register O7. Most significant bit In computing , bit numbering is the convention used to identify the bit positions in a binary number . In computing ,

4745-767: The version 9 SPARC specification published in 1994. In SPARC version 8, the floating-point register file has 16 double-precision registers. Each of them can be used as two single-precision registers, providing a total of 32 single-precision registers. An odd–even number pair of double-precision registers can be used as a quad-precision register, thus allowing 8 quad-precision registers. SPARC Version 9 added 16 more double-precision registers (which can also be accessed as 8 quad-precision registers), but these additional registers can not be accessed as single-precision registers. No SPARC CPU implements quad-precision operations in hardware as of 2024. Tagged add and subtract instructions perform adds and subtracts on values checking that

4818-421: Was designed to allow the programmer to write their own instruction set architecture (ISA) dedicated to the language they were using. The microcode instruction set was stored in static RAM . There was no default ISA, although Linn supplied one for running programs in the C programming language . The system did not provide the analog of a memory address to the programs running on it, instead, objects were given

4891-480: Was free in the used portion, Objekt paused the system, copied any object with a valid pointer to it to the unused half of memory, and then switched to make the formerly unused half the active portion. In extremely memory-limited cases, Objekt would first attempt to spool some objects to disk, and if that failed to free up enough room, would use both halves of memory. Objects are composite structures with multiple values within them, which in most systems are implemented as

4964-459: Was handled by a program running on the underlying Sun system, which significantly hampered performance. Sun SPARC SPARC ( Scalable Processor ARChitecture ) is a reduced instruction set computer (RISC) instruction set architecture originally developed by Sun Microsystems . Its design was strongly influenced by the experimental Berkeley RISC system developed in the early 1980s. First developed in 1986 and released in 1987, SPARC

5037-481: Was one of the most successful early commercial RISC systems, and its success led to the introduction of similar RISC designs from many vendors through the 1980s and 1990s. The first implementation of the original 32-bit architecture (SPARC V7) was used in Sun's Sun-4 computer workstation and server systems, replacing their earlier Sun-3 systems based on the Motorola 68000 series of processors. SPARC V8 added

5110-629: Was released by Fujitsu and Sun, describing processor functions which were identically implemented in the CPUs of both companies ("Commonality"). The first CPUs conforming to JPS1 were the UltraSPARC III by Sun and the SPARC64 V by Fujitsu. Functionalities which are not covered by JPS1 are documented for each processor in "Implementation Supplements". At the end of 2003, JPS2 was released to support multicore CPUs. The first CPUs conforming to JPS2 were

5183-587: Was released by SPARC International in 1993. It was developed by the SPARC Architecture Committee consisting of Amdahl Corporation , Fujitsu , ICL , LSI Logic , Matsushita , Philips , Ross Technology , Sun Microsystems , and Texas Instruments . Newer specifications always remain compliant with the full SPARC V9 Level 1 specification. In 2002, the SPARC Joint Programming Specification 1 (JPS1)

5256-412: Was released in 1990. The main differences between V7 and V8 were the addition of integer multiply and divide instructions, and an upgrade from 80-bit "extended-precision" floating-point arithmetic to 128-bit " quad-precision " arithmetic. SPARC V8 served as the basis for IEEE Standard 1754-1994, an IEEE standard for a 32-bit microprocessor architecture. SPARC version 9 , the 64-bit SPARC architecture,

5329-694: Was turned over to the SPARC International trade group in 1989, and since then its architecture has been developed by its members. SPARC International is also responsible for licensing and promoting the SPARC architecture, managing SPARC trademarks (including SPARC, which it owns), and providing conformance testing . SPARC International was intended to grow the SPARC architecture to create a larger ecosystem; SPARC has been licensed to several manufacturers, including Atmel , Bipolar Integrated Technology , Cypress Semiconductor , Fujitsu , Matsushita and Texas Instruments . Due to SPARC International, SPARC

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