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46-470: The APIC is a split architecture design, with a local component (LAPIC) usually integrated into the processor itself, and an optional I/O APIC on a system bus. The first APIC was the 82489DX – it was a discrete chip that functioned both as local and I/O APIC. The 82489DX enabled construction of symmetric multiprocessor (SMP) systems with the Intel 486 and early Pentium processors; for example,

92-429: A multiprocessor computer hardware and software architecture where two or more identical processors are connected to a single, shared main memory , have full access to all input and output devices, and are controlled by a single operating system instance that treats all processors equally, reserving none for special purposes. Most multiprocessor systems today use an SMP architecture. In the case of multi-core processors ,

138-432: A NUMA architecture, processors may access local memory quickly and remote memory more slowly. This can dramatically improve memory throughput as long as the data are localized to specific processes (and thus processors). On the downside, NUMA makes the cost of moving data from one processor to another, as in workload balancing, more expensive. The benefits of NUMA are limited to particular workloads, notably on servers where

184-610: A cause of system failure when the operating system does not support it properly. On older operating systems, the I/O and local APICs often had to be disabled. While this is not possible anymore due to the prevalence of symmetric multiprocessor and multi-core systems, the bugs in the firmware and the operating systems are now a rare occurrence. AMD and Cyrix once proposed a somewhat similar-in-purpose OpenPIC architecture supporting up to 32 processors; it had at least declarative support from IBM and Compaq around 1995. No x86 motherboard

230-547: A discrete chip or integrated in a CPU, has a version register containing a four-bit version number for its specific APIC implementation. For example, the 82489DX has an APIC version number of 0, while version 1 was assigned to the first generation of local APICs integrated in the Pentium 90 and 100 processors. In systems containing an 8259 PIC , the 8259 may be connected to the LAPIC in the system's bootstrap processor (BSP), one of

276-514: A few limits on the scalability of SMP due to cache coherence and shared objects. Uniprocessor and SMP systems require different programming methods to achieve maximum performance. Programs running on SMP systems may experience an increase in performance even when they have been written for uniprocessor systems. This is because hardware interrupts usually suspends program execution while the kernel that handles them can execute on an idle processor instead. The effect in most applications (e.g. games)

322-580: A pool of homogeneous processors running independently of each other. Each processor, executing different programs and working on different sets of data, has the capability of sharing common resources (memory, I/O device, interrupt system and so on) that are connected using a system bus or a crossbar . SMP systems have centralized shared memory called main memory (MM) operating under a single operating system with two or more homogeneous processors. Usually each processor has an associated private high-speed memory known as cache memory (or cache) to speed up

368-576: A quad-core device, called the Companion core, built specifically for executing tasks at a lower frequency during mobile active standby mode, video playback, and music playback. Project Kal-El ( Tegra 3 ), patented by NVIDIA, was the first SoC (System on Chip) to implement this new vSMP technology. This technology not only reduces mobile power consumption during active standby state, but also maximizes quad core performance during active usage for intensive mobile applications. Overall this technology addresses

414-409: A similar technology called AVIC , it is available family 15h models 6Xh (Carrizo) processors and newer. There are a number of known bugs in implementations of APIC systems, especially with concern to how the 8254 is connected. Defective BIOSes may not set up interrupt routing properly, or provide incorrect ACPI tables and Intel MultiProcessor Specification (MPS) tables. The APIC can also be

460-463: A small write-through cache connected to a common memory to form a shared memory system. Another early commercial Unix SMP implementation was the NUMA based Honeywell Information Systems Italy XPS-100 designed by Dan Gielan of VAST Corporation in 1985. Its design supported up to 14 processors, but due to electrical limitations, the largest marketed version was a dual processor system. The operating system

506-678: A system with more than one process running can run different processes on different processors. On personal computers , SMP is less useful for applications that have not been modified. If the system rarely runs more than one process at a time, SMP is useful only for applications that have been modified for multithreaded (multitasked) processing. Custom-programmed software can be written or modified to use multiple threads, so that it can make use of multiple processors. Multithreaded programs can also be used in time-sharing and server systems that support multithreading, allowing them to make more use of multiple processors. In current SMP systems, all of

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552-409: A uniprocessor system, because different programs can run on different CPUs simultaneously. Conversely, asymmetric multiprocessing (AMP) usually allows only one processor to run a program or task at a time. For example, AMP can be used in assigning specific tasks to CPU based to priority and importance of task completion. AMP was created well before SMP in terms of handling multiple CPUs, which explains

598-436: A uniprocessor system. SMP systems can also lead to more complexity regarding instruction sets. A homogeneous processor system typically requires extra registers for "special instructions" such as SIMD (MMX, SSE, etc.), while a heterogeneous system can implement different types of hardware for different instructions/uses. When more than one program executes at the same time, an SMP system has considerably better performance than

644-498: Is exposed from QEMU going back to Conroe and even for AMD Opteron G-series processors (neither of which natively support x2APIC). APICv is Intel's brand name for hardware virtualization support aimed at reducing interrupt overhead in guests. APICv was introduced in the Ivy Bridge-EP processor series, which is sold as Xeon E5-26xx v2 (launched in late 2013) and as Xeon E5-46xx v2 (launched in early 2014). AMD announced

690-399: Is handled independently, this creates an embarrassingly parallel situation across the entire multi-compilation-unit project, allowing near linear scaling of compilation time. Distributed computing projects are inherently parallel by design.) Systems programmers must build support for SMP into the operating system , otherwise, the additional processors remain idle and the system functions as

736-407: Is intended by SMP is a shared memory multiprocessor where the cost of accessing a memory location is the same for all processors; that is, it has uniform access costs when the access actually is to memory. If the location is cached, the access will be faster, but cache access times and memory access times are the same on all processors." SMP systems are tightly coupled multiprocessor systems with

782-411: Is not so much a performance increase as the appearance that the program is running much more smoothly. Some applications, particularly building software and some distributed computing projects, run faster by a factor of (nearly) the number of additional processors. (Compilers by themselves are single threaded, but, when building a software project with multiple compilation units, if each compilation unit

828-501: Is one LAPIC in each CPU in the system. In the very first implementation ( 82489DX ), the LAPIC was a discrete circuit, as opposed to its later implementation in Intel processors' silicon. There is typically one I/O APIC for each peripheral bus in the system. In original system designs, LAPICs and I/O APICs were connected by a dedicated APIC bus. Newer systems use the system bus for communication between all APIC components. Each APIC, whether

874-503: Is serialized; this and cache coherency issues cause performance to lag slightly behind the number of additional processors in the system. SMP uses a single shared system bus that represents one of the earliest styles of multiprocessor machine architectures, typically used for building smaller computers with up to 8 processors. Larger computer systems might use newer architectures such as NUMA (Non-Uniform Memory Access), which dedicates different memory banks to different processors. In

920-724: The Michigan Terminal System (MTS), used both CPUs. Both processors could access data channels and initiate I/O. In OS/360 M65MP, peripherals could generally be attached to either processor since the operating system kernel ran on both processors (though with a "big lock" around the I/O handler). The MTS supervisor (UMMPS) has the ability to run on both CPUs of the IBM System/360 model 67–2. Supervisor locks were small and used to protect individual common data structures that might be accessed simultaneously from either CPU. Other mainframes that supported SMP included

966-565: The UNIVAC 1108 II , released in 1965, which supported up to three CPUs, and the GE-635 and GE-645 , although GECOS on multiprocessor GE-635 systems ran in a master-slave asymmetric fashion, unlike Multics on multiprocessor GE-645 systems, which ran in a symmetric fashion. Starting with its version 7.0 (1972), Digital Equipment Corporation 's operating system TOPS-10 implemented the SMP feature,

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1012-549: The APIC timer is not a shareable resource. The aperiodic interrupts offered by the APIC timer are used by the Linux kernel tickless kernel feature. This optional but default feature is new with 2.6.18. When enabled on a computer with an APIC timer, the kernel does not use the 8253 programmable interval timer for timekeeping. A VMware document notes that "software does not have a reliable way to determine its frequency. Generally,

1058-500: The P5 microarchitecture ( P54C ) have a built-in local APIC. However, if the local APIC is disabled in a P5 processor, it cannot be re-enabled by software; this limitation no longer exists in the P6 processors and later ones. With the introduction of Pentium 4 HT and Pentium D , each CPU core and each CPU thread are have the integrated LAPIC. The Message Signaled Interrupts (MSI) feature of

1104-614: The PCI 2.2 and later specifications cannot be used without the local APIC being enabled. Use of MSI obviates the need for an I/O APIC. Additionally, up to 224 interrupts are supported in MSI mode, and IRQ sharing is not allowed. Another advantage of the local APIC is that it also provides a high-resolution (on the order of one microsecond or better) timer that can be used in both interval and one-off mode. The APIC timer had its initial acceptance woes. A Microsoft document from 2002 (which advocated for

1150-407: The Pentium processors. The 82489DX had 16 interrupt lines; it also had a quirk that it could lose some ISA interrupts. In a multiprocessor 486 system, each CPU had to be paired with its own 82489DX; additionally a supplementary 82489DX had to be used as I/O APIC. The 82489DX could not emulate the 8259A (XT-PIC) so these also had to be included as physical chips for backwards compatibility. The 82489DX

1196-402: The SMP architecture applies to the cores, treating them as separate processors. Professor John D. Kubiatowicz considers traditionally SMP systems to contain processors without caches. Culler and Pal-Singh in their 1998 book "Parallel Computer Architecture: A Hardware/Software Approach" mention: "The term SMP is widely used but causes a bit of confusion. [...] The more precise description of what

1242-437: The adoption of High Precision Event Timer instead) criticized the LAPIC timer for having "poor resolution" and stating that "the clocks silicon is sometimes very buggy". Nevertheless, the APIC timer is used for example by Windows 7 when profiling is enabled, and by Windows 8 in all circumstances. (Before Windows 8 claimed exclusive rights to this timer, it was also used by some programs like CPU-Z .) Under Microsoft Windows

1288-441: The data are often associated strongly with certain tasks or users. Finally, there is computer clustered multiprocessing (such as Beowulf ), in which not all memory is available to all processors. Clustering techniques are used fairly extensively to build very large supercomputers. Variable Symmetric Multiprocessing (vSMP) is a specific mobile use case technology initiated by NVIDIA. This technology includes an extra fifth core in

1334-495: The data for that task is located in memory, provided that each task in the system is not in execution on two or more processors at the same time. With proper operating system support, SMP systems can easily move tasks between processors to balance the workload efficiently. The earliest production system with multiple identical processors was the Burroughs B5000 , which was functional around 1961. However at run-time this

1380-736: The earliest system running SMP was the DECSystem 1077 dual KI10 processor system. Later KL10 system could aggregate up to 8 CPUs in a SMP manner. In contrast, DECs first multi-processor VAX system, the VAX-11/782, was asymmetric, but later VAX multiprocessor systems were SMP. Early commercial Unix SMP implementations included the Sequent Computer Systems Balance 8000 (released in 1984) and Balance 21000 (released in 1986). Both models were based on 10 MHz National Semiconductor NS32032 processors, each with

1426-510: The lack of performance based on the example provided. In cases where an SMP environment processes many jobs, administrators often experience a loss of hardware efficiency. Software programs have been developed to schedule jobs and other functions of the computer so that the processor utilization reaches its maximum potential. Good software packages can achieve this maximum potential by scheduling each CPU separately, as well as being able to integrate multiple SMP machines and clusters. Access to RAM

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1472-725: The latency even more, by a factor of nearly seven relative to the XT-PIC baseline. The xAPIC was introduced with the Pentium 4 , while the x2APIC is the most recent generation of the Intel's programmable interrupt controller, introduced with the Nehalem microarchitecture in November 2008. The major improvements of the x2APIC address the number of supported CPUs and performance of the interface. The x2APIC now uses 32 bits to address CPUs, allowing to address up to 2 − 1 CPUs using

1518-473: The main memory data access and to reduce the system bus traffic. Processors may be interconnected using buses, crossbar switches or on-chip mesh networks. The bottleneck in the scalability of SMP using buses or crossbar switches is the bandwidth and power consumption of the interconnect among the various processors, the memory, and the disk arrays. Mesh architectures avoid these bottlenecks, and provide nearly linear scalability to much higher processor counts at

1564-556: The need for increase in battery life performance during active and standby usage by reducing the power consumption in mobile processors. Unlike current SMP architectures, the vSMP Companion core is OS transparent meaning that the operating system and the running applications are totally unaware of this extra core but are still able to take advantage of it. Some of the advantages of the vSMP architecture includes cache coherency, OS efficiency, and power optimization. The advantages for this architecture are explained below: These advantages lead

1610-527: The only way to determine the local APIC timer’s frequency is to measure it using the PIT or CMOS timer, which yields only an approximate result." I/O APICs contain a redirection table, which is used to route the interrupts it receives from peripheral buses to one or more local APICs. Early I/O APICs (like 82489DX, SIO.A and PCEB/ESC) only had support for 16 interrupt lines, but later ones like 82093AA (separate chip for PIIX3/PIIX4) had support for 24 interrupt lines. It

1656-439: The physical destination mode. The logical destination mode now works differently and introduces clusters; using this mode, one can address up to 2 − 16 processors. The improved interface reduces the number of needed APIC register accesses for sending inter-processor interrupts (IPIs). Because of this advantage, KVM can and does emulate the x2APIC for older processors that do not physically support it, and this support

1702-618: The processors are tightly coupled inside the same box with a bus or switch; on earlier SMP systems, a single CPU took an entire cabinet. Some of the components that are shared are global memory, disks, and I/O devices. Only one copy of an OS runs on all the processors, and the OS must be designed to take advantage of this architecture. Some of the basic advantages involves cost-effective ways to increase throughput. To solve different problems and tasks, SMP applies multiple processors to that one problem, known as parallel programming . However, there are

1748-584: The reference two-way 486 SMP system used three 82489DX chips, two as local APICs and one as I/O APIC. Starting with the P54C processor, the local APIC functionality was integrated into the Intel processors' silicon. The first dedicated I/O APIC was the Intel 82093AA, which was intended for PIIX3 -based systems. There are two components in the Intel APIC system, the local APIC (LAPIC) and the I/O APIC . There

1794-530: The sacrifice of programmability: Serious programming challenges remain with this kind of architecture because it requires two distinct modes of programming; one for the CPUs themselves and one for the interconnect between the CPUs. A single programming language would have to be able to not only partition the workload, but also comprehend the memory locality, which is severe in a mesh-based architecture. SMP systems allow any processor to work on any task no matter where

1840-410: The system's I/O APICs, or both. Logically, however, the 8259 is only connected once at any given time. The first-generation Intel APIC chip, the 82489DX, which was meant to be used with Intel 80486 and early Pentium processors, is actually an external local and I/O APIC in one circuit. The Intel MP 1.4 specification refers to it as "discrete APIC" in contrast with the "integrated APIC" found in most of

1886-403: The vSMP architecture to considerably benefit over other architectures using asynchronous clocking technologies. CPU-Z CPU-Z is a freeware system profiling and monitoring application for Microsoft Windows and Android that detects the central processing unit , RAM , motherboard chipset, and other hardware features of a modern personal computer or Android device . CPU-Z

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1932-477: Was asymmetric , with one processor restricted to application programs while the other processor mainly handled the operating system and hardware interrupts. The Burroughs D825 first implemented SMP in 1962. IBM offered dual-processor computer systems based on its System/360 Model 65 and the closely related Model 67 and 67–2. The operating systems that ran on these machines were OS/360 M65MP and TSS/360 . Other software developed at universities, notably

1978-502: Was a packaged as a 132-pin PQFP . Local APICs (LAPICs) manage all external interrupts for some specific processor in an SMP system. In addition, they are able to accept and generate inter-processor interrupts (IPIs) between LAPICs. Each one LAPIC may support up to 224 usable interrupt vectors from an I/O APIC. Vector numbers 0 to 31, out of 0 to 255, are reserved for exception handling by x86 processors. All Intel processors starting with

2024-537: Was derived and ported by VAST Corporation from AT&T 3B20 Unix SysVr3 code used internally within AT&;T. Earlier non-commercial multiprocessing UNIX ports existed, including a port named MUNIX created at the Naval Postgraduate School by 1975. Time-sharing and server systems can often use SMP without changes to applications, as they may have multiple processes running in parallel, and

2070-540: Was packaged as a 64-Pin PQFP . The 82093AA normally connected to the PIIX3 / PIIX4 and used its integrated legacy 8259 PICs. The ICH1 integrated the I/O APIC. An integrated I/O APIC of modern chipsets may provide more than 24 interrupt lines. According to a 2009 Intel benchmark using Linux , the I/O APIC reduced interrupt latency by a factor of almost three relative to the 8259 emulation (XT-PIC), while using MSI reduced

2116-657: Was released with OpenPIC however. After the OpenPIC's failure in the x86 market, AMD licensed Intel's APIC for its AMD Athlon and later processors. IBM however developed their MultiProcessor Interrupt Controller (MPIC) based on the OpenPIC register specifications. MPIC was used in PowerPC based designs, including those of IBM, for instance in some RS/6000 systems, but also by Apple, as late as their Power Mac G5s . Symmetric multiprocessor Symmetric multiprocessing or shared-memory multiprocessing ( SMP ) involves

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