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126-706: The Pentium II is a brand of sixth-generation Intel x86 microprocessors based on the P6 microarchitecture , introduced on May 7, 1997. It combined the P6 microarchitecture seen on the Pentium Pro with the MMX instruction set of the Pentium MMX . Containing 7.5 million transistors (27.4 million in the case of the mobile Dixon with 256  KB on-die L2 cache ), the Pentium II featured an improved version of

252-554: A 100 MT/s FSB. Later in 1998, Pentium IIs running at 266, 300, 350, 400, and 450 MHz were also released. The Deschutes core introduced FXSAVE and FXRSTOR instructions for fast FPU context save and restore. Towards the end of its design life, Deschutes chips capable of 500 MHz within Intel cooling and design specifications were produced. However, these were not marketed. Rather than destroy already multiplier-locked units, those Deschutes units that had been tested and locked with

378-434: A 100 MT/s front-side bus was Intel's release of the 440BX Seattle chipset and its derivatives, the 440MX, 450NX, and 440ZX chipsets. Replacing the aged 66 MHz FSB, which had been on the market since 1993, the 100 MHz FSB resulted in solid performance improvements for the Pentium II lineup. Pentium II chips starting with 350 MHz were released in both SECC and SECC2 form factors. Late Pentium IIs also marked

504-609: A 60 or 66 MHz front-side bus. This combination brought together some of the more attractive aspects of the Pentium II and the Pentium II Xeon: MMX support/improved 16-bit performance and full-speed L2 cache, respectively. The later "Dixon" mobile Pentium II would emulate this combination with 256 KB of full-speed cache. In Intel's "Family/Model/Stepping" scheme, the Pentium II OverDrive CPU identifies itself as family 6, model 3, though this

630-431: A common virtual address space. A program executes by calculating, comparing, reading and writing to addresses of its virtual address space, rather than addresses of physical address space, making programs simpler and thus easier to write. Virtual memory requires the processor to translate virtual addresses generated by the program into physical addresses in main memory. The portion of the processor that does this translation

756-611: A decade, from 2007 to 2016 fiscal years, until it was removed from the ranking in 2018. In 2020, it was reinstated and ranked 45th, being the 7th-largest technology company in the ranking . Intel supplies microprocessors for most manufacturers of computer systems, and is one of the developers of the x86 series of instruction sets found in most personal computers (PCs). It also manufactures chipsets , network interface controllers , flash memory , graphics processing units (GPUs), field-programmable gate arrays (FPGAs), and other devices related to communications and computing. Intel has

882-429: A direct-mapped cache, closer to the miss rate of a fully associative cache. Comparing with a direct-mapped cache, a set associative cache has a reduced number of bits for its cache set index that maps to a cache set, where multiple ways or blocks stays, such as 2 blocks for a 2-way set associative cache and 4 blocks for a 4-way set associative cache. Comparing with a direct mapped cache, the unused cache index bits become

1008-428: A full 4 GB cacheable area. The original Klamath Pentium II microprocessor (Intel product code 80522) ran at 233, 266, and 300  MHz and was produced in a 0.35 μm process. The 300 MHz version, however, only became available in large quantities later in 1997. These CPUs had a 66 MHz front-side bus and were initially used on motherboards equipped with the aging Intel 440FX Natoma chipset designed for

1134-437: A limited group of private investors (equivalent to $ 21 million in 2022), convertible at $ 5 per share. Just 2 years later, Intel became a public company via an initial public offering (IPO), raising $ 6.8 million ($ 23.50 per share). Intel was one of the very first companies to be listed on the then-newly established National Association of Securities Dealers Automated Quotations ( NASDAQ ) stock exchange. Intel's third employee

1260-572: A major retrenchment for most of the major semiconductor manufacturers, except for Qualcomm, which continued to see healthy purchases from its largest customer, Apple. As of July 2013, five companies were using Intel's fabs via the Intel Custom Foundry division: Achronix , Tabula , Netronome , Microsemi , and Panasonic  – most are field-programmable gate array (FPGA) makers, but Netronome designs network processors. Only Achronix began shipping chips made by Intel using

1386-535: A mapping table held in core memory before every programmed access to main memory. With no caches, and with the mapping table memory running at the same speed as main memory this effectively cut the speed of memory access in half. Two early machines that used a page table in main memory for mapping, the IBM System/360 Model 67 and the GE 645 , both had a small associative memory as a cache for accesses to

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1512-429: A multiplier of 5 were sold as being 333 MHz. This was accomplished by disabling the 100 MHz bus option. Overclockers , upon learning of this, purchased the units in question and ran them well over 500 MHz; most notably, when overclocking, the final batch of "333 MHz" CPUs were capable of speeds much higher than CPUs sold at 350, 400, or 450 MHz. Concurrent with the release of Deschutes cores supporting

1638-632: A new microprocessor manufacturing facility in Chandler, Arizona , completed in 2013 at a cost of $ 5 billion. The building is now the 10 nm-certified Fab 42 and is connected to the other Fabs (12, 22, 32) on Ocotillo Campus via an enclosed bridge known as the Link. The company produces three-quarters of its products in the United States, although three-quarters of its revenue come from overseas. The Alliance for Affordable Internet (A4AI)

1764-505: A part of the tag bits. For example, a 2-way set associative cache contributes 1 bit to the tag and a 4-way set associative cache contributes 2 bits to the tag. The basic idea of the multicolumn cache is to use the set index to map to a cache set as a conventional set associative cache does, and to use the added tag bits to index a way in the set. For example, in a 4-way set associative cache, the two bits are used to index way 00, way 01, way 10, and way 11, respectively. This double cache indexing

1890-696: A processor for tablets and smartphones – to the market in 2012, as an effort to compete with Arm. As a 32-nanometer processor, Medfield is designed to be energy-efficient, which is one of the core features in Arm's chips. At the Intel Developers Forum (IDF) 2011 in San Francisco, Intel's partnership with Google was announced. In January 2012, Google announced Android 2.3, supporting Intel's Atom microprocessor. In 2013, Intel's Kirk Skaugen said that Intel's exclusive focus on Microsoft platforms

2016-413: A reduced or omitted (in some cases present but disabled) on-die full-speed L2 cache and a 66 MT/s FSB. The Xeon was characterized by a range of full-speed L2 cache (from 512 KB to 2048 KB), a 100 MT/s FSB, a different physical interface ( Slot 2 ), and support for symmetric multiprocessing . In February 1999, the Pentium II was replaced by the nearly identical Pentium III , which only added

2142-579: A standalone business unit. Unlike Intel Custom Foundry, IFS will offer a combination of packaging and process technology, and Intel's IP portfolio including x86 cores. Other plans for the company include a partnership with IBM and a new event for developers and engineers, called "Intel ON". Gelsinger also confirmed that Intel's 7 nm process is on track, and that the first products using their 7 nm process (also known as Intel 4) are Ponte Vecchio and Meteor Lake . In January 2022, Intel reportedly selected New Albany, Ohio , near Columbus, Ohio , as

2268-636: A stroke regained much of its leadership of the field. In 2008, Intel had another "tick" when it introduced the Penryn microarchitecture, fabricated using the 45 nm process node. Later that year, Intel released a processor with the Nehalem architecture to positive reception. On June 27, 2006, the sale of Intel's XScale assets was announced. Intel agreed to sell the XScale processor business to Marvell Technology Group for an estimated $ 600 million and

2394-418: A strong presence in the high-performance general-purpose and gaming PC market with its Intel Core line of CPUs, whose high-end models are among the fastest consumer CPUs, as well as its Intel Arc series of GPUs. The Open Source Technology Center at Intel hosts PowerTOP and LatencyTOP , and supports other open source projects such as Wayland , Mesa , Threading Building Blocks (TBB), and Xen . Intel

2520-486: A struggle with Microsoft for control over the direction of the PC industry. Since the 2000s and especially since the late 2010s, Intel has faced increasing competition, which has led to a reduction in Intel's dominance and market share in the PC market. Nevertheless, with a 68.4% market share as of 2023, Intel still leads the x86 market by a wide margin. In addition, Intel's ability to design and manufacture its own chips

2646-456: Is RISC-V , which is an open source CPU instruction set. The major Chinese phone and telecommunications manufacturer Huawei has released chips based on the RISC-V instruction set due to US sanctions against China . Intel has been involved in several disputes regarding the violation of antitrust laws , which are noted below. Intel reported total CO 2 e emissions (direct + indirect) for

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2772-402: Is a failed attempt to read or write a piece of data in the cache, which results in a main memory access with much longer latency. There are three kinds of cache misses: instruction read miss, data read miss, and data write miss. Cache read misses from an instruction cache generally cause the largest delay, because the processor, or at least the thread of execution , has to wait (stall) until

2898-624: Is an American multinational corporation and technology company headquartered in Santa Clara, California , and incorporated in Delaware . Intel designs, manufactures, and sells computer components and related products for business and consumer markets. It is considered one of the world's largest semiconductor chip manufacturers by revenue and ranked in the Fortune 500 list of the largest United States corporations by revenue for nearly

3024-506: Is another large customer for Intel. In September 2024, Intel reportedly qualified for as much as $ 3.5 billion in federal grants to make semiconductors for the Defense Department. According to IDC , while Intel enjoyed the biggest market share in both the overall worldwide PC microprocessor market (73.3%) and the mobile PC microprocessor (80.4%) in the second quarter of 2011, the numbers decreased by 1.5% and 1.9% compared to

3150-399: Is called a "major location mapping", and its latency is equivalent to a direct-mapped access. Extensive experiments in multicolumn cache design shows that the hit ratio to major locations is as high as 90%. If cache mapping conflicts with a cache block in the major location, the existing cache block will be moved to another cache way in the same set, which is called "selected location". Because

3276-411: Is considered a rarity in the semiconductor industry , as most chip designers do not have their own production facilities and instead rely on contract manufacturers (e.g. AMD and Nvidia ). In 2023, Dell accounted for about 19% of Intel's total revenues, Lenovo accounted for 11% of total revenues, and HP Inc. accounted for 10% of total revenues. As of May 2024, the U.S. Department of Defense

3402-520: Is crucial to CPU performance, and so most modern level-1 caches are virtually indexed, which at least allows the MMU's TLB lookup to proceed in parallel with fetching the data from the cache RAM. But virtual indexing is not the best choice for all cache levels. The cost of dealing with virtual aliases grows with cache size, and as a result most level-2 and larger caches are physically indexed. Caches have historically used both virtual and physical addresses for

3528-643: Is equal to the number of cache blocks divided by the number of ways of associativity, what leads to 128 / 4 = 32 sets, and hence 2  = 32 different indices. There are 2  = 64 possible offsets. Since the CPU address is 32 bits wide, this implies 32 − 5 − 6 = 21 bits for the tag field. The original Pentium 4 processor also had an eight-way set associative L2 integrated cache 256 KiB in size, with 128-byte cache blocks. This implies 32 − 8 − 7 = 17 bits for

3654-438: Is expected to affect Intel minimally; however, it might prompt other PC manufacturers to reevaluate their reliance on Intel and the x86 architecture. On March 23, 2021, CEO Pat Gelsinger laid out new plans for the company. These include a new strategy, called IDM 2.0, that includes investments in manufacturing facilities, use of both internal and external foundries, and a new foundry business called Intel Foundry Services (IFS),

3780-496: Is extra latency from computing the hash function. Additionally, when it comes time to load a new line and evict an old line, it may be difficult to determine which existing line was least recently used, because the new line conflicts with data at different indexes in each way; LRU tracking for non-skewed caches is usually done on a per-set basis. Nevertheless, skewed-associative caches have major advantages over conventional set-associative ones. A true set-associative cache tests all

3906-548: Is generally still a small number of KiB. The IBM zEC12 from 2012 is an exception however, to gain unusually large 96 KiB L1 data cache for its time, and e.g. the IBM z13 having a 96 KiB L1 instruction cache (and 128 KiB L1 data cache), and Intel Ice Lake -based processors from 2018, having 48 KiB L1 data cache and 48 KiB L1 instruction cache. In 2020, some Intel Atom CPUs (with up to 24 cores) have (multiple of) 4.5 MiB and 15 MiB cache sizes. Data

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4032-495: Is known as the memory management unit (MMU). The fast path through the MMU can perform those translations stored in the translation lookaside buffer (TLB), which is a cache of mappings from the operating system's page table , segment table, or both. For the purposes of the present discussion, there are three important features of address translation: One early virtual memory system, the IBM M44/44X , required an access to

4158-536: Is misleading, as it is not based on the family 6/model 3 Klamath core. As mentioned in the Pentium II Processor update documentation from Intel, "although this processor has a CPUID of 163xh, it uses a Pentium II processor CPUID 065xh processor core." The 0.25 μm Tonga core was the first mobile Pentium II and had all of the features of the desktop models. In Intel's "Family/Model/Stepping" scheme, Tonga CPUs are family 6, model 5. Later, in 1999,

4284-471: Is planned for 2027. Including subcontractors, this would create 10,000 new jobs. In August 2022, Intel signed a $ 30   billion partnership with Brookfield Asset Management to fund its recent factory expansions. As part of the deal, Intel would have a controlling stake by funding 51% of the cost of building new chip-making facilities in Chandler, with Brookfield owning the remaining 49% stake, allowing

4410-476: Is that it must predict which existing cache entry is least likely to be used in the future. Predicting the future is difficult, so there is no perfect method to choose among the variety of replacement policies available. One popular replacement policy, least-recently used (LRU), replaces the least recently accessed entry. Marking some memory ranges as non-cacheable can improve performance, by avoiding caching of memory regions that are rarely re-accessed. This avoids

4536-399: Is transferred between memory and cache in blocks of fixed size, called cache lines or cache blocks . When a cache line is copied from memory into the cache, a cache entry is created. The cache entry will include the copied data as well as the requested memory location (called a tag). When the processor needs to read or write a location in memory, it first checks for a corresponding entry in

4662-494: Is usually not shared between the cores. The L2 cache, and higher-level caches, may be shared between the cores. L4 cache is currently uncommon, and is generally dynamic random-access memory (DRAM) on a separate die or chip, rather than static random-access memory (SRAM). An exception to this is when eDRAM is used for all levels of cache, down to L1. Historically L1 was also on a separate die, however bigger die sizes have allowed integration of it as well as other cache levels, with

4788-513: The IBM 801 CPU, became mainstream in the late 1980s, and in 1997 entered the embedded CPU market with the ARMv5TE. In 2015, even sub-dollar SoCs split the L1 cache. They also have L2 caches and, for larger processors, L3 caches as well. The L2 cache is usually not split, and acts as a common repository for the already split L1 cache. Every core of a multi-core processor has a dedicated L1 cache and

4914-586: The Intel MMX integer SIMD instruction set which had already been introduced on the Pentium MMX . The Pentium II was a more consumer-oriented version of the Pentium Pro. It was cheaper to manufacture because of the separate, slower L2 cache memory. The improved 16-bit performance and MMX support made it a better choice for consumer-level operating systems, such as Windows 9x , and multimedia applications. The slower and cheaper L2 cache's performance penalty

5040-515: The PowerPC architecture developed by the AIM alliance . This was seen as a win for Intel; an analyst called the move "risky" and "foolish", as Intel's current offerings at the time were considered to be behind those of AMD and IBM. In 2006, Intel unveiled its Core microarchitecture to widespread critical acclaim; the product range was perceived as an exceptional leap in processor performance that at

5166-614: The Semiconductor Chip Protection Act of 1984 , a law sought by Intel and the Semiconductor Industry Association (SIA). During the late 1980s and 1990s (after this law was passed), Intel also sued companies that tried to develop competitor chips to the 80386 CPU . The lawsuits were noted to significantly burden the competition with legal bills, even if Intel lost the suits. Antitrust allegations had been simmering since

Pentium II - Misplaced Pages Continue

5292-492: The Zen microarchitecture and a new chiplet -based design to critical acclaim. Since its introduction, AMD, once unable to compete with Intel in the high-end CPU market, has undergone a resurgence, and Intel's dominance and market share have considerably decreased. In addition, Apple began to transition away from the x86 architecture and Intel processors to their own Apple silicon for their Macintosh computers in 2020. The transition

5418-535: The semiconductor memory market, widely predicted to replace magnetic-core memory . Its first product, a quick entry into the small, high-speed memory market in 1969, was the 3101 Schottky TTL bipolar 64-bit static random-access memory (SRAM), which was nearly twice as fast as earlier Schottky diode implementations by Fairchild and the Electrotechnical Laboratory in Tsukuba, Japan . In

5544-430: The skewed cache , where the index for way 0 is direct, as above, but the index for way 1 is formed with a hash function . A good hash function has the property that addresses which conflict with the direct mapping tend not to conflict when mapped with the hash function, and so it is less likely that a program will suffer from an unexpectedly large number of conflict misses due to a pathological access pattern. The downside

5670-457: The x86 processor market is AMD, with which Intel has had full cross-licensing agreements since 1976: each partner can use the other's patented technological innovations without charge after a certain time. However, the cross-licensing agreement is canceled in the event of an AMD bankruptcy or takeover. Some smaller competitors, such as VIA Technologies, produce low-power x86 processors for small factor computers and portable equipment. However,

5796-407: The "cache size" of the most important caches mentioned above), such as the translation lookaside buffer (TLB) which is part of the memory management unit (MMU) which most CPUs have. When trying to read from or write to a location in the main memory, the processor checks whether the data from that location is already in the cache. If so, the processor will read from or write to the cache instead of

5922-645: The 0.25; 0.18 (400  MHz ) μm Dixon core with 256 KB of on-die full speed cache was produced for the mobile market. Reviews showed that the Dixon core was the fastest type of Pentium II produced. In Intel's "Family/Model/Stepping" scheme, Dixon CPUs are family 6, model 6 and their Intel product code is 80524. These identifiers are shared with the Mendocino Celeron processors. Mobile Pentium II Mobile Pentium II PE ("Performance Enhanced") Intel datasheets Intel Intel Corporation

6048-464: The 22 nm Tri-Gate process. Several other customers also exist but were not announced at the time. The foundry business was closed in 2018 due to Intel's issues with its manufacturing. Intel continued its tick-tock model of a microarchitecture change followed by a die shrink until the 6th-generation Core family based on the Skylake microarchitecture. This model was deprecated in 2016, with

6174-438: The CPU attempts to execute independent instructions after the instruction that is waiting for the cache miss data. Another technology, used by many processors, is simultaneous multithreading (SMT), which allows an alternate thread to use the CPU core while the first thread waits for required CPU resources to become available. The placement policy decides where in the cache a copy of a particular entry of main memory will go. If

6300-502: The CPU part number. In Intel's "Family/Model/Stepping" scheme, Klamath CPUs are family 6, model 3. The Deschutes core Pentium II (80523), which debuted at 333 MHz in January 1998, was produced with a 0.25 μm process and has a significantly lower power draw. The die size is 113 mm. The 333 MHz variant was the final Pentium II CPU that used the older 66 MT/s front-side bus ; all subsequent Deschutes-core models used

6426-463: The CPU will run out of work while waiting for the cache line. When a CPU reaches this state, it is called a stall. As CPUs become faster compared to main memory, stalls due to cache misses displace more potential computation; modern CPUs can execute hundreds of instructions in the time taken to fetch a single cache line from main memory. Various techniques have been employed to keep the CPU busy during this time, including out-of-order execution in which

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6552-466: The Pentium II CPU was packaged in a slot -based module rather than a CPU socket . The processor and associated components were carried on a daughterboard similar to a typical expansion board within a plastic cartridge. A fixed or removable heatsink was carried on one side, sometimes using its own fan. This larger package was a compromise allowing Intel to separate the secondary cache from

6678-418: The Pentium Pro's low yield issues, allowing Intel to introduce the Pentium II at a mainstream price level. Intel improved 16-bit code execution performance on the Pentium II, an area in which the Pentium Pro was at a notable handicap, by adding segment register caches. Most consumer software of the day was still using at least some 16-bit code, because of a variety of factors. The issues with partial registers

6804-709: The Pentium Pro. Pentium II-based systems using the Intel 440LX Balboa chipset widely popularized SDRAM (which was to replace EDO RAM and was already introduced with 430VX), and the AGP graphics bus. On July 14, 1997, Intel announced a version of the Pentium II Klamath with 2× 72-bit ECC L2 cache for entry-level servers, as opposed to the 2× 64-bit non-ECC L2 cache on regular models. The extra bits give it error-correction capability built into hardware, without impacting performance. The variant can be determined through

6930-611: The UN Broadband Commission's worldwide target of 5% of monthly income. In April 2011, Intel began a pilot project with ZTE Corporation to produce smartphones using the Intel Atom processor for China's domestic market. In December 2011, Intel announced that it reorganized several of its business units into a new mobile and communications group that would be responsible for the company's smartphone, tablet, and wireless efforts. Intel planned to introduce Medfield –

7056-689: The United States. Intel was incorporated in Mountain View, California , on July 18, 1968, by Gordon E. Moore (known for " Moore's law "), a chemist ; Robert Noyce , a physicist and co-inventor of the integrated circuit ; and Arthur Rock , an investor and venture capitalist . Moore and Noyce had left Fairchild Semiconductor , where they were part of the " traitorous eight " who founded it. There were originally 500,000 shares outstanding of which Dr. Noyce bought 245,000 shares, Dr. Moore 245,000 shares, and Mr. Rock 10,000 shares; all at $ 1 per share. Rock offered $ 2,500,000 of convertible debentures to

7182-484: The Xeon 6 processor, aiming for better performance and power efficiency compared to its predecessor. Intel's Gaudi 2 and Gaudi 3 AI accelerators were revealed to be more cost-effective than competitors' offerings. Additionally, Intel disclosed architecture details for its Lunar Lake processors for AI PCs, which were released on September 24, 2024. Tag RAM Other types of caches exist (that are not counted towards

7308-409: The advantages of a direct-mapped cache is that it allows simple and fast speculation . Once the address has been computed, the one cache index which might have a copy of that location in memory is known. That cache entry can be read, and the processor can continue to work with that data before it finishes checking that the tag actually matches the requested address. The idea of having the processor use

7434-587: The advent of such mobile computing devices, in particular, smartphones , has led to a decline in PC sales . Since over 95% of the world's smartphones currently use processors cores designed by Arm , using the Arm instruction set , Arm has become a major competitor for Intel's processor market. Arm is also planning to make attempts at setting foot into the PC and server market, with Ampere and IBM each individually designing CPUs for servers and supercomputers . The only other major competitor in processor instruction sets

7560-488: The associativity of their caches in low-power states, which acts as a power-saving measure. In order of worse but simple to better but complex: In this cache organization, each location in the main memory can go in only one entry in the cache. Therefore, a direct-mapped cache can also be called a "one-way set associative" cache. It does not have a placement policy as such, since there is no choice of which cache entry's contents to evict. This means that if two locations map to

7686-402: The assumption of unspecified liabilities. The move was intended to permit Intel to focus its resources on its core x86 and server businesses, and the acquisition completed on November 9, 2006. In 2008, Intel spun off key assets of a solar startup business effort to form an independent company, SpectraWatt Inc. In 2011, SpectraWatt filed for bankruptcy. In February 2011, Intel began to build

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7812-404: The cache do not have to include that part of the main memory address which is implied by the cache memory's index. Since the cache tags have fewer bits, they require fewer transistors, take less space on the processor circuit board or on the microprocessor chip, and can be read and compared faster. Also LRU algorithm is especially simple since only one bit needs to be stored for each pair. One of

7938-405: The cache line. For a cache miss, the cache allocates a new entry and copies data from main memory, then the request is fulfilled from the contents of the cache. To make room for the new entry on a cache miss, the cache may have to evict one of the existing entries. The heuristic it uses to choose the entry to evict is called the replacement policy. The fundamental problem with any replacement policy

8064-399: The cache miss rate play an important role in determining this performance. To improve the cache performance, reducing the miss rate becomes one of the necessary steps among other steps. Decreasing the access time to the cache also gives a boost to its performance and helps with optimization. The time taken to fetch one cache line from memory (read latency due to a cache miss) matters because

8190-583: The cache. (The tag, flag and error correction code bits are not included in the size, although they do affect the physical area of a cache.) An effective memory address which goes along with the cache line (memory block) is split ( MSB to LSB ) into the tag, the index and the block offset. The index describes which cache set that the data has been put in. The index length is ⌈ log 2 ⁡ ( s ) ⌉ {\displaystyle \lceil \log _{2}(s)\rceil } bits for s cache sets. The block offset specifies

8316-407: The cache. The cache checks for the contents of the requested memory location in any cache lines that might contain that address. If the processor finds that the memory location is in the cache, a cache hit has occurred. However, if the processor does not find the memory location in the cache, a cache miss has occurred. In the case of a cache hit, the processor immediately reads or writes the data in

8442-455: The cached data before the tag match completes can be applied to associative caches as well. A subset of the tag, called a hint , can be used to pick just one of the possible cache entries mapping to the requested address. The entry selected by the hint can then be used in parallel with checking the full tag. The hint technique works best when used in the context of address translation, as explained below. Other schemes have been suggested, such as

8568-420: The companies to split the revenue from those facilities. On January 31, 2023, as part of $ 3 billion in cost reductions, Intel announced pay cuts affecting employees above midlevel, ranging from 5% upwards. It also suspended bonuses and merit pay increases, while reducing retirement plan matching. These cost reductions followed layoffs announced in the fall of 2022. In October 2023, Intel confirmed it would be

8694-456: The company as NM Electronics on July 18, 1968, but by the end of the month had changed the name to Intel , which stood for Int egrated El ectronics. Since "Intel" was already trademarked by the hotel chain Intelco, they had to buy the rights for the name. At its founding, Intel was distinguished by its ability to make logic circuits using semiconductor devices . The founders' goal was

8820-425: The company's focus to microprocessors and to change fundamental aspects of that business model. Moore's decision to sole-source Intel's 386 chip played into the company's continuing success. By the end of the 1980s, buoyed by its fortuitous position as microprocessor supplier to IBM and IBM's competitors within the rapidly growing personal computer market , Intel embarked on a 10-year period of unprecedented growth as

8946-490: The current set (the set has been retrieved by index) to see if this set contains the requested address. If it does, a cache hit occurs. The tag length in bits is as follows: Some authors refer to the block offset as simply the "offset" or the "displacement". The original Pentium 4 processor had a four-way set associative L1 data cache of 8  KiB in size, with 64-byte cache blocks. Hence, there are 8 KiB / 64 = 128 cache blocks. The number of sets

9072-470: The data consistent are known as cache coherence protocols. Cache performance measurement has become important in recent times where the speed gap between the memory performance and the processor performance is increasing exponentially. The cache was introduced to reduce this speed gap. Thus knowing how well the cache is able to bridge the gap in the speed of processor and memory becomes important, especially in high-performance systems. The cache hit rate and

9198-434: The desired data within the stored data block within the cache row. Typically the effective address is in bytes, so the block offset length is ⌈ log 2 ⁡ ( b ) ⌉ {\displaystyle \lceil \log _{2}(b)\rceil } bits, where b is the number of bytes per data block. The tag contains the most significant bits of the address, which are checked against all rows in

9324-519: The early 1980s, and manufacturing and development centers in China, India, and Costa Rica in the 1990s. By the early 1980s, its business was dominated by DRAM chips. However, increased competition from Japanese semiconductor manufacturers had, by 1983, dramatically reduced the profitability of this market. The growing success of the IBM personal computer, based on an Intel microprocessor, was among factors that convinced Gordon Moore (CEO since 1975) to shift

9450-506: The early 1990s and had been the cause of one lawsuit against Intel in 1991. In 2004 and 2005, AMD brought further claims against Intel related to unfair competition . In 2005, CEO Paul Otellini reorganized the company to refocus its core processor and chipset business on platforms (enterprise, digital home, digital health, and mobility). On June 6, 2005, Steve Jobs , then CEO of Apple , announced that Apple would be using Intel's x86 processors for its Macintosh computers, switching from

9576-435: The execution of subsequent instructions; the processor can continue until the queue is full. For a detailed introduction to the types of misses, see cache performance measurement and metric . Most general purpose CPUs implement some form of virtual memory . To summarize, either each program running on the machine sees its own simplified address space , which contains code and data for that program only, or all programs run in

9702-557: The first P6 -generation core of the Pentium Pro, which contained 5.5 million transistors. However, its L2 cache subsystem was a downgrade when compared to the Pentium Pro's. In 1998, Intel stratified the Pentium II family by releasing the Pentium II-based Celeron line of processors for low-end computers and the Intel Pentium II Xeon line for servers and workstations. The Celeron was characterized by

9828-653: The first commercial user of high-NA EUV lithography tool, as part of its plan to regain process leadership from TSMC . In August 2024, following a below-expectations Q2 earnings announcement, Intel announced "significant actions to reduce our costs. We plan to deliver $ 10 billion in cost savings in 2025, and this includes reducing our head count by roughly 15,000 roles, or 15% of our workforce." In December 2023, Intel unveiled Gaudi3, an artificial intelligence (AI) chip for generative AI software which will launch in 2024 and compete with rival chips from Nvidia and AMD. On 4 June 2024, Intel announced AI chips for data centers,

9954-445: The first commercially available dynamic random-access memory (DRAM), the 1103 released in 1970, solved these issues. The 1103 was the bestselling semiconductor memory chip in the world by 1972, as it replaced core memory in many applications. Intel's business grew during the 1970s as it expanded and improved its manufacturing processes and produced a wider range of products , still dominated by various memory devices. Intel created

10080-409: The first commercially available microprocessor, the Intel 4004 , in 1971. The microprocessor represented a notable advance in the technology of integrated circuitry, as it miniaturized the central processing unit of a computer, which then made it possible for small machines to perform calculations that in the past only very large machines could do. Considerable technological innovation was needed before

10206-440: The first quarter of 2011. Intel's market share decreased significantly in the enthusiast market as of 2019, and they have faced delays for their 10 nm products. According to former Intel CEO Bob Swan, the delay was caused by the company's overly aggressive strategy for moving to its next node. In the 1980s, Intel was among the world's top ten sellers of semiconductors (10th in 1987 ). Along with Microsoft Windows , it

10332-425: The following structure: The data block (cache line) contains the actual data fetched from the main memory. The tag contains (part of) the address of the actual data fetched from the main memory. The flag bits are discussed below . The "size" of the cache is the amount of main memory data it can hold. This size can be calculated as the number of bytes stored in each data block times the number of blocks stored in

10458-408: The in-memory page table. Both machines predated the first machine with a cache for main memory, the IBM System/360 Model 85 , so the first hardware cache used in a computer system was not a data or instruction cache, but rather a TLB. Caches can be divided into four types, based on whether the index or tag correspond to physical or virtual addresses: The speed of this recurrence (the load latency )

10584-443: The instruction is fetched from main memory. Cache read misses from a data cache usually cause a smaller delay, because instructions not dependent on the cache read can be issued and continue execution until the data is returned from main memory, and the dependent instructions can resume execution. Cache write misses to a data cache generally cause the shortest delay, because the write can be queued and there are few limitations on

10710-519: The level-1 data cache in an AMD Athlon is two-way set associative, which means that any particular location in main memory can be cached in either of two locations in the level-1 data cache. Choosing the right value of associativity involves a trade-off . If there are ten places to which the placement policy could have mapped a memory location, then to check if that location is in the cache, ten cache entries must be searched. Checking more places takes more power and chip area, and potentially more time. On

10836-434: The local cache are now stale and should be marked invalid. A data cache typically requires two flag bits per cache line – a valid bit and a dirty bit . Having a dirty bit set indicates that the associated cache line has been changed since it was read from main memory ("dirty"), meaning that the processor has written data to that line and the new value has not propagated all the way to main memory. A cache miss

10962-399: The main memory can be cached in either of two locations in the cache, one logical question is: which one of the two? The simplest and most commonly used scheme, shown in the right-hand diagram above, is to use the least significant bits of the memory location's index as the index for the cache memory, and to have two entries for each index. One benefit of this scheme is that the tags stored in

11088-426: The main memory may be changed by other entities (e.g., peripherals using direct memory access (DMA) or another core in a multi-core processor ), in which case the copy in the cache may become out-of-date or stale. Alternatively, when a CPU in a multiprocessor system updates data in the cache, copies of data in caches associated with other CPUs become stale. Communication protocols between the cache managers that keep

11214-404: The main memory, and the cache instead tracks which locations have been written over, marking them as dirty . The data in these locations is written back to the main memory only when that data is evicted from the cache. For this reason, a read miss in a write-back cache may sometimes require two memory accesses to service: one to first write the dirty location to main memory, and then another to read

11340-633: The major location in a cache block. Multicolumn cache remains a high hit ratio due to its high associativity, and has a comparable low latency to a direct-mapped cache due to its high percentage of hits in major locations. The concepts of major locations and selected locations in multicolumn cache have been used in several cache designs in ARM Cortex R chip, Intel's way-predicting cache memory, IBM's reconfigurable multi-way associative cache memory and Oracle's dynamic cache replacement way selection based on address tab bits. Cache row entries usually have

11466-416: The majority of its business until 1981. Although Intel created the world's first commercial microprocessor chip—the Intel 4004 —in 1971, it was not until the success of the PC in the early 1990s that this became its primary business. During the 1990s, the partnership between Microsoft Windows and Intel, known as " Wintel ", became instrumental in shaping the PC landscape and solidified Intel's position on

11592-400: The market. As a result, Intel invested heavily in new microprocessor designs in the mid to late 1990s, fostering the rapid growth of the computer industry . During this period, it became the dominant supplier of PC microprocessors, with a market share of 90%, and was known for aggressive and anti-competitive tactics in defense of its market position, particularly against AMD , as well as

11718-536: The microprocessor could actually become the basis of what was first known as a "mini computer" and then known as a "personal computer". Intel also created one of the first microcomputers in 1973. Intel opened its first international manufacturing facility in 1972, in Malaysia , which would host multiple Intel operations, before opening assembly facilities and semiconductor plants in Singapore and Jerusalem in

11844-525: The much slower main memory. Many modern desktop , server , and industrial CPUs have at least three independent levels of caches (L1, L2 and L3) and different types of caches: Early examples of CPU caches include the Atlas 2 and the IBM System/360 Model 85 in the 1960s. The first CPUs that used a cache had only one level of cache; unlike later level 1 cache, it was not split into L1d (for data) and L1i (for instructions). Split L1 cache started in 1976 with

11970-486: The new location from memory. Also, a write to a main memory location that is not yet mapped in a write-back cache may evict an already dirty location, thereby freeing that cache space for the new memory location. There are intermediate policies as well. The cache may be write-through, but the writes may be held in a store data queue temporarily, usually so multiple stores can be processed together (which can reduce bus turnarounds and improve bus utilization). Cached data from

12096-404: The newly indexed cache block is a most recently used (MRU) block, it is placed in the major location in multicolumn cache with a consideration of temporal locality. Since multicolumn cache is designed for a cache with a high associativity, the number of ways in each set is high; thus, it is easy find a selected location in the set. A selected location index by an additional hardware is maintained for

12222-610: The node. The first microprocessor under that node, Cannon Lake (marketed as 8th-generation Core), was released in small quantities in 2018. The company first delayed the mass production of their 10 nm products to 2017. They later delayed mass production to 2018, and then to 2019. Despite rumors of the process being cancelled, Intel finally introduced mass-produced 10 nm 10th-generation Intel Core mobile processors (codenamed " Ice Lake ") in September 2019. Intel later acknowledged that their strategy to shrink to 10 nm

12348-540: The other hand, caches with more associativity suffer fewer misses (see conflict misses ), so that the CPU wastes less time reading from the slow main memory. The general guideline is that doubling the associativity, from direct mapped to two-way, or from two-way to four-way, has about the same effect on raising the hit rate as doubling the cache size. However, increasing associativity more than four does not improve hit rate as much, and are generally done for other reasons (see virtual aliasing ). Some CPUs can dynamically reduce

12474-465: The overhead of loading something into the cache without having any reuse. Cache entries may also be disabled or locked depending on the context. If data is written to the cache, at some point it must also be written to main memory; the timing of this write is known as the write policy. In a write-through cache, every write to the cache causes a write to main memory. Alternatively, in a write-back or copy-back cache, writes are not immediately mirrored to

12600-634: The part number 80523. In 1998, the 0.25 μm Deschutes core was utilized in the creation of the Pentium II Overdrive processor, which was aimed at allowing corporate Pentium Pro users to upgrade their aging servers. Combining the Deschutes core in a flip-chip package with a 512 KB full-speed L2 cache chip from the Pentium II Xeon into a Socket 8 -compatible module resulted in a 300 or 333 MHz processor that could run on

12726-420: The placement policy is free to choose any entry in the cache to hold the copy, the cache is called fully associative . At the other extreme, if each entry in the main memory can go in just one place in the cache, the cache is direct-mapped . Many caches implement a compromise in which each entry in the main memory can go to any one of N places in the cache, and are described as N-way set associative. For example,

12852-560: The possible exception of the last level. Each extra level of cache tends to be bigger and optimized differently. Caches (like for RAM historically) have generally been sized in powers of: 2, 4, 8, 16 etc. KiB ; when up to MiB sizes (i.e. for larger non-L1), very early on the pattern broke down, to allow for larger caches without being forced into the doubling-in-size paradigm, with e.g. Intel Core 2 Duo with 3 MiB L2 cache in April 2008. This happened much later for L1 caches, as their size

12978-422: The possible ways simultaneously, using something like a content-addressable memory . A pseudo-associative cache tests each possible way one at a time. A hash-rehash cache and a column-associative cache are examples of a pseudo-associative cache. In the common case of finding a hit in the first way tested, a pseudo-associative cache is as fast as a direct-mapped cache, but it has a much lower conflict miss rate than

13104-670: The primary and most profitable hardware supplier to the PC industry, part of the winning 'Wintel' combination. Moore handed over his position as CEO to Andy Grove in 1987. By launching its Intel Inside marketing campaign in 1991, Intel was able to associate brand loyalty with consumer selection, so that by the end of the 1990s, its line of Pentium processors had become a household name. After 2000, growth in demand for high-end microprocessors slowed. Competitors, most notably AMD (Intel's largest competitor in its primary x86 architecture market), garnered significant market share, initially in low-end and mid-range processors but ultimately across

13230-499: The processor while still keeping it on a closely coupled back-side bus . The L2 cache ran at half the processor's clock frequency, unlike the Pentium Pro, whose off die L2 cache ran at the same frequency as the processor. However, its associativity was increased to 16-way (compared to 4-way on the Pentium Pro) and its size was always 512 KB, twice of the smallest option of 256 KB on the Pentium Pro. Off-package cache solved

13356-514: The product range, and Intel's dominant position in its core market was greatly reduced, mostly due to controversial NetBurst microarchitecture. In the early 2000s then-CEO, Craig Barrett attempted to diversify the company's business beyond semiconductors, but few of these activities were ultimately successful. Bob had also for a number of years been embroiled in litigation. U.S. law did not initially recognize intellectual property rights related to microprocessor topology (circuit layouts), until

13482-536: The release of the 7th-generation Core family (codenamed Kaby Lake ), ushering in the process–architecture–optimization model . As Intel struggled to shrink their process node from 14 nm to 10 nm , processor development slowed down and the company continued to use the Skylake microarchitecture until 2020, albeit with optimizations. While Intel originally planned to introduce 10 nm products in 2016, it later became apparent that there were manufacturing issues with

13608-405: The same entry, they may continually knock each other out. Although simpler, a direct-mapped cache needs to be much larger than an associative one to give comparable performance, and it is more unpredictable. Let x be block number in cache, y be block number of memory, and n be number of blocks in cache, then mapping is done with the help of the equation x = y mod n . If each location in

13734-405: The same year, Intel also produced the 3301 Schottky bipolar 1024-bit read-only memory (ROM) and the first commercial metal–oxide–semiconductor field-effect transistor (MOSFET) silicon gate SRAM chip, the 256-bit 1101. While the 1101 was a significant advance, its complex static cell structure made it too slow and costly for mainframe memories. The three- transistor cell implemented in

13860-514: The site for a major new manufacturing facility. The facility will cost at least $ 20 billion. The company expects the facility to begin producing chips by 2025. The same year Intel also choose Magdeburg , Germany , as a site for two new chip mega factories for €17 billion (topping Tesla 's investment in Brandenburg ). The start of the construction was initially planned for 2023, but this has been postponed to late 2024, while production start

13986-503: The smartphone market. Finding itself with excess fab capacity after the failure of the Ultrabook to gain market traction and with PC sales declining, in 2013 Intel reached a foundry agreement to produce chips for Altera using a 14 nm process. General Manager of Intel's custom foundry division Sunit Rikhi indicated that Intel would pursue further such deals in the future. This was after poor sales of Windows 8 hardware caused

14112-474: The switch to flip-chip based packaging with direct heatsink contact to the die, as opposed to traditional bonding. While Klamath features 4 cache chips and simulates dual-porting through interleaving (2x 64-bit) for a slight performance improvement on concurrent accesses, Deschutes only sports 2 cache chips and offers slightly lower L2 cache performance at the same clockspeed. Furthermore, Deschutes always features ECC-enabled L2 cache. The Pentium II Xeon

14238-507: The tag field. An instruction cache requires only one flag bit per cache row entry: a valid bit. The valid bit indicates whether or not a cache block has been loaded with valid data. On power-up, the hardware sets all the valid bits in all the caches to "invalid". Some systems also set a valid bit to "invalid" at other times, such as when multi-master bus snooping hardware in the cache of one processor hears an address broadcast from some other processor, and realizes that certain data blocks in

14364-413: The then-new SSE instruction set. However, the older family would continue to be produced until June 2001 for desktop units, September 2001 for mobile units, and the end of 2003 for embedded devices. The Pentium II microprocessor was largely based upon the microarchitecture of its predecessor, the Pentium Pro , but with some significant improvements. Unlike previous Pentium and Pentium Pro processors,

14490-400: The twelve months ending December 31, 2020, at 2,882 Kt (+94/+3.4% y-o-y). Intel plans to reduce carbon emissions 10% by 2030 from a 2020 base year. Intel has self-reported that they have Wafer fabrication plants in the United States, Ireland , and Israel. They have also self-reported that they have assembly and testing sites mostly in China, Costa Rica, Malaysia, and Vietnam, and one site in

14616-408: Was Andy Grove , a chemical engineer , who later ran the company through much of the 1980s and the high-growth 1990s. In deciding on a name, Moore and Noyce quickly rejected "Moore Noyce", near homophone for "more noise" – an ill-suited name for an electronics company, since noise in electronics is usually undesirable and typically associated with bad interference . Instead, they founded

14742-469: Was a high-end version of Deschutes core intended for use on workstations and servers . Principally, it used a different type of slot ( Slot 2 ), case, board design, and more expensive full-speed custom L2 cache, which was off-die. Versions were produced with 512 KB, 1 MB or 2 MB L2 caches by varying the number of 512 KB chips incorporated on the board. In Intel's "Family/Model/Stepping" scheme, Deschutes CPUs are family 6, model 5 and have

14868-559: Was a thing of the past and that they would now support all "tier-one operating systems" such as Linux, Android, iOS, and Chrome. In 2014, Intel cut thousands of employees in response to "evolving market trends", and offered to subsidize manufacturers for the extra costs involved in using Intel chips in their tablets. In April 2016, Intel cancelled the SoFIA platform and the Broxton Atom SoC for smartphones, effectively leaving

14994-415: Was also addressed by adding an internal flag to skip pipeline flushes whenever possible. To compensate for the slower L2 cache, the Pentium II featured 32 KB of L1 cache, double that of the Pentium Pro, as well as 4 write buffers (vs. 2 on the Pentium Pro); these can also be used by either pipeline, instead of each one being fixed to one pipeline. The Pentium II was also the first P6-based CPU to implement

15120-402: Was founded on July 18, 1968, by semiconductor pioneers Gordon Moore (of Moore's law ) and Robert Noyce , along with investor Arthur Rock , and is associated with the executive leadership and vision of Andrew Grove . The company was a key component of the rise of Silicon Valley as a high-tech center, as well as being an early developer of SRAM and DRAM memory chips, which represented

15246-514: Was launched in October 2013 and Intel is part of the coalition of public and private organizations that also includes Facebook , Google , and Microsoft . Led by Sir Tim Berners-Lee , the A4AI seeks to make Internet access more affordable so that access is broadened in the developing world, where only 31% of people are online. Google will help to decrease Internet access prices so that they fall below

15372-411: Was mitigated by the doubled L1 cache and architectural improvements for legacy code. General processor performance was increased while costs were cut. All Klamath and some early Deschutes Pentium IIs use a combined L2 cache controller / tag RAM chip that only allows for 512 MB to be cached; while more RAM could be installed in theory, this would result in very slow performance. While this limit

15498-955: Was part of the " Wintel " personal computer domination in the 1990s and early 2000s. In 1992, Intel became the biggest semiconductor chip maker by revenue and held the position until 2018 when Samsung Electronics surpassed it, but Intel returned to its former position the year after. Other major semiconductor companies include TSMC , GlobalFoundries , Texas Instruments , ASML , STMicroelectronics , United Microelectronics Corporation (UMC), Micron , SK Hynix , Kioxia , and SMIC . Intel's competitors in PC chipsets included AMD , VIA Technologies , Silicon Integrated Systems , and Nvidia . Intel's competitors in networking include NXP Semiconductors , Infineon , Broadcom Limited , Marvell Technology Group and Applied Micro Circuits Corporation , and competitors in flash memory included Spansion , Samsung Electronics, Qimonda , Kioxia, STMicroelectronics, Micron , and SK Hynix . The only major competitor in

15624-435: Was practically irrelevant for the average home user at the time, it was a concern for some workstation or server users. Presumably, Intel put this limitation deliberately in place to distinguish the Pentium II from the more upmarket Pentium Pro line, which has a full 4 GB cacheable area. The '82459AD' revision of the chip on some 333 MHz and all 350 MHz and faster Pentium IIs lifted this restriction and also offered

15750-401: Was reported that all Intel processors made since 1995 (besides Intel Itanium and pre-2013 Intel Atom ) had been subject to two security flaws dubbed Meltdown and Spectre. Due to Intel's issues with its 10 nm process node and the company's slow processor development, the company now found itself in a market with intense competition. The company's main competitor, AMD, introduced

15876-428: Was too aggressive. While other foundries used up to four steps in 10 nm or 7 nm processes, the company's 10 nm process required up to five or six multi-pattern steps. In addition, Intel's 10 nm process is denser than its counterpart processes from other foundries. Since Intel's microarchitecture and process node development were coupled, processor development stagnated. In early January 2018, it

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