The NS32000 , sometimes known as the 32k , is a series of microprocessors produced by National Semiconductor . Design work began around 1980 and it was announced at the International Solid-State Circuits Conference in April 1981.
77-452: The first member of the family came to market in 1982, briefly known as the 16032 before being renamed as the 32016 . It was the first general-purpose microprocessor on the market that used 32-bit data internally: the Motorola 68000 had 32-bit registers and instructions to perform 32-bit arithmetic, but used a 16-bit ALU for arithmetic operations on data, and thus took twice as long as
154-520: A PDP-8 , an Intel 80386 , an Intel 4004 , a Motorola 68000 , a System z mainframe, a Burroughs B5000 , a VAX , a Zilog Z80000 , and a MOS Technology 6502 all vary widely in the number, sizes, and formats of instructions, the number, types, and sizes of registers, and the available data types. Some have hardware support for operations like scanning for a substring, arbitrary-precision BCD arithmetic, or transcendental functions , while others have only 8-bit addition and subtraction. But they are all in
231-459: A processor , memory , and other major system components that operate on data in 32- bit units. Compared to smaller bit widths, 32-bit computers can perform large calculations more efficiently and process more data per clock cycle. Typical 32-bit personal computers also have a 32-bit address bus , permitting up to 4 GB of RAM to be accessed, far more than previous generations of system architecture allowed. 32-bit designs have been used since
308-605: A "fully qualified 10 MHz TI32000 32-bit microprocessor chip set" consisting of the TI32016 CPU and TI32082 memory management unit as 48-pin devices, the TI32201 timing control unit and TI32081 floating-point unit as 24-pin devices, and the TI32202 interrupt control unit as a 40-pin device, with the five-device chipset "priced at $ 289 in 100-unit quantities". National changed its design methodology to make it possible to get
385-492: A fairly simple superscalar design to be located after the (fairly complex) decoders (and buffers), giving, so to speak, the best of both worlds in many respects. This technique is also used in IBM z196 and later z/Architecture microprocessors. The terms CISC and RISC have become less meaningful with the continued evolution of both CISC and RISC designs and implementations. The first highly (or tightly) pipelined x86 implementations,
462-420: A larger subset of instructions in a pipelined (overlapping) fashion, and facilitates more advanced extraction of parallelism out of the code stream, for even higher performance. Contrary to popular simplifications (present also in some academic texts,) not all CISCs are microcoded or have "complex" instructions. As CISC became a catch-all term meaning anything that's not a load–store (RISC) architecture, it's not
539-526: A mirror surface. HDR imagery allows for the reflection of highlights that can still be seen as bright white areas, instead of dull grey shapes. A 32-bit file format is a binary file format for which each elementary information is defined on 32 bits (or 4 bytes ). An example of such a format is the Enhanced Metafile Format . Complex instruction set computer A complex instruction set computer ( CISC / ˈ s ɪ s k / )
616-449: A processor which in many ways is reminiscent in structure to very early CPU designs. In the early 1970s, this gave rise to ideas to return to simpler processor designs in order to make it more feasible to cope without ( then relatively large and expensive) ROM tables and/or PLA structures for sequencing and/or decoding. An early (retroactively) RISC- labeled processor ( IBM 801 – IBM 's Watson Research Center, mid-1970s)
693-445: A report in a June 1983 publication, however, it was remarked that National was "promising production quantities this summer" of 16032 parts, having been "shipping sample quantities for several months", with the floating point co-processor sampling "this month". Although a 1982 introduction post-dates the 68k by about two years, the 68k was not yet being widely used in the market and the 32016 generated significant interest. Unfortunately,
770-415: A sequence of simpler instructions. One reason for this was that architects ( microcode writers) sometimes "over-designed" assembly language instructions, including features that could not be implemented efficiently on the basic hardware available. There could, for instance, be "side effects" (above conventional flags), such as the setting of a register or memory location that was perhaps seldom used; if this
847-543: A series of related support chips like the NS32081 floating point unit (FPU), NS32082 memory management unit (MMU), NS32203 direct memory access (DMA) and NS32202 interrupt controllers . With the full set plus memory chips and peripherals, it was feasible to build a 32-bit computer system capable of supporting modern multi-tasking operating systems, something that had previously been possible only on expensive minicomputers and mainframes . In 1985, National Semi introduced
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#1732790247763924-459: A series of special-purpose registers: (Additional system registers not listed). The instruction set is very much in the CISC model, with 2-operand instructions, memory-to-memory operations, flexible addressing modes , and variable-length byte-aligned instruction encoding. Addressing modes can involve up to two displacements and two memory indirections per operand as well as scaled indexing, making
1001-413: A total of 96 bits per pixel. 32-bit-per-channel images are used to represent values brighter than what sRGB color space allows (brighter than white); these values can then be used to more accurately retain bright highlights when either lowering the exposure of the image or when it is seen through a dark filter or dull reflection. For example, a reflection in an oil slick is only a fraction of that seen in
1078-440: Is a computer architecture in which single instructions can execute several low-level operations (such as a load from memory , an arithmetic operation , and a memory store) or are capable of multi-step operations or addressing modes within single instructions. The term was retroactively coined in contrast to reduced instruction set computer (RISC) and has therefore become something of an umbrella term for everything that
1155-402: Is a 32-bit machine, with 32-bit registers and instructions that manipulate 32-bit quantities, but the external address bus is 36 bits wide, giving a larger address space than 4 GB, and the external data bus is 64 bits wide, primarily in order to permit a more efficient prefetch of instructions and data. Prominent 32-bit instruction set architectures used in general-purpose computing include
1232-521: Is not RISC, where the typical differentiating characteristic is that most RISC designs use uniform instruction length for almost all instructions, and employ strictly separate load and store instructions. Examples of CISC architectures include complex mainframe computers to simplistic microcontrollers where memory load and store operations are not separated from arithmetic instructions. Specific instruction set architectures that have been retroactively labeled CISC are System/360 through z/Architecture ,
1309-606: The 8088/8086 or 80286 , 16-bit microprocessors with a segmented address space where programs had to switch between segments to reach more than 64 kilobytes of code or data. As this is quite time-consuming in comparison to other machine operations, the performance may suffer. Furthermore, programming with segments tend to become complicated; special far and near keywords or memory models had to be used (with care), not only in assembly language but also in high level languages such as Pascal , compiled BASIC , Fortran , C , etc. The 80386 and its successors fully support
1386-769: The IBM System/360 , IBM System/370 (which had 24-bit addressing), System/370-XA , ESA/370 , and ESA/390 (which had 31-bit addressing), the DEC VAX , the NS320xx , the Motorola 68000 family (the first two models of which had 24-bit addressing), the Intel IA-32 32-bit version of the x86 architecture, and the 32-bit versions of the ARM , SPARC , MIPS , PowerPC and PA-RISC architectures. 32-bit instruction set architectures used for embedded computing include
1463-551: The IBM System/360 Model 30 had an 8-bit ALU, 8-bit internal data paths, and an 8-bit path to memory, and the original Motorola 68000 had a 16-bit data ALU and a 16-bit external data bus, but had 32-bit registers and a 32-bit oriented instruction set. The 68000 design was sometimes referred to as 16/32-bit . However, the opposite is often true for newer 32-bit designs. For example, the Pentium Pro processor
1540-654: The Microchip Technology PIC has been labeled RISC in some circles and CISC in others. Before the RISC philosophy became prominent, many computer architects tried to bridge the so-called semantic gap , i.e., to design instruction sets that directly support high-level programming constructs such as procedure calls, loop control, and complex addressing modes , allowing data structure and array accesses to be combined into single instructions. Instructions are also typically highly encoded in order to further enhance
1617-813: The PDP-11 and VAX architectures, and many others. Well known microprocessors and microcontrollers that have also been labeled CISC in many academic publications include the Motorola 6800 , 6809 and 68000 families; the Intel 8080 , iAPX 432 , x86 and 8051 families; the Zilog Z80 , Z8 and Z8000 families; the National Semiconductor NS320xx family; the MOS Technology 6502 family; and others. Some designs have been regarded as borderline cases by some writers. For instance,
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#17327902477631694-544: The Pentium . The Pentium internal microarchitecture is similar to the preceding Swordfish. The focus of Swordfish was high-end PostScript laser printers , and performance was exceptional at the time. Competing solutions could render about one new page per minute, but the Swordfish demo unit would print out sixteen pages per minute, limited only by the laser-engine mechanics. On each page it would print out how much time it
1771-459: The VAX-11 architecture. The VAX is well known for its highly "orthogonal" instruction set architecture (ISA), in which any instruction can be applied to any data. For instance, an ADD instruction might add the contents of two processor registers , or one register against a value in memory, two values in memory, or use the register as an offset against an address. This flexibility was considered
1848-519: The central processing unit (CPU) space. Instead, the basic 32000 architecture was combined with several support systems and relaunched as the Swordfish microcontroller . This had some success in the market before it was replaced by the CompactRISC architecture in mid-1990s. The NS32000 series traces its history to an effort by National Semiconductor to produce a single-chip implementation of
1925-448: The integer representation used. With the two most common representations, the range is 0 through 4,294,967,295 (2 − 1) for representation as an ( unsigned ) binary number , and −2,147,483,648 (−2 ) through 2,147,483,647 (2 − 1) for representation as two's complement . One important consequence is that a processor with 32-bit memory addresses can directly access at most 4 GiB of byte-addressable memory (though in practice
2002-533: The 16-bit segments of the 80286 but also segments for 32-bit address offsets (using the new 32-bit width of the main registers). If the base address of all 32-bit segments is set to 0, and segment registers are not used explicitly, the segmentation can be forgotten and the processor appears as having a simple linear 32-bit address space. Operating systems like Windows or OS/2 provide the possibility to run 16-bit (segmented) programs as well as 32-bit programs. The former possibility exists for backward compatibility and
2079-511: The 1970s, analysis of high-level languages indicated compilers produced some complex corresponding machine language. It was determined that new instructions could improve performance. Some instructions were added that were never intended to be used in assembly language but fit well with compiled high-level languages. Compilers were updated to take advantage of these instructions. The benefits of semantically rich instructions with compact encodings can be seen in modern processors as well, particularly in
2156-710: The 200,000 transistor MC68020. The NS32CG160 is the CG16 with timers and DMA peripherals, while the NS32FV/FX16x chips have extra DSP functionality on top of the CG16 BitBLT core for the fax and answering machine market. They are complemented by the NS32532 based NS32GX32 later. Unlike the previous chips, there was no extra hardware. The NS32GX32 is the NS32532 without the MMU sold at an attractive price for embedded system. In
2233-430: The 24-bit address bus . By sharing pins, external hardware had to latch the address for the memory address while the pins were used in data mode, and this introduces a 1-cycle delay in every access. So while the internal 32-bit implementation improves performance, the small pin-count decreases it again. It may have been the first 32-bit chip to reach mass production and sale (at least according to National's marketing). In
2310-487: The 32016 to perform those arithmetic operations. However, the 32016 contained many bugs and often could not be run at its rated speed. These problems, and the presence of the otherwise similar 68000 which had been available since 1980, led to little use in the market despite considerable early interest. Several improved versions followed, including 1985's 32032 which was essentially a bug-fixed 32016 with an external 32-bit data bus. While it offered about 50% better speed than
2387-439: The 32016, it was outperformed by the 32-bit Motorola 68020 , released a year prior. The 32532 , released in 1987, outperformed the contemporary Motorola 68030 by almost two times, but by this time most interest in microprocessors had turned to RISC platforms and this otherwise excellent design saw almost no use as well. National was working on further improvements in the 32732 , but eventually gave up attempting to compete in
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2464-546: The 486 designs from Intel , AMD , Cyrix , and IBM , supported every instruction that their predecessors did, but achieved maximum efficiency only on a fairly simple x86 subset that was only a little more than a typical RISC instruction set (i.e., without typical RISC load–store limits). The Intel P5 Pentium generation was a superscalar version of these principles. However, modern x86 processors also (typically) decode and split instructions into dynamic sequences of internally buffered micro-operations , which helps execute
2541-423: The 68000 family and ColdFire , x86, ARM, MIPS, PowerPC, and Infineon TriCore architectures. On the x86 architecture , a 32-bit application normally means software that typically (not necessarily) uses the 32-bit linear address space (or flat memory model ) possible with the 80386 and later chips. In this context, the term came about because DOS , Microsoft Windows and OS/2 were originally written for
2618-528: The CISC category . because they have "load-operate" instructions that load and/or store memory contents within the same instructions that perform the actual calculations. For instance, the PDP-8, having only 8 fixed-length instructions and no microcode at all, is a CISC because of how the instructions work, PowerPC, which has over 230 instructions (more than some VAXes), and complex internals like register renaming and
2695-574: The NS32032 was as part of a "fault-tolerant transaction system" employing "two 32032s in parallel and comparing results on alternate memory cycles to detect soft errors". The NS32132 chip allows a pair of CPUs to be connected to the same memory system, without much change of the PCB. Prototype systems were built by Diab Data AB in Sweden , but did not perform as well as the single-CPU MC68020 system designed by
2772-483: The NS32332, a much-improved version of the 32032. From the datasheet, the enhancements include "the addition of new dedicated addressing hardware (consisting of a high speed ALU, a barrel shifter and an address register), a very efficient increased (20 bytes) instruction prefetch queue, a new system/memory bus interface/protocol, increased efficiency slave processor protocol and finally enhancements of microcode." There
2849-471: The NS32732 called Swordfish was aimed at embedded systems and arrived in about 1990. Swordfish has an integrated floating point unit, timers, DMA controllers and other peripherals not normally available in microprocessors. It has a 64-bit data bus and is internally overclocked from 25 to 50 MHz. The chief architect of the Swordfish is Donald Alpert , who went on to manage the architectural team designing
2926-561: The NS32CG16 should be noted. The key difference between this and the NS32C016 is the integration of the expensive timing control unit (TCU) which generates the needed two-phase clock from a crystal, and the removal of the floating point coprocessor support, which freed up microcode space for the useful BitBLT instruction set, which significantly improves the performance in laser printer operations, making this 60,000 transistor chip faster than
3003-719: The University of Michigan to develop the first synthesizable Verilog Model, and Verilog was used from the CR16C and onwards. Versions of the older NS32000 line for low-cost products such as the NS32CG16, NS32CG160, NS32FV16, NS32FX161, NS32FX164 and the NS32AM160/1/3, all based on the NS302CG16 were introduced from 1987 and onwards. These processors had some success in the laser printer and fax market, despite intense competition from AMD and Intel RISC chips. Especially
3080-438: The aim of higher throughput at lower cost and also allowed high-level language constructs to be expressed by fewer instructions, it was observed that this was not always the case. For instance, low-end versions of complex architectures (i.e. using less hardware) could lead to situations where it was possible to improve performance by not using a complex instruction (such as a procedure call or enter instruction) but instead using
3157-440: The basic structure of RISC processors. The CDC 6600 supercomputer, first delivered in 1965, has also been retroactively described as RISC. It had a load–store architecture which allowed up to five loads and two stores to be in progress simultaneously under programmer control. It also had multiple function units which could operate at the same time. In a more modern context, the complex variable-length encoding used by some of
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3234-430: The beginning, this was just a remarked chip. It is unclear if the chip was redesigned for lower-cost production. Datasheets exist for an NS32132, apparently designed for multiprocessor systems. This is the NS32032 extended with an arbiter. The bus usage of the NS32032 is about 50 percent, owing to its very compact instruction set, or its very slow pipeline as competitors would phrase it. Indeed, one suggested application of
3311-621: The code density. The compact nature of such instruction sets results in smaller program sizes and fewer main memory accesses (which were often slow), which at the time (early 1960s and onwards) resulted in a tremendous saving on the cost of computer memory and disc storage, as well as faster execution. It also meant good programming productivity even in assembly language , as high level languages such as Fortran or Algol were not always available or appropriate. Indeed, microprocessors in this category are sometimes still programmed in assembly language for certain types of critical applications. In
3388-526: The code, although this is strongly mediated by the fast cache structures used in modern designs, as well as by other measures. Due to inherently compact and semantically rich instructions, the average amount of work performed per machine code unit (i.e. per byte or bit) is higher for a CISC than a RISC processor, which may give it a significant advantage in a modern cache-based implementation. Transistors for logic, PLAs, and microcode are no longer scarce resources; only large high-speed cache memories are limited by
3465-490: The earliest days of electronic computing, in experimental systems and then in large mainframe and minicomputer systems. The first hybrid 16/32-bit microprocessor , the Motorola 68000 , was introduced in the late 1970s and used in systems such as the original Apple Macintosh . Fully 32-bit microprocessors such as the HP FOCUS , Motorola 68020 and Intel 80386 were launched in the early to mid 1980s and became dominant by
3542-722: The early 1990s. This generation of personal computers coincided with and enabled the first mass-adoption of the World Wide Web . While 32-bit architectures are still widely-used in specific applications, the PC and server market has moved on to 64 bits with x86-64 and other 64-bit architectures since the mid-2000s with installed memory often exceeding the 32-bit 4G RAM address limits on entry level computers. The latest generation of smartphones have also switched to 64 bits. A 32-bit register can store 2 different values. The range of integer values that can be stored in 32 bits depends on
3619-533: The early versions were filled with bugs and could rarely be run at their rated speed. By 1984, after two years, the errata list still contained items specifying uncontrollable conditions that would result in the processor coming to a halt, forcing a reset. The original product roadmap envisaged 6 MHz and 10 MHz parts during 1983 and 12 MHz and 14 MHz parts during 1984. However, press reports in 1984 indicated difficulties in keeping to this roadmap, with it reportedly having taken five months to increase
3696-524: The existing NS32381 or the NS32580 interface to a Weitek FPA. The NS32532 was the basis of the PC532 , a "public domain" hardware project, and one of the few to produce a useful machine running a real operating system (in this case, Minix or NetBSD ). The semi-mythical NS32732 (sometimes called NS32764), envisioned as the high-performance successor to the NS32532, never came to the market. A derivative of
3773-574: The first decades of 32-bit architectures (the 1960s to the 1980s). Older 32-bit processor families (or simpler, cheaper variants thereof) could therefore have many compromises and limitations in order to cut costs. This could be a 16-bit ALU , for instance, or external (or internal) buses narrower than 32 bits, limiting memory size or demanding more cycles for instruction fetch, execution or write back. Despite this, such processors could be labeled 32-bit , since they still had 32-bit registers and instructions able to manipulate 32-bit quantities. For example,
3850-516: The frequency of the parts from 6 MHz to 8 MHz, and with representatives estimating a further "two, three or five months" to increase the frequency to 10 MHz. Two unspecified chips of the five in the chipset were reported to be the cause of these problems. An early 1985 article about the 32016-based Whitechapel MG-1 workstation noted that the 32081 memory management unit was "suffering from bugs" and had been situated on its own board providing hardware fixes. In 1986, Texas Instruments announced
3927-419: The high-performance segment where caches are a central component (as opposed to most embedded systems ). This is because these fast, but complex and expensive, memories are inherently limited in size, making compact code beneficial. Of course, the fundamental reason they are needed is that main memories (i.e., dynamic RAM today) remain slow compared to a (high-performance) CPU core. While many designs achieved
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#17327902477634004-414: The internal implementation with a five-stage pipeline, an integrated Cache/MMU and improved memory performance, making it about twice as performant as the competing MC68030 and i80386 . At this stage RISC architectures were starting to make inroads, and the main competitors became the now equally dead AM29000 and MC88000 , which was considered faster than the NS32532. For floating-point, the NS32532 used
4081-412: The latter is usually meant to be used for new software development . In digital images/pictures, 32-bit usually refers to RGBA color space ; that is, 24-bit truecolor images with an additional 8-bit alpha channel . Other image formats also specify 32 bits per pixel, such as RGBE . In digital images, 32-bit sometimes refers to high-dynamic-range imaging (HDR) formats that use 32 bits per channel,
4158-468: The limit may be lower). The world's first stored-program electronic computer , the Manchester Baby , used a 32-bit architecture in 1948, although it was only a proof of concept and had little practical capacity. It held only 32 32-bit words of RAM on a Williams tube , and had no addition operation, only subtraction. Memory, as well as other digital circuits and wiring, was expensive during
4235-477: The longest conceivable instruction 23 bytes. The actual number of instructions is much lower than that of contemporary RISC processors. Unlike some other processors, automatic increment of the base register is not provided; the only exception is a "top of stack" addressing modes that pop sources and push destinations. Uniquely, the size of the displacement is encoded in its most significant bits: 0, 10 and 11 preceded 7-, 14- and 30-bit signed displacements. (Although
4312-499: The market, notably the Apple Macintosh , and the 32016 never saw widespread use. The 32016 has a 16-bit external data bus , a 24-bit external address bus , and a full 32-bit instruction set . It also includes a coprocessor interface, allowing coprocessors such as FPUs and MMUs to be attached as peers to the main processor. The MMU is based on demand paging virtual memory, which is the most unusual feature compared to
4389-462: The maximum number of transistors today. Although complex, the transistor count of CISC decoders do not grow exponentially like the total number of transistors per processor (the majority typically used for caches). Together with better tools and enhanced technologies, this has led to new implementations of highly encoded and variable-length designs without load–store limitations (i.e. non-RISC). This governs re-implementations of older architectures such as
4466-444: The number of instructions, nor the complexity of the implementation or of the instructions, that define CISC, but that arithmetic instructions also perform memory accesses. Compared to a small 8-bit CISC processor, a RISC floating-point instruction is complex. CISC does not even need to have complex addressing modes; 32- or 64-bit RISC processors may well have more complex addressing modes than small 8-bit CISC processors. A PDP-10 ,
4543-608: The overall processing task, was only 16-bit. This meant it had to cycle 32-bit data through the ALU twice—in two 16-bit halves—to complete a 32-bit operation. In contrast, the NS32000 has a 32-bit ALU, so that 32-bit and 16-bit instructions take the same time to complete. The 32016 first shipped in 1982 in a 46-pin DIP package. To fit a 32-bit chip into a 46-pin package required the data bus to be 16-bits wide, and to share pins with
4620-671: The paragon of design in the era of complex instruction set computers (CISC). National took Digital Equipment Corporation (DEC) to court in California to ensure the legality of the design, but when DEC had the lawsuit moved to Massachusetts , DEC's home state, the lawsuit was dropped and the Series 32000 architecture was developed instead. Although the new instruction set architecture was not VAX-11 compatible, it did retain its highly " orthogonal " design philosophy. That is, every instruction could be used with any type of data. Articles of
4697-487: The part into production and a design system based on the language "Z" was co-developed with the University of Tel-Aviv, close to the "NSC" design centre in Herzliya , Israel. The "Z" language is similar to today's Verilog and VHDL , but has a Pascal-like syntax and is optimized for two-phase clock designs. However, by the times the fruit of these efforts were being felt in the design, numerous 68k machines were already on
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#17327902477634774-456: The part of the processor designer in cases where a simpler, but (typically) slower, solution based on decode tables and/or microcode sequencing is not appropriate. At a time when transistors and other components were a limited resource, this also left fewer components and less opportunity for other types of performance optimizations. The circuitry that performs the actions defined by the microcode in many (but not all) CISC processors is, in itself,
4851-668: The processors are otherwise consistently little-endian, displacements in the instruction stream are stored in big-endian order). General-purpose operands are specified using a 5-bit field. To this can be added an index byte (specifying the index register and 5-bit base address), and up to 2 variable-length displacements per operand. The first chip in the series was originally referred to as the 16032, but later renamed 32016 to emphasize its 32-bit internals. This contrasts it with its primary competitor in this space, 1979's Motorola 68000 (68k). The 68k used 32-bit instructions and registers, but its arithmetic logic unit (ALU), which controls much of
4928-427: The same company. In June 2015, Udo Möller released a complete Verilog implementation of an NS32000 processor on OpenCores . Fully software-compatible with an NS32532 CPU with N32381 FPU, it is significantly faster when implemented on an FPGA , both operating at a higher clock rate and using fewer cycles per instruction. 32-bit In computer architecture , 32-bit computing refers to computer systems with
5005-474: The segmented memory approach used by the competition, and has become the standard for how microprocessors are designed today. The architecture supports an instruction restart mechanism on a page fault, which is much cleaner than the Motorola approach to dump the internal status on a page fault, which has to be read back, before the instruction is continued. While often compared to the 68k's instruction set, this
5082-520: The time also referred to this as "symmetrical". The original processor family consisted of the NS16032 CPU and a NS16C032 low-power variant, both having a 16-bit data path and so requiring two machine cycles to load a single 32-bit word. Both could be used with the NS16082 memory management unit (MMU), which provided 24-bit virtual memory support for up to 16 MB physical memory. The NS16008
5159-414: The typical CISC architectures makes it complicated, but still feasible, to build a superscalar implementation of a CISC programming model directly ; the in-order superscalar original Pentium and the out-of-order superscalar Cyrix 6x86 are well-known examples of this. The frequent memory accesses for operands of a typical CISC machine may limit the instruction-level parallelism that can be extracted from
5236-411: The ubiquitous x86 (see below) as well as new designs for microcontrollers for embedded systems , and similar uses. The superscalar complexity in the case of modern x86 was solved by converting instructions into one or more micro-operations and dynamically issuing those micro-operations, i.e. indirect and dynamic superscalar execution; the Pentium Pro and AMD K5 are early examples of this. It allows
5313-515: Was a cut-down version with an 8-bit external data path and no virtual memory support, which had a reduced pin count and was thus somewhat easier to implement. Both the NS16008 and NS16016 were to feature an emulation mode for the Intel 8080 running at four times the speed of that processor. At the same time, National Semiconductor also announced two future versions, the NS32032 and NS32132. The former
5390-458: Was a tightly pipelined simple machine originally intended to be used as an internal microcode kernel, or engine, in CISC designs, but also became the processor that introduced the RISC idea to a somewhat larger audience. Simplicity and regularity also in the visible instruction set would make it easier to implement overlapping processor stages ( pipelining ) at the machine code level (i.e. the level seen by compilers). However, pipelining at that level
5467-403: Was already used in some high-performance CISC "supercomputers" in order to reduce the instruction cycle time (despite the complications of implementing within the limited component count and wiring complexity feasible at the time). Internal microcode execution in CISC processors, on the other hand, could be more or less pipelined depending on the particular design, and therefore more or less akin to
5544-466: Was also a new NS32382 MMU, NS32381 FPU and the (very rare) NS32310 interface to a Weitek FPA. The aggregate performance boost of the NS32332 from these enhancements only made it 50 percent faster than the original NS32032, and therefore less than that of the main competitor, the MC68020 . National Semi introduced the NS32532 in early 1987. Running at 20-, 25- & 30-MHz, it was a complete redesign of
5621-406: Was done via ordinary (non duplicated) internal buses, or even the external bus, it would demand extra cycles every time, and thus be quite inefficient. Even in balanced high-performance designs, highly encoded and (relatively) high-level instructions could be complicated to decode and execute efficiently within a limited transistor budget. Such architectures therefore required a great deal of work on
5698-577: Was essentially a version of the NS16032 with a 32-bit external data bus, allowing it to read data at twice the rate. This was project to be released in 1984. The NS32132 was a version with a 29-bit internal addresses and 32-bit external, allowing it to address a complete 4 GB of memory. It was to be released in 1985. All of these could also be used with the NS16081 floating-point unit (FPU). The processors have 8 general-purpose 32-bit registers, plus
5775-586: Was idling, waiting for the engine to complete. The Swordfish die is huge, and it was eventually decided to drop the project altogether, and the product never went into production. The lessons from the Swordfish were used for the CompactRISC designs. In the beginning, there were both a CompactRISC-32 and a CompactRISC-16, designed using "Z". National never brought a chip to the market with the CompactRISC-32 core. National's Research department worked with
5852-510: Was introduced in 1984. It is almost completely compatible with the 32016, but features a 32-bit data bus (although keeping the 24-bit address bus) for somewhat faster performance, described as "minicomputer performance" comparable with that of a VAX-11 system. There was also a 32008, a 32016 with a data bus cut down to 8-bits wide for low-cost applications. It is philosophically similar to the MC68008 , and equally unpopular. National also produced
5929-439: Was rejected by NSC employees; one of the key marketing phrases of the time was "Elegance is Everything", comparing the highly orthogonal Series 32000 to the "kludge". One key difference is Motorola's use of address registers and data registers, with instructions only working on either address or data registers. The Series 32000 has general-purpose registers, described as "address-data" registers in technical documentation. The 32032
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